CTNF 18/411,748 CTNF 91895 2842 DETAILED ACTION 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries set forth in Graham v. John Deere Co. , 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim 1 is rejected under 35 U.S.C. § 103 as being unpatentable over Self (Distortion in Power Amplifiers, article published in Sept. 1993, Electronics World + Wireless World, and is cited by the applicant) in view of the common knowledge of the person having ordinary skill in the art regarding the functional equivalence of transistor types . Regrading Claim 1 , Self teaches a differential pair comprising a first and a second branch having a common first node. Specifically, Self discloses a differential input pair (Tr2 and Tr3) where the emitters of both transistors are tied together at a common node. Self teaches that each of the first and second branches comprises at least one transistor (Tr2, Tr3) having a conduction node (the emitter) directly connected to said common first node. Furthermore, Self teaches a third branch coupling said common first node to a power supply node (e.g., the tail current branch coupling the emitters to the V+ or V- rail). Self discloses wherein said third branch comprises a current source in series with a resistive element; for example, the tail branch utilizes a current source transistor (Tr1) in series with a 1k resistor (R1) connected to the power supply. Finally, Self teaches a capacitor having a first terminal coupled to the control terminal of the at least one transistor of the second branch and a second terminal coupled to ground, as clearly illustrated in Figure 4 where a 100pF capacitor is connected between the base of Tr3 and ground. PNG media_image1.png 287 451 media_image1.png Greyscale (Self) Self utilizes Bipolar Junction Transistors (BJTs) throughout its circuit diagrams, which possess "bases," "emitters," and "collectors". The claim explicitly requires the capacitor to be coupled to a " gate " of the transistor. Therefore, Self does not strictly disclose a capacitor coupled to the "gate" of the second branch transistor. It is well-established common knowledge in the field of electrical engineering and amplifier design that Field Effect Transistors (FETs) and Bipolar Junction Transistors (BJTs) are functionally equivalent semiconductor switching and amplifying devices. A person of ordinary skill in the art recognizes that a FET's "gate" is the direct structural and functional equivalent to a BJT's "base" (both acting as the control terminal of the transistor). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the differential pair circuit taught by Self by substituting the BJT transistors (Tr2, Tr3) with art-equivalent FET transistors. By making this standard component substitution, the 100pF capacitor taught by Self would be directly coupled to the "gate" of the second branch transistor, completely reading on the claimed limitation. The motivation to substitute FETs for BJTs (or vice versa) in a differential amplifier is a routine design choice driven by well-known trade-offs in circuit characteristics, such as achieving higher input impedance, virtually eliminating input bias current errors, or adjusting the noise profile of the input stage. A person of ordinary skill in the art would recognize that substituting the BJTs in Self's circuit with equivalent FETs involves mere substitution of known equivalents, yielding the predictable result of a stabilized differential input pair that functions identically in routing the feedback signal to the inverting input's control terminal . 07-21-aia AIA Claim 1-7, 9-14 are rejected under 35 U.S.C. 103 as being unpatentable over Lim (US 2006/0119429) in view of Self (cited by the applicant) . Regarding claim 1 , Lim teaches a differential pair, comprising a first and a second branches having a common first node. Specifically, Lim discloses an NMOS differential pair comprising a first branch with transistor Mn1 and a second branch with transistor Mn2, where their sources share a common node. Lim teaches that each of the first and second branches comprises at least one transistor (Mn1, Mn2) having a conduction node (the source) directly connected to said common first node. PNG media_image2.png 574 823 media_image2.png Greyscale Fig. 3a of Lim representing differential amplifier. Furthermore, Lim teaches a third branch coupling said common first node to a power supply node (gnda, representing the negative rail or ground). Lim discloses wherein said third branch comprises a current source in series with a resistive element, specifically showing tail current source transistor Mb2 in series with resistive element Rb2. Because Lim utilizes Field Effect Transistors (FETs), it inherently teaches transistors possessing a "gate". Lim does not explicitly disclose a capacitor having a first terminal coupled to a gate of the at least one transistor of the second branch and a second terminal coupled to ground. Self, which is in the same field of endeavor (audio amplifier differential input stage design), teaches the missing limitation. Specifically, Self discloses a differential input pair (Tr2 and Tr3) wherein a capacitor is coupled directly between the control terminal (the base) of the second branch transistor (Tr3) and ground. This is clearly illustrated in Figure 3a of Self, which shows a capacitor in parallel with a 22k resistor connected from the base of Tr3 to the ground reference. While Self utilizes Bipolar Junction Transistors (BJTs) which have "bases," a person of ordinary skill in the art recognizes this as the direct functional equivalent to a FET "gate" serving as the control terminal of the transistor. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the differential pair of Lim by adding a capacitor having a first terminal coupled to the gate of the second branch transistor (e.g., Mn2) and a second terminal coupled to ground, as taught by the differential pair configuration in Self. The motivation to combine the teachings of Self into the circuit of Lim is to properly stabilize the feedback network and set appropriate AC/DC conditions for the inverting input of the differential pair. As demonstrated by Self, placing a capacitor from the control terminal (base/gate) of the feedback-receiving transistor to ground provides an AC ground path and high-frequency roll-off, which prevents unwanted high-frequency noise or radio-frequency interference from entering the feedback loop, while also ensuring proper closed-loop stability of the amplifier stage. A person of ordinary skill in the art would recognize that adding Self's stabilizing capacitor to the gate of Lim's second branch transistor is a standard and predictable design choice that yields the predictable result of improved high-frequency stability in a differential amplifier. Regarding Claims 4, 6, 9, 10, 11, 12, 13, and 14 , ( These claims merely recite specific components and topologies already explicitly disclosed in the primary reference, Lim). In addition to the base limitations of claim 1, Lim explicitly teaches the additional limitations of these dependent claims. Claim 4: Lim discloses that the resistive element is a resistor, shown as Rb1 and Rb2. Claim 6: Lim discloses the current source is a MOS transistor, specifically PMOS Mb1 and NMOS Mb2. Claims 9 & 10: For the NMOS pair, Lim teaches the power supply node is a ground/negative rail (gnda) and the current source is an NMOS transistor (Mb2). Claims 11, 12, 13 & 14: For the PMOS pair, Lim teaches the power supply node is a voltage supply rail (vdda), the current source is a PMOS transistor (Mb1), the differential branch transistors are PMOS (Mp1, Mp2), and their conduction nodes connected to the common first node are their sources . Lim, however, does not teach the stabilizing capacitor on the gate of the second branch transistor to ground (the base limitation of Claim 1). Self teaches the missing capacitor coupled between the control terminal of the second branch transistor and ground. It would have been obvious to modify Lim's differential pairs by adding Self's grounding capacitor to the gate of the second branch transistor. To properly stabilize the feedback network and prevent unwanted high-frequency noise from entering the inverting input of the differential pair, as is standard practice. Regarding Claims 2 and 3 (Resistor Values > 100 Ohms and > 1 k W ) Lim teaches using a resistive element (Rb1, Rb2) in the tail branch but does not explicitly disclose its numerical resistance value. Lim does not teach that the resistance value is greater than 100 Ohms or greater than 1 k W . Self, in the same field of endeavor, explicitly teaches tail branch resistive elements having values of exactly 1 k W (R1) or greater (e.g., 2.2 k W , 10 k W ). It would have been obvious to select a resistance value greater than 100 Ohms or greater than 1 k W for Lim's resistive elements (Rb1/Rb2), as explicitly taught by Self. To provide adequate degeneration and tail current control to stabilize the differential pair's operating point and improve linearity, a well-known benefit of sizing tail resistors in the kilo-ohm range. Regarding Claim 5 (Resistive Element is a MOS Transistor) Lim teaches a resistive element (Rb1, Rb2) but portrays it as a standard passive resistor. Lim, however, does not explicitly teach replacing the passive resistor with a MOS transistor. It is textbook common knowledge in the art of CMOS integrated circuit design to implement a "resistive element" using a MOS transistor biased in the triode (linear) region to act as a voltage-controlled resistor. It would have been obvious to a person of ordinary skill in the art to implement Lim's resistive elements (Rb1/Rb2) as MOS transistors operating in the triode region. To save physical die area on a CMOS integrated circuit (since passive resistors consume large amounts of silicon space) and to allow the resistance value to be easily tuned via a bias voltage. Regarding Claim 7 (Power Supply -> Current Source -> Resistor -> Common Node), Lim teaches this exact topology for its PMOS differential pair. Specifically, the power supply node (vdda) connects to a first conduction node (source) of the current source transistor (Mb1). The second conduction node (drain) of Mb1 is coupled via the resistive element (Rb1) to the common first node (the sources of Mp1, Mp2). 2-5. The claim is rejected under § 103 for the exact same reasons as Claim 1 (Lim in view of Self), as Lim already teaches the additional structural arrangement of this dependent claim . 07-21-aia AIA Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Lim (US 2006/0119429) in view of Self (cited by the applicant) and further in view of Naito . Regarding Claim 8 (Common Node -> Current Source -> Resistor -> Power Supply), Lim's NMOS pair utilizes a different topology: Common Node -> Resistor (Rb2) -> Current Source (Mb2) -> Ground. Lim, however, does not teach placing the current source between the common node and the resistor. Naito (US 2008/0143441), in the same field of endeavor, explicitly teaches this exact topology. In Naito's Fig. 3, the differential pair DP4 (M28, M30) has a common first node connected to a conduction node (drain) of the current source transistor M32. The other conduction node (source) of M32 is coupled by the resistive element R10 to the power supply node (ground via B2). It would have been obvious to modify Lim's NMOS tail branch topology to match the topology taught by Naito (placing the current source transistor above the resistive element). Naito teaches that this specific arrangement (variable current source M32 in series with a source degeneration resistor R10) allows for variable tail current control while using the resistor to stabilize the current source and precisely adjust the distortion-canceling point of the amplifier. Allowable Subject Matter 07-43 Claim 15 is objected to as being dependent upon a rejected base claim 1 but would be allowable if rewritten in independent form including all the limitations of the base claim 1 and any intervening claims. Claim 15 is allowable because Claim 15 requires that the transistors of the first and second branches are NMOS transistors and have their drains connected to the first node (the common tail node). In standard differential pair architectures—including every single embodiment shown in Lim, Self, and Naito—the transistors have their sources (or emitters for BJTs) tied together at the common tail node. Tying the drains of an NMOS pair to the common tail node fundamentally destroys the differential steering mechanism of the circuit (it would sum currents rather than steer them differentially based on Vgs. None of the cited references teach, suggest, or provide any motivation to connect the drains of an NMOS differential pair to the common tail node. Because this specific structural arrangement is completely absent from the prior art of record, claim 15 is allowable. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAFIZUR RAHMAN whose telephone number is (571)270-0659. The examiner can normally be reached M-F: 10-6. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached on (571) 272-2078 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HAFIZUR RAHMAN/Primary Examiner, Art Unit 2843. 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