Detailed Office Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restriction
Applicant’s election without traverse of claims 1-8 in the reply filed on 6 February 2026 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 3-8
Claims 11 and 3-8 are rejected under 35 U.S.C. 103 as being unpatentable over Kotb et al, All-optical latches using carrier reservoir semiconductor optical amplifiers, Optics & Laser Technology, Volume 157, 2023, 108737, ISSN 0030-3992; “Kotb”) in view of Vivero et al. (2R-Regeneration in a monolithically integrated four-section SOA-EA chip, Optics Communications, vol.282, no.1, pp.117, 2009; “Vivero”) and further in view of Shahar et al. (2004/0184750; “Shahar”).
Regarding claim 1, Kotb discloses in figure 4, and related figures and text, an optical flip-flop circuit comprising logical gates which, in turn, comprise networks of Semiconductor Optical Amplifiers (SOA). Kotb, figure 4, and related figures and text (“The D Flip-Flop is a common building component for logic functions. A memory cell, a zero-order hold, or a delay line can all be used to describe the D Flip-Flop. It captures the value of the data input D at a definite portion of the gate cycle, resulting in the output Q. At other times instants when D = ‘1′ and G = ‘0′ , the output Q does not change; Q remains ’0′ or ’1′ based on the previous output state. Two logic functions NAND and NOT are used to build the D Flip-Flop. The diagrams and the truth table of D Flip-Flop using CR-SOAs-MZIs are shown in Fig. 4.”).
Kotb – Figure 4 and Selected Text
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Concurrently a continuous wave (CW) beam at 1550 is injected into both CR-SOA3 and CR-SOA4 from port 7 to map the gain dynamics perturbation and convert it to amplitude change transferred at the output.
5. Flip-Flop function The D Flip-Flop is a common building component for logic functions. A memory cell, a zero-order hold, or a delay line can all be used to describe the D Flip-Flop. It captures the value of the data input D at a definite portion of the gate cycle, resulting in the output Q. At other times instants when D = ‘1′ and G = ‘0′ , the output Q does not change; Q remains ’0′ or ’1′ based on the previous output state. Two logic functions NAND and NOT are used to build the D Flip-Flop. The diagrams and the truth table of D Flip-Flop using CR-SOAs-MZIs are shown in Fig. 4.
Further regarding claim 1, Vivero discloses in figures 1, 2, 3, 5, and 9, and related figures and text, discloses a cascade of monolithically integrated SOAs and electro-absorbers (EAs) achieves a steep static transfer function with very sharp slope that enhances re-amplification and reshaping. Vivero, Selected Text (“The steepness of the step-like transfer function is important …because it determines the ability to distinguish between ‘‘0” and ‘‘1” levels, achieving an enhancement of the extinction ratio (ER) and eye opening (through noise redistribution).”),
Vivero – Figures 1, 2, 3, 5, and 9, and Selected Text
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Abstract. Optical regeneration using a monolithically integrated chip formed by a cascade of semiconductor optical amplifiers and saturable absorbers is investigated. Static transfer functions, signal reshaping, extinction ratio enhancement, noise dynamics and device dependence on operation conditions are measured. Results show that by cascading two-pairs of SOA–EAs a steep static transfer function is achieved. Dynamical measurements show large improvements in extinction ratio as well as a large improvement in the receiver-sensitivity when used as a regenerator for NRZ signals at 10 Gb/s.
1. Introduction
All-optical signal regeneration has been demonstrated employing different techniques [2–4]. There are three different levels of regeneration depending on their objective: 1R (re-amplification), 2R (re-amplification and reshaping) and 3R (re-amplification, reshaping and re-timing). 1R-regenerators are in-line signal amplifiers such as semiconductor optical amplifiers (SOA) and erbium- doped fibre amplifiers (EDFA). The problem with this kind of in-line amplifiers is that they add noise. Taking into account that the input signal already might have accumulated noise, the resultant optical-to-signal-ratio (OSNR) may be degraded even further. 2R is obtained with a nonlinear device that has a threshold or step-like transfer function. The steepness of the step-like transfer function is important [5] because it determines the ability to distinguish between ‘‘0” and ‘‘1” levels, achieving an enhancement of the extinction ratio (ER) and eye opening (through noise redistribution).
In this work, we focus on a monolithically integrated 2R-regenerator using a cascade of SOAs and electro-absorbers (EAs). A similar approach has been suggested using ion-implanted [6] or vertical micro cavity saturable absorbers [7]. By using an electrode- controlled wave guide device we can concatenate several sections to improve performance and achieve better control [8]. Compared to other proposed all-optical 2R-regenerators [9,10] our sectioned waveguide device is simple and easy to integrate in larger photonic circuits. We start by presenting the principles of the proposed device in Section 2 and the details of the specific device in Section 3. The static experimental measurements with focus on the characteristic transfer functions is discussed in Section 4 and the dynamical characterization, like signal reshaping, ER enhancement, 10 Gb/s system performance and optical-signal-to-noise- ratio (OSNR) is presented in Section 5. Finally we conclude in Section 6
6. Conclusions. We have shown experimentally that a two-pair SOA–EA regenerator device can achieve a step-like transfer function with very sharp slope and therefore it can be suitable for implementing a 2R optical regenerator. In dynamic measurements, the SOA–EA regenerator achieves, depending on the input ER, good signal reshaping and noise re-distribution. Improvements of the output OSNR was achieved for input OSNR values above 17 dB, resulting in an improvement of the BER. All these results demonstrate that the two-pair SOA–EA regenerator device can be potentially employed as an in-line regenerator, and its integrated nature allows combining it on-chip with other circuits for advanced data signal processing.
Consequently, in light of Vivero’s disclosures of cascades of monolithically integrated SOAs and electro-absorbers (EAs) characterized by steep transfer functions, it would have been obvious to one of ordinary skill in the art to modify Kotb’s logical gates to disclose a photonic circuit comprising: a first photonic gate having a first set of one or more inputs and a first set of one or more outputs; and a second photonic gate having a second set of one or more inputs and a second set of one or more outputs, a first input of the first set of one or more inputs configured to receive a first photonic input signal, a second input of the first set of one or more inputs coupled to an output of the second set of one or more outputs and configured to receive a second photonic output signal that was generated by the second photonic gate, the first photonic gate configured to generate a first photonic output signal at an output of the first set of one or more outputs based at least in part on the first photonic input signal and the second photonic output signal, a first input of the second set of one or more inputs configured to receive a second photonic input signal, a second input of the second set of one or more inputs coupled to the output of the first set of one or more outputs and configured to receive the first photonic output signal, the second photonic gate configured to generate the second photonic output signal at the output of the second set of one or more outputs based at least in part on the second photonic input signal and the first photonic output signal; Kotb, figure 4, and related figures and text; Vivero, figures 1, 2, 3, 5, and 9, and related figures and text; because the resulting configuration would facilitate designing, fabricating, and implementing SOA-based logical gates. Shahar – Figures 9a and 10d and Selected Text.
Shahar – Figures 9a and 10d and Selected Text
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[0080] Some of the logic gates according to the present invention, which are discussed first, include summing gates that are combined with threshold devices. The summing gates include two inputs and at least two outputs in a configuration that one of the outputs is used as a coincidence output. The signals produced, by the summing gate at its coincidence output, are fed into the input of a threshold device. The threshold device produces an output signal only if it is fed, at its input, by a signal that its amplitude is above a certain threshold level. Each of the inputs of the summing gate may receive input signals A or B. When either of the inputs of the summing gate receives input signal A or B (a non-coincidence state), a low level signal that is under the threshold level of the threshold device is produced, by the summing gate, at the coincidence output. In this case, the threshold device receives, at its input, a signal that is below its threshold and thus no output signal is produced.
[0081] When both of the inputs of the summing gate simultaneously receive input signals A and B (a coincidence state), a high level signal that is above the threshold level of the threshold device is produced by the summing gate, at the coincidence output. In this case, the threshold device receives, at its input, a signal that is above its threshold and thus an output signal is produced. Accordingly, it is clear that the combination of the summing gate with the threshold device operates as an AND gate and perform the logic function AND (symbolically marked A.multidot.B)
[0148] Threshold Devices
[0149] FIG. 9a schematically illustrates a graph 5000 having coordinates of output intensity Io and output relative phase change .DELTA..phi. versus input intensity Ii. Graph 5000 depicts ideal and practical transmission curves 5002 and 5004, respectively, illustrating the relationship between output and input intensities, Io and Ii, respectively, of a nonlinear medium, e.g., a Non-Linear Element (NLE) such as, for example, an optical amplifier, an Erbium Doped Fiber Optic Amplifier (EDFA), a Solid state Optical Amplifier (SOA), a Linear Optical amplifier (LOA), an optical limiter, or any other suitable nonlinear device or material. Curve 5006 schematically illustrates the relationship between the output phase change .DELTA..phi. and the input intensity Ii in optical devices such as, for example, the above-mentioned amplifiers, limiters, or nonlinear media.
[0150] As shown in FIG. 9a, curve 5004 has a linear region 5008, a nonlinear knee region 5010, and a quasi-flat saturation region 5012. For relatively low level input signals Ii, in range 5008, the corresponding output signals Io are substantially linearly proportional to the input signal Ii. For intermediate levels of input signals Ii, e.g., in range 5010, the output signals Io are no longer linearly proportional to the input signals. For relatively high-level input signals Ii, e.g., in the range 5012, the output signals Io are saturated, generally fixed, and independent of the intensity of the input signals Ii.
[0178] Reference is now made to FIGS. 10d, 11a, and 11b. FIG. 10d illustrates threshold device 5043 in accordance with further exemplary embodiments of the present invention. FIGS. 11a and 11b illustrate the amplitude and phase transmission functions of a NLE (e.g., SOA, LOA, or EDFA) of device 5043 for two, respective, excitations levels. The threshold device 5043 in accordance with the embodiment of FIG. 10d may have a structural design generally similar to the structural design of device 5041 of FIG. 10c, with the following differences. In the component structure of the device, attenuator 5092 of FIG. 10c is removed and attenuator 5094 of FIG. 10c is replaced by an amplifier 5098. Additionally, device 5043 may be designed to operate in accordance with two different modes as detailed below.
[0179] In the first mode of operation of device 5043, couplers 5045 and 5060 may be symmetric couplers (e.g., m=1, n=1). Amplifiers 5054 and 5098 may be generally identical; however, the excitation level (e.g., optical pumping or current injection level) of amplifier 5098 may be lower than the excitation level of amplifier 5054. Thus amplifier 5098 may have a lower saturation level. The transmission functions and the saturation levels of amplifiers 5098 and 5054 are depicted denoted by symbols 5100 and 5102, respectively. Lower input pulses 5400 and 5037 and high-level pulse 5039 of input signal pattern 5027 may be amplified and attenuated by amplifier 5086 and attenuator 5088, respectively, to produce a variable input gain, if necessary. Lower input pulses 5400 and 5037, which may be split by splitter 5045 into branches 5048 and 5050, may be amplified and their phase may be shifted by amplifiers 5098 and 5054. Phase shifter 5052 may control the phase of pulses within the range of lower level amplitudes such that the pulses enter port 5056 in a phase that ensures a desired destructive interference at port 5062. In this design, lower-level pulses substantially cancel each other out at output port 5062, resulting in a zero-level output signal from coupler 5060.
[0180] Higher-level input pulse 5039 may also be split by splitter 5045 into pulses 5039a and 5039b, propagating along branches 5048 and 5050, respectively. Pulse 5039b may be amplified by amplifier 5054 to produce pulse 5039d. Pulse 5039a may be amplified by amplifier 5098, which may have a saturation level lower than the saturation level of amplifier 5054 and, thus, may already be saturated at the amplitude magnitude of pulse 5039a. Accordingly, the amplitude of pulse 5039c that is produced by amplifier 5098 is smaller than the amplitude of pulse 5039d produced by amplifier 5054. The difference between the amplitudes of pulses 5039d and 5039c is enough to produce a significantly non-zero output signal at port 5062. In addition, the phase shift of pulse 5039c, which may be in the saturated region of amplifier 5098, may be greater than the phase shift of pulse 5039d, which may be in the linear region of amplifier 5054. In this scenario, the different shifts of the phases of pulses 5039c and 5039d further enhance output signal 5087, for higher level input signal, because the interference at port 5062 may not be perfectly destructive. Amplifier 5090 may be used to enhance pulse 5087 and, thereby, to produce a higher amplitude signal 5089.
14. An optical AND logic gate comprising: i) a combining device having first and second inputs and a first output, said one of said first and second inputs includes an optical delay line and said first output includes a directing device for directing optical signal returning to said first output into a second output; ii) a splitting device having first second and third terminals; iii) a nonlinear element; and iv) an attenuator; v) said second and third terminals form an optical loop including said attenuator and said nonlinear element displaced from the center of said optical loop; vi) said first and second inputs arranged to receive first and second optical signals for producing a third optical signal at said first output of said combining device; vii) the first terminal of said splitting device arranged to receive said third optical signal from said first output of said combining device for producing at said second output a signal corresponding to the AND product of said first and second optical signals.
15. The optical logic gate of claim 14 wherein said nonlinear element is a semiconductor optical amplifier (SOA).
18. The optical logic gate of claim 14 wherein said attenuator is a semiconductor optical amplifier (SOA).
Regarding dependent claims 3-8, it would have been obvious to one of ordinary skill in the art to modify Kotb in view of Vivero and further in view of Shahar, as applied in the rejection of claim 1, to disclose:
3. The photonic circuit of claim 1, wherein the first photonic gate comprises a first photonic combiner, a phase shifter and a second photonic combiner that is coupled to an output of the first photonic combiner and an output of the phase shifter, an output of the second photonic combiner representing the output of the first set of one or more outputs. Kotb, figure 4, and related figures and text; Vivero, figures 1, 2, 3, 5, and 9, and related figures and text; Shahar – Figures 9a and 10d and Selected Text.
4. The photonic circuit of claim 3, wherein a first input of the first photonic combiner is configured to receive the first photonic input signal, and a second input of the first photonic combiner is coupled to the output of the second set of one or more outputs and configured to receive the second photonic output signal. Kotb, figure 4, and related figures and text; Vivero, figures 1, 2, 3, 5, and 9, and related figures and text; Shahar – Figures 9a and 10d and Selected Text.
5. The photonic circuit of claim 1, wherein the second photonic gate comprises a first photonic combiner, a phase shifter and a second photonic combiner that is coupled to an output of the first photonic combiner and an output of the phase shifter, an output of the second photonic combiner representing the output of the second set of one or more outputs. Kotb, figure 4, and related figures and text; Vivero, figures 1, 2, 3, 5, and 9, and related figures and text; Shahar – Figures 9a and 10d and Selected Text.
6. The photonic circuit of claim 5, wherein a first input of the first photonic combiner is configured to receive the second photonic input signal, and a second input of the first photonic combiner is coupled to the first output and configured to receive the first photonic output signal. Kotb, figure 4, and related figures and text; Vivero, figures 1, 2, 3, 5, and 9, and related figures and text; Shahar – Figures 9a and 10d and Selected Text.
7. The photonic circuit of claim 1, wherein: the first input of the first set of one or more inputs is configured to receive the first photonic input signal that comprises a first set of one or more multiplexed light signals of a set of one or more wavelengths; the first input of the second set of one or more inputs is configured to receive the second photonic input signal that comprises a second set of one or more multiplexed light signals of the set of one or more wavelengths; the output of the first set of one or more outputs is configured to output the first photonic output signal that comprises a third set of one or more multiplexed light signals of the set of one or more wavelengths; and the output of the second set of one or more outputs is configured to output the second photonic output signal that comprises a fourth set of one or more multiplexed light signals of the set of one or more wavelengths. Kotb, figure 4, and related figures and text; Vivero, figures 1, 2, 3, 5, and 9, and related figures and text; Shahar – Figures 9a and 10d and Selected Text.
8. The photonic circuit of claim 1, wherein the photonic circuit is part of a photonic register of a photonic processor, and the photonic circuit is configured to operate as a photonic set-reset flip flop. Kotb, figure 4, and related figures and text; Vivero, figures 1, 2, 3, 5, and 9, and related figures and text; Shahar – Figures 9a and 10d and Selected Text.
because the resulting configurations would facilitate designing, fabricating, and implementing SOA-based logical gates. Shahar – Figures 9a and 10d and Selected Text.
Claim 2
Claim 2, as dependent upon claim 1, is rejected under 35 U.S.C. 103 as being unpatentable over Kotb et al, All-optical latches using carrier reservoir semiconductor optical amplifiers, Optics & Laser Technology, Volume 157, 2023, 108737, ISSN 0030-3992; “Kotb”) in view of Vivero et al. (2R-Regeneration in a monolithically integrated four-section SOA-EA chip, Optics Communications, vol.282, no.1, pp.117, 2009; “Vivero”) and further in view of Shahar et al. (2004/0184750; “Shahar”), as applied in the rejection of claims 1 and 3-8, and further in view of Kita et al. (Ultrashort low-loss Ψ gates for linear optical logic on Si photonics platform. Commun Phys 3, 33 (2020); “Kita”).
Regarding claim 2, Kita discloses in figure 1, and related figures and text, 3-to-1 “Ψ” logic gates (3 inputs, 1 output; one of the inputs is ‘an auxiliary bias port.’ Kit, figure 1 and selected text (“A single Ψ gate can perform representative Boolean operations by changing the bias power and relative phases.”).
Kita, Figure 1 and Selected Text
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Nonlinear optical gates are usually considered as fundamental building blocks for universal optical computation. However, the performance is severely limited by small optical nonlinearity, thereby bounding their operation speed, consumption energy, and device size. In this paper, we propose and experimentally demonstrate linear optical logic operations with ~3 μm-long Si wire “Ψ” gates consist of 3 × 1 optical combiners including auxiliary bias port, which maximizes the binary contrast of the output in telecom wavelength. We have demonstrated 20 Gbps Boolean “AND” operation with experimentally measured small signal loss (1.6 dB experimentally). A single Ψ gate can perform representative Boolean operations by changing the bias power and relative phases. We have also demonstrated wavelength independent operation by seven wavelengths, which leads to wavelength-division multiplexed parallel computation. This ultrashort, highly-integrable, low-loss, and energy-efficient optical logic gates pave the way for ultralow latency optical pattern matching, recognition, and conversion.
Design of Ψ gates. Figure 1 summarizes the principle of our logic gates. Here a Ψ gate consisting of three inputs and one output (rigorously it is a part of a 3 × 3 interferometer with extra two hidden radiation ports) is assumed, as shown in Fig. 1a. As regards the inputs, it has two different intensity-modulated bit signals (“A” and “B”) and one continuous-wave bias light with a fixed power and a fixed relative phase to signals (“Bias”). All the inputs have fixed relative phase relationships with an identical wavelength λ.
For future work, the proposed Ψ gates should be applied for optical information processing by cascading many gates. However, we can only cascade AND or NOR gates because the cascade connection of the other gates are not linearly separable
Consequently, it would have been obvious to one of ordinary skill in the art to modify Kotb in view of Vivero and further in view of Shahar, as applied in the rejection of claims 1 and 3-8, to disclose: a first bias signal input to a third input of the first set of one or more inputs, the first bias signal having a first amplitude value that is constant over time; and a second bias signal input to a third input of the second set of one or more inputs, the second bias signal having a second amplitude value that is constant over time; Kita, figure 1, and related figures and text; Kotb, figure 4, and related figures and text; Vivero, figures 1, 2, 3, 5, and 9, and related figures and text; Shahar – Figures 9a and 10d and Selected Text; because the resulting configuration would facilitate designing, fabricating, and implementing SOA-based logical gates; Shahar – Figures 9a and 10d and Selected Text; perform representative Boolean operations by changing the bias power and relative phases.”); that facilitate ‘performing representative Boolean operations by changing the bias power and relative phases.’ Kita, figure 1, and related figures and text.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/PETER RADKOWSKI/Primary Examiner, Art Unit 2874
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