DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on 6/22/2026 is acknowledged.
Claims 17-20, have been withdrawn from consideration as being drawn to non-elected inventions.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 are rejected under 35 U.S.C. 102a1 as being anticipated by US Patent Application Publication to Santori 2018/0106967US.
In terms of Claim 1, Santori teaches A photonic counter circuit (Figure 6a), comprising: a first photonic circuit (Figure 6a: top box) having a first set of one or more inputs (Figure 6a: 101-103 corresponding to CW, Clock 1, and input) and a first set of one or more outputs (Figure 6a: from 124 to waveguide 125 which is then coupled to second circuit in a cascading fashion), a first input (Figure 6a: input to 103) of the first set of one or more inputs coupled to an output of the first set of one or more outputs (Figure 6a: signal from 103 is routed to resonator 120 and becomes part of the output signal that exits out 124 to waveguide 125 of which is then outputted into the 2nd photonic circuit or bottom box circuit elements shown below), a second input (Figure 6a: clock 1) of the first set of one or more inputs configured to receive a photonic clock signal (Figure 6a: 102 and clock signal), the first photonic circuit (Figure 6a: top box portion) configured to generate a first photonic output bit signal at the output of the first set of one or more outputs based in part on the photonic clock signal (Figure 6a: output signal travels to 125 from 124 which contains portion from all 3 input signals); and a second photonic circuit (Figure 6a: bottom box portion shown below) having a second set of one or more inputs (Figure 6a: CW2 and clock 2) and a second set of one or more outputs (Figure 6a: output 1-4), a first input (CW2) of the second set of one or more inputs coupled to an output of the second set of one or more outputs (CW2), a second input (Figure 6a: clock 2) of the second set of one or more inputs coupled to the output of the first set (Figure 6a: clock 2 signal is coupled to output signal from 125 at 645) of one or more outputs (at 125) and configured to receive the first photonic output bit signal (Figure 6a: at 125 receives output signal from 124), the second photonic circuit configured to generate a second photonic output bit signal (Figure 6a: output signal that exits 654 and routed via 667 to output 1-4) at the output of the second set of one or more outputs based in part on the first photonic output bit signal (Figure 6a: output 1-4 contains portions of the signals that travels through 125 towards 645).
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As for Claim 2, Santori teaches the optical counter circuit of claim 1, wherein: the second input (clock 1 signal at 102) of the first set of one or more inputs (101/103 AND cw1, clock 1 and logical input) is configured to receive the photonic clock signal (Figure 6a: clock 1) that comprises a first set of one or more multiplexed light signals of a set of one or more wavelengths (Figure 6a: 102 is disclosed as a waveguide, and waveguides are capable of transmitting multiplexed light; further the circuit is able process multiplex or demultiplex signals [0060]); the output (at 125) of the first set of one or more outputs is configured to output the first photonic output bit signal that comprises a second set of one or more multiplexed light signals of the set of one or more wavelengths (Figure 6a: accepts 3 signals, of which is combine into one signal path to resonator, the signals must be multiplex in order to travel through the same path at 112; Santori also teaches that the circuit 600 is able to handle multiplex or demultiplex signals [0060]. Lastly, all the waveguides that make up pathways from 112 to 122 are capable of carrying multiplexed signals); and the output (Figure 6a: output 1-4) of the second set of one or more outputs is configured to output the second photonic output bit signal that comprises a third set of one or more multiplexed light signals of the set of one or more wavelengths (Figure 6a: CW1 101 is combine with several signals at 115, 1st set of multiplexed signal; CW2 is combine with clock 2 and output of 125 at 645 to form 2nd set of multiplexed signal; CW3 is then combine with several signals from 654 to form 3rd set of multiplex signals. Further Figure 6c illustrates the system can have many gates and wherein the gates combination of “AND with OR” produce by 600 can produce signals outputs having multiplex features [0060]).
As for Claim 3, Santori teaches the optical counter circuit of claim 1, wherein the first photonic circuit (Figure 6c) comprises: a first set of one or more cascading photonic gates (Figure 6a: made of AND and OR gates sequentially cascading [0060]) having at least one first input and at least one first output (Figure 6a: 101-103 for inputs and 125 for outputs); and a second set of one or more cascading photonic gates having at least one second input and at least one second output ([0060] teaches wherein multiplex sets of AND / OR gates can be combine sequentially to produce the photonic circuits), a first input (101) of the at least one first input coupled to a second output of the at least one second output (output 1-4) and configured to receive the second photonic output bit signal (at output 1-4), a second input (Clock 1) of the at least one first input configured to receive the photonic clock signal (Figure 6a: clock 1), the first set of one or more cascading photonic gates configured to generate, at a first output (125) of the at least one first output, a first intermediate output signal ([0060] teaches multiple sets of AND/OR gate being combine to produce an output signal; the 1st set of and / or gate is output via output 1-4 this is then coupled to a second and/or gate set as disclosed by [0060]. The coupling opposite end of 685 which couples to a second set of and/or gate is considered by the examiner as the intermediate output signal) based at least in part on the second photonic output bit signal and the photonic clock signal, and generate, at a second output of the at least one first output (Base on Clock 1, and clock of which is all output out via output 1-4); a second intermediate output signal (Figure 6a: teaches and/or gates combination, [0060] teaches multiple sets of these gates can be combine sequentially, hence the output of the 2nd set of circuit 600 at output 1-4 on the second set will be considered as the second intermediate output) based at least in part on the first intermediate output signal and the photonic clock signal (Figure 6a and [0060] since all the sets of and/or gates are combine sequentially all the signals at the end of the sequence of gates will be base on all the signals prior to it), a second input ([0060] indicates multiple sets of 600 shown in Figure 6a which is and/or circuit can be sequentially combine) of the at least one second input coupled to the first output of the at least one first output and configured to receive the first intermediate output signal (the input of 2nd sets of signals to 600 are shown will also be present in 2nd circuit of and/or circuit similar to 600), a first input (101 of the 2nd circuit 600 shown in Figure 6a) of the at least one second input (Figure 6a: 600 having inputs 101-103 but in the 2nd set of and/or circuits 600) coupled to the second output of the at least one first output and configured to receive the second intermediate output signal (Since Figure 6a can be duplicated to and combine with each other all the waveguides will be coupled to each other), the second set of one or more cascading photonic gates configured to generate, at a first output of the at least one second output, a first photonic output signal based at least in part on the second intermediate output signal and the second photonic output bit signal that was output by the second set of one or more cascading photonic gates at the second output of the at least one second output, and generate, at the second output of the at least one second output, the second photonic output bit signal based at least in part on the first intermediate output signal and the first photonic output signal (Figure 6a and [0060] wherein all the inputs, outputs of and intermediate outputs will be coupled to a corresponding circuit 600 that is identical to the one shown in Figure 6a when coupled to each other in a sequentially fashion [0060]).
As for Claim 4, Santori teaches the optical counter circuit of claim 3, wherein the first set of one or more cascading photonic gates (Figure 6a: made of up and/or gates shown above as top box and bottom box; [0060] teaches multiples sets of these can be combine squenetially) comprises: a first photonic gate (Figure 6a: top box) having one or more first inputs (101-103) and one or more first outputs (125); and a second photonic gate (Figure 6a: 600 bottom box) having one or more second inputs (Clock 2 and Cw2) and one or more second outputs (output 1-4), a first input of the one or more first inputs coupled to the second output of the second set of one or more cascading photonic gates (101 coupled to output1 via the optical branches of 667 and 112) and configured to receive the second photonic output bit signal (output 1-4 produces a second output bit signal base on all the inputs signals), a second input (clock 1) of the one or more first inputs (101-103) configured to receive the photonic clock signa (Clock 1)l, the first photonic gate configured to generate the first intermediate output signal at an output of the one or more first outputs based at least in part on the first photonic output bit signal and the photonic clock signal (Figure 6a: output 1 has a waveguide 685, the opposite end of 685 is then coupled to another circuit similar to 600 as disclosed by [0060]. The 2nd end of 685 produces the 1st intermediate signal),a first input (Figure 6a: similar 101 but on the 2nd sequentially circuits 600) of the one or more second inputs (101-103 located in the 2nd sequentially circuits 600) coupled to the output of the one or more first outputs (Figure 6a: 125 on the 2nd sequentially circuits 600) and configured to receive the first intermediate output signal (from output 1-4 of the 1st circuit 600), a second input of the one or more second inputs coupled to the second input of the one or more first inputs and configured to receive the photonic clock signal, the second photonic gate configured to generate the second intermediate output signal at an output of the one or more second outputs based at least in part on the first intermediate output signal and the photonic clock signal (Figure 6a: output 1-4 of 2nd circuit contains all the elements of all signals that is coupled to it in a sequentially fashion).
As for Claim 5, Santori teaches the optical counter circuit of claim 4, further comprising: a first bias signal input (CW1 is a bias signal [0026]) to a third input of the one or more first inputs (101-103), the first bias signal having a first amplitude value that is constant over time [0026-0027]); and a second bias signal input (CW2) to a third input of the one or more second inputs (Clock 2), the second bias signal having a second amplitude value that is constant over time ([0026-0027]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication to Santori 2018/0106967US.
In regards to claims 15 and 16, Santori teaches the device of claim 1 having a frequency and clock signal (Figure 6a: clock1 and clock 2 and various frequency of CW1, CW2, and CW3 signal).
Santori does not teach wherein: a frequency of the photonic clock signal is two times higher than a frequency of the first photonic output bit signal; and the frequency of the first photonic output bit signal is two times higher than a frequency of the second photonic output bit signal and wherein the first photonic output bit signal and the second photonic output bit signal together represent a bit count of a number of pulses of the photonic clock signal.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the output signal to represent the bit count of a number pulse and the modify the frequency to be two times in order to track the amount of calculations that has be been performed by the flip-flop circuit 600. The frequency adjusting will change the logic values of each pass for logic calculations. It has been held that discovering an optimum value of a result effective variable involves only routine skill in the art, In re Antonie, 195 USPQ 6 (C.C.P.A. 1977).
Claims 6-7 and 8-14 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication to Santori 2018/0106967US in view of the US Patent Application Publication to Mower 2015/0354938US.
In regards to Claim 6, Santori teaches the optical counter circuit of claim 4, wherein: the first photonic gate (Figure 6a: top box) comprises a first photonic combiner (at end of 110), a phase shifter (weaker coupler 115 can phase shift [0027] and [0051]) and a second photonic combiner (Figure 6a: see branch combining at end of 630 which is coupled to 1st combiner via the different waveguides such 117/120) that is coupled to an output of the first photonic combiner and an output of the phase shifter (at resonator 120/124), an output of the second photonic combiner coupled to the output of the one or more first outputs (at 645 is coupled to 125) a second input of the first photonic combiner is configured to receive the photonic clock signal (Clock 1).
Santori does not teach a feedback loop wherein a first input of the first photonic combiner is configured to receive the second photonic output bit signal.
Mower does teach a feedback loop wherein a first input (from 1410) of the first photonic combiner is configured to receive the second photonic output bit signal (from 1412). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit to contain a feedback loop which couples the result from the output in back into the input end. Mower indicates this is useful for multi-pass application for iterative type processing of logic calculations (Mower’s [0115-0117]).
In regards to Claim 7, Santori teaches optical counter circuit of claim 4, wherein: the second photonic gate (Figure 6a above: bottom box) comprises a first photonic combiner (at end of 630), a phase shifter (weaker coupler 645 can phase shift [0051]) and a second photonic combiner (665) that is coupled to an output of the first photonic combiner (Figure 6a: 630 is coupled to 665 via 650) and an output of the phase shifter (645 is coupled to 665 via 650), an output of the second photonic combiner coupled to the second output of the first set of one or more cascading photonic gates (665 coupled to output 1-4); a first input (waveguide 630 couple to 645) of the first photonic combiner is coupled to the first output (125) of the at least one first output; a second input of the first photonic combiner is configured to receive the photonic clock signal (clock 2).
Santori does not teach the first output at 125 contains a loop to receive the first intermediate output signal (from 685).
Mower does teach a feedback loop wherein a first input (from 1410) of the first photonic combiner is configured to receive output bit signal (from 1412). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit to contain a feedback loop which couples the result from the output 1-4 (which is the intermediated output) back into the output portion 125 which functions as an input for the 2nd gate (bottom box of Figure 6a above). Mower indicates loop configuration is useful for multi-pass application for iterative type processing of logic calculations (Mower’s [0115-0117]).
In regards to Claims 8 and 11, Santori teaches optical counter circuit of claim 4, wherein the second set of one or more cascading photonic gates (Figure 6a teaches and/or cascading gate combination; [0060] teaches multiple sets of these gates can be arranged sequentially) comprises: a first photonic gate (Figure 6a: top box) having one or more first inputs (101-103) and one or more first outputs (125),; and a second photonic gate (bottom box) having one or more second inputs (Clock2 and cw2) and one or more second outputs (output 1-4), a first input (101) of the one or more first inputs coupled to the second output of the first set of one or more cascading photonic gates (101 is coupled to output 1-4); wherein: the second photonic gate comprises a first photonic combiner (at end of 630), a phase shifter (weaker coupler 645) and a second photonic combiner (665) that is coupled to an output of the first photonic combiner (665 coupled to 630) and an output of the phase shifter (645), an output of the second photonic combiner (at 667) coupled to the second output of the at least one second output (output 1-4).
Santori and Mower does not teach an output of the one or more first outputs (from 125) coupled to the first output of the second set of one or more cascading photonic gates an output of the one or more second outputs coupled to the second output of the second set of one or more cascading photonic gates; and configured to receive the second intermediate output signal, a second input of the one or more first inputs coupled to the second output of the at least one second output and configured to receive the second photonic output bit signal, the first photonic gate configured to generate the first photonic output signal at the output of the one or more first outputs based at least in part on the second intermediate output signal and the second photonic output bit signal, a first input of the one or more second inputs coupled to the first output of the first set of one or more cascading photonic gates and configured to receive the first intermediate output signal, a second input of the one or more second inputs coupled to the output of the one or more first outputs and configured to receive the first photonic output signal, the second photonic gate configured to generate the second photonic output bit signal at the output of the one or more second outputs based at least in part on the first intermediate output signal and the first photonic output signal (Claim 8); a first input of the first photonic combiner is coupled to the second output of the first set of one or more cascading photonic gates and configured to receive the first intermediate output signal; and a second input of the first photonic combiner is coupled to the first output of the second set of one or more cascading photonic gates and configured to receive the first photonic output signal (Claim 11).
The examiner considers the various modifications wherein different inputs / outputs of the various junctions in the cascading gates described above are obvious in view of KSR obvious to try rationale. Logic gates digital processing is known and by combining different combination of 1 and 0 are known to produce predictable logic tables. Since the structure of Figure 6a is a logic gate base off different optical signals having modulating functions to change values from 1 to 0 and vice versa. The act of coupling different inputs to different outputs merely changes the logic value being fed into the gate for logic processing. Further by applying loops as indicated by Mower such as coupling and output end back into an input are known to be used for “iterative processing” and producing logic functions. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 421, 82 USPQ2d 1385, 1397 (2007).
As for Claim 9, Santori / Mower teaches the optical counter circuit of claim 8, wherein Santori teaches further comprising: a first bias signal input (CW1 is a bias signal [0026]) to a third input of the one or more first inputs (101-103), the first bias signal having a first amplitude value that is constant over time [0026-0027]); and a second bias signal input (CW2) to a third input of the one or more second inputs (Clock 2), the second bias signal having a second amplitude value that is constant over time ([0026-0027]).
In regards to Claim 10, Santori / Mower teaches the optical counter circuit of claim 8, wherein Santori teaches the first photonic gate (Figure 6a: top box) comprises a first photonic combiner (at end of 110), a phase shifter (weaker coupler 115 can phase shift [0027] and [0051]) and a second photonic combiner (Figure 6a: see branch combining at end of 630 which is coupled to 1st combiner via the different waveguides such 117/120) that is coupled to an output of the first photonic combiner and an output of the phase shifter (at resonator 120/124), an output of the second photonic combiner coupled to the output of the one or more first outputs (at 645 is coupled to 125) a second input of the first photonic combiner is configured to receive the photonic clock signal (Clock 1).
Santori does not teach a feedback loop wherein a first input of the first photonic combiner is configured to receive the second intermediate output signal; and a feedback loop wherein a second input of the first photonic combiner is coupled to the second output of the at least one second output and configured to receive the second photonic output bit signal.
Mower does teach a feedback loop wherein a first input (from 1410) of the first photonic combiner is configured to receive the second photonic output bit signal (from 1412). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit to contain a feedback loop which couples the result from the output in back into the input end for the 1st input and second intermediate output signal and for the second output and second output bit signal. Mower indicates this is useful for multi-pass application for iterative type processing of logic calculations (Mower’s [0115-0117]).
In regards to Claims 12-14, Santori teaches the optical counter of claim 1.
Santori does not teach wherein the second photonic circuit comprises: a first set of one or more cascading photonic gates having at least one first input and at least one first output; and a second set of one or more cascading photonic gates having at least one second input and at least one second output,a first input of the at least one first input coupled to a second output of the at least one second output and configured to receive the second photonic output bit signal, a second input of the at least one first input coupled to the output of the at least one first output of the first photonic circuit and configured to receive the first photonic output bit signal of the photonic counter circuit, the first set of one or more cascading photonic gates configured to generate, at a first output of the at least one first output, a first intermediate output signal based at least in part on the first photonic output bit signal of the photonic counter circuit and the second photonic output bit signal of the second set of one or more cascading photonic gates, and generate, at a second output of the at least one first output, a second intermediate output signal based at least in part on the first intermediate output signal and the first photonic output bit signal of the photonic counter circuit, a first input of the at least one second input coupled to the second output of the at least one first output and configured to receive the second intermediate output signal, a second input of the at least one second input coupled to the first output of the at least one first output and configured to receive the first intermediate output signal, the second set of one or more cascading photonic gates configured to: generate, at a first output of the at least one second output, a first photonic output signal based at least in part on the second intermediate output signal and the second photonic output bit signal that was output by the second set of one or more cascading photonic gates at the second output of the at least one second output, and generate, at the second output of the at least one second output, the second photonic output bit signal based at least in part on the first intermediate output signal and the first photonic output signal (Claim 12); wherein the first set of one or more cascading photonic gates comprises: a first photonic gate having one or more first inputs and one or more first outputs; and a second photonic gate having one or more second inputs and one or more second outputs, a first input of the one or more first inputs coupled to the second output of the second set of one or more cascading photonic gates and configured to receive the second photonic output bit signal, a second input of the one or more first inputs configured to receive the first photonic output bit signal of the photonic counter circuit, the first photonic gate configured to generate the first intermediate output signal at the output of the one or more first outputs based at least in part on the second photonic output bit signal of the second set of one or more cascading photonic gates and the first photonic output bit signal of the photonic counter circuit, a first input of the one or more second inputs coupled to the output of the one or more first outputs and configured to receive the first intermediate output signal, a second input of the one or more second inputs coupled to the second input of the one or more first inputs and configured to receive the first photonic output bit signal of the photonic counter circuit, the second photonic gate configured to generate the second intermediate output signal at an output of the one or more second outputs based at least in part on the first intermediate output signal and the first photonic output bit signal of the photonic counter circuit (Claim 13); wherein the second set of one or more cascading photonic gates comprises: a first photonic gate having one or more first inputs and one or more first outputs, an output of the one or more first outputs coupled to the first output of the second set of one or more cascading photonic gates; and a second photonic gate having one or more second inputs and one or more second outputs, an output of the one or more second outputs coupled to the second output of the second set of one or more cascading photonic gates, a first input of the one or more first inputs coupled to the second output of the first set of one or more cascading photonic gates and configured to receive the second intermediate output signal, a second input of the one or more first inputs coupled to the second output of the at least one second output and configured to receive the second photonic output bit signal, the first photonic gate configured to generate the first photonic output signal at the output of the one or more first outputs based at least in part on the second intermediate output signal and the second photonic output bit signal,a first input of the one or more second inputs coupled to the first output of the first set of one or more cascading photonic gates and configured to receive the first intermediate output signal, a second input of the one or more second inputs coupled to the output of the one or more first outputs and configured to receive the first photonic output signal, the second photonic gate configured to generate the second photonic output bit signal at the output of the one or more second outputs based at least in part on the first intermediate output signal and the first photonic output signal (Claim 14).
The examiner considers the various modifications wherein different inputs / outputs of the various junctions in the cascading gates described above in claim 12, 13 and 14 are obvious in view of KSR obvious to try rationale. Logic gates digital processing is known wherein by combining different combinations of 1 and 0 are known to produce predictable logic tables. Since the structure of Figure 6a is a logic gate base off different optical signals having modulating functions to change values from 1 to 0 and vice versa. The act of coupling different inputs to different outputs at various portions of the waveguide to each other merely changes the logic value being fed into the gate for logic processing. Further by applying loops as indicated by Mower such as coupling and output end back into an input are known to be used for “iterative processing” and producing logic functions. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 421, 82 USPQ2d 1385, 1397 (2007).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent Application Publication to Yohannes 2020/0119251 teaches quantum processing using optical gates.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HOANG Q TRAN whose telephone number is (571)272-5049. The examiner can normally be reached 9:30 am - 5:30pm Monday - Friday.
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/HOANG Q TRAN/ Examiner, Art Unit 2874
/UYEN CHAU N LE/ Supervisory Patent Examiner, Art Unit 2874
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