Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1–3, 8, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Testa et al. (US 2015/0215066 A1) in view of McKenzie et al. (US 6,693,904 B1), and further in view of Chang et al. (US 6,724,759 B1).
Regarding Claim 1:
For purposes of examination, “interface” encompasses a port, terminal, or physical connection through which data is communicated between circuit elements or semiconductor dies; “divider” encompasses a splitter or demultiplexer; and “combiner” encompasses a multiplexer or signal-combining structure.
Testa teaches a data switching apparatus, comprising: a plurality of dies, by disclosing (paragraph [0093] “different parts of the switch fabric 68 may be constructed from several connected semiconductor dies”; see also Fig. 5).
Testa further teaches a divider; a switching unit, wherein a first output end of the divider is coupled to a first input end of the switching unit; a combiner, wherein a first output end of the switching unit is coupled to a first input end of the combiner; a first interface, wherein an input end of the divider is coupled to the first interface; [and] a fourth interface, wherein an output end of the combiner is coupled to the fourth interface (paragraph [0079] “Each bandsplit filter 62 is arranged to receive a wavelength multiplexed input optical signal from the respective input port 12 and is configured to split the received input optical signal into two sub-band signals”), (paragraph [0085] “The individual optical signals, at wavelengths λ1 to λ48, are coupled into respective rows of the switch matrix 68”), and (paragraph [0090] “all of the optical signals travelling to a respective output port 18 are multiplexed by a respective AWG 66, then the interleavers 64 combine the odd and even wavelength into upper and lower sub-band signals and finally the bandsplit filters 76 combine the lower and upper bands”). Thus, input port 12, bandsplit filter 62, switch matrix 68, the output AWGs 66/interleavers 64/bandsplit filters 76, and output port 18 correspond to the claimed first interface, divider, switching unit, combiner, and fourth interface, respectively.
Testa does not expressly teach wherein each of the plurality of dies comprises the recited divider, switching unit, combiner, and first through fourth interfaces.
McKenzie teaches a divider; a switching unit, wherein a first output end of the divider is coupled to a first input end of the switching unit; [and] a combiner, wherein a first output end of the switching unit is coupled to a first input end of the combiner (col. 1, l. 65–col. 2, l. 2: “Switch fabric 100 has a column of n input demultiplexers 102, a column of m switches 104, and a column of n output multiplexers 106”), (col. 2, ll. 5–10: “Each demultiplexer 102 can receive and parallelize a different incoming signal on a bit-by-bit basis, whereby every mth bit of the incoming signal is transmitted to the same parallel switch 104”), (col. 2, ll. 19–24: “Each switch 104 switches the corresponding subset of each incoming signal to a different output multiplexer 106”), and (col. 2, ll. 26–40: “Each output multiplexer 106 serializes the eight parallel streams of bits received from the eight switches 104 to form a single serial stream corresponding to the output signal”).
Testa and McKenzie do not expressly teach a second interface, wherein a second output end of the divider and a second input end of the switching unit are both coupled to the second interface; a third interface, wherein a second output end of the switching unit and a second input end of the combiner are both coupled to the third interface; [or] wherein the third interface of each of the plurality of dies is coupled to the third interface of another of the plurality of dies, and the second interface of each of the plurality of dies is coupled to the second interface of still another of the plurality of dies.
Chang teaches ports of a switching component coupled to different neighboring switching components, by disclosing (col. 17, l. 60–col. 18, l. 2: “each switch fabric component has two ports coupled to the two adjacent switch fabric components”). Chang further discloses (col. 18, ll. 2–10: “ports 5/1 and 6/1 of SF1 2202a are coupled to ports 2/2 and 1/2 of SF2 2202b, respectively, and ports 7/1 and 8/1 of SF1 2202a are coupled to ports 4/3 and 3/3 of SF3 2202c, respectively”; see also Fig. 22).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Testa in view of McKenzie and Chang by implementing McKenzie’s parallel demultiplexer-switch-multiplexer arrangement in Testa’s connected semiconductor dies and using Chang’s separate-port arrangement to connect the additional paths between different dies, thereby providing the claimed second and third interfaces and increasing switching capacity through parallel processing (McKenzie, col. 1, ll. 48–55).
Regarding Claim 2: Testa, McKenzie, and Chang disclose the apparatus of Claim 1
Testa teaches wherein the plurality of dies are interconnected to form a switch fabric, (paragraph [0093] “different parts of the switch fabric 68 may be constructed from several connected semiconductor dies”).
Testa does not expressly teach wherein the first interfaces and the fourth interfaces of the plurality of dies are configured to serve as input interfaces and output interfaces of the switch fabric, respectively.
McKenzie teaches wherein the first interfaces and the fourth interfaces of the plurality of dies are configured to serve as input interfaces and output interfaces of the switch fabric, respectively, by disclosing input and output structures positioned at the respective input and output sides of a switch fabric (col. 1, l. 65–col. 2, l. 2: “Switch fabric 100 has a column of n input demultiplexers 102, a column of m switches 104, and a column of n output multiplexers 106”) and that the input demultiplexers receive incoming signals (col. 2, ll. 5–7: “Each demultiplexer 102 can receive and parallelize a different incoming signal on a bit-by-bit basis”) and that the output multiplexers generate outgoing signals (col. 2, ll. 37–40: “Each output multiplexer 106 serializes the eight parallel streams of bits received from the eight switches 104 to form a single serial stream corresponding to the output signal”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the first and fourth interfaces of Testa’s interconnected semiconductor dies as the respective input and output interfaces of the switch fabric, consistent with McKenzie’s input demultiplexers and output multiplexers, thereby providing defined signal-entry and signal-exit paths (McKenzie, col. 1, l. 65–col. 2, l. 2).
Regarding Claim 3: Testa, McKenzie, and Chang disclose the apparatus of Claim 1
Testa teaches wherein the plurality of dies comprise a first die, a second die, a third die, and a fourth die (paragraph [0093] “different parts of the switch fabric 68 may be constructed from several connected semiconductor dies”).
Testa and McKenzie do not expressly teach wherein a third interface of the first die is coupled to a third interface of the second die, a third interface of the third die is coupled to a third interface of the fourth die, a second interface of the first die is coupled to a second interface of the third die, and a second interface of the second die is coupled to a second interface of the fourth die.
Chang teaches wherein a third interface of the first die is coupled to a third interface of the second die, a third interface of the third die is coupled to a third interface of the fourth die, a second interface of the first die is coupled to a second interface of the third die, and a second interface of the second die is coupled to a second interface of the fourth die, by disclosing switching components coupled to different switching components through separate conduits and that each outer-stage switch-fabric component is directly coupled through independent conduits to each middle-stage switch-fabric component and that each middle-stage component is directly coupled through independent conduits to each outer-stage component (col. 6, ll. 29–46) and further discloses a non-blocking topology (col. 6, l. 65–col. 7, l. 2: “there is a path from every port controller to all of the other port controllers”; see also Fig. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply Chang’s four-component adjacent-port arrangement to four semiconductor dies of the Testa-McKenzie switch fabric, thereby providing the claimed second- and third-interface couplings and separate communication paths among the four dies (Chang, col. 17, ll. 35–46).
Regarding Claim 8: Testa, McKenzie, and Chang disclose the apparatus of Claim 1
For purposes of examination, “virtual output interface” encompasses a logical output interface represented by one or more physical interfaces through which data is directed to an output.
Testa, McKenzie, and Chang do not expressly teach wherein there is one virtual output interface corresponding to a third interface of either of two dies that are in the plurality of dies and whose third interfaces are coupled, and a virtual output interface of either of the two dies corresponds to a fourth interface of the other die.
Testa teaches the recited “fourth interface,” as established for Claim 1, by disclosing (paragraph [0090]: “After being transmitted across the switch matrix 68, at the end of the respective row all of the optical signals travelling to a respective output port 18 are multiplexed by a respective AWG 66, then the interleavers 64 combine the odd and even wavelength into upper and lower sub-band signals and finally the bandsplit filters 76 combine the lower and upper bands”).
McKenzie teaches the recited output end of the combiner, as established for Claim 1, by disclosing (col. 2, ll. 26–40: “Each output multiplexer 106 can receive and serialize bits for a different outgoing signal”; further, “Each output multiplexer 106 serializes the eight parallel streams of bits received from the eight switches 104 to form a single serial stream corresponding to the output signal”).
Chang teaches interfaces of two switching components that are coupled, by disclosing (col. 17, l. 60–col. 18, l. 2: “each switch fabric component has two ports coupled to the two adjacent switch fabric components”). Chang further discloses (col. 18, ll. 2–10: “ports 5/1 and 6/1 of SF1 2202a are coupled to ports 2/2 and 1/2 of SF2 2202b, respectively, and ports 7/1 and 8/1 of SF1 2202a are coupled to ports 4/3 and 3/3 of SF3 2202c, respectively”; see also Fig. 22).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to represent Chang’s coupled inter-component interfaces as a virtual output interface associated with the output interface taught by Testa and McKenzie, thereby simplifying output identification and routing (Testa, paragraph [0090]; McKenzie, col. 2, ll. 26–40; Chang, col. 17, l. 60–col. 18, l. 2).
Regarding Claim 9: Testa, McKenzie, and Chang disclose the apparatus of Claim 1
Testa teaches wherein the plurality of dies comprise a plurality of die sets only to the extent that Testa discloses a plurality of connected semiconductor dies (paragraph [0093] “different parts of the switch fabric 68 may be constructed from several connected semiconductor dies”).
Testa and McKenzie do not expressly teach wherein, for two respective dies in a same die set, the third interfaces of the two dies are coupled, and wherein for two respective dies in different die sets, the second interfaces of the two dies are coupled.
Chang teaches groups of switching components interconnected through independent conduits (col. 6, ll. 5–29: “a three-stage or layer Clos network topology having a middle stage of switch fabric components … connecting a pair of outer stages of switch fabric components”) and (col. 6, ll. 29–46: “each outer stage switch fabric component … is directly coupled via independent conduits to each of the middle stage switch fabric components”; further, “each of the middle stage switch fabric components … is directly coupled via independent conduits to each of the outer stage switch fabric components”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to organize Testa’s connected semiconductor dies into die sets corresponding to Chang’s switching-component stages and to use Chang’s independent conduits for the intra-set and inter-set interface connections, thereby providing separate communication paths between the dies (Chang, col. 6, ll. 5–46).
Claims 4, 14, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Testa, McKenzie, and Chang, and further in view of Kalkunte et al. (US 6,950,430 B2).
Regarding Claim 4: Testa, McKenzie, and Chang disclose the apparatus of Claim 3
Testa and McKenzie teach the divider is configured to: receive first data through an input end of the divider”; the switching unit is configured to: receive second data through the first input end and the second input end of the switching unit; and the combiner is configured to: receive third data through the first input end and the second input end of the combiner, and output the third data through the output end of the combiner (paragraph [0079] “Each bandsplit filter 62 is arranged to receive a wavelength multiplexed input optical signal from the respective input port 12 and is configured to split the received input optical signal into two sub-band signals”), and that the divided signals are supplied to switch matrix 68 (paragraph [0085] “The individual optical signals, at wavelengths λ1 to λ48, are coupled into respective rows of the switch matrix 68”), and that the switched signals are multiplexed and combined for output (paragraph [0090] “all of the optical signals travelling to a respective output port 18 are multiplexed by a respective AWG 66, then the interleavers 64 combine the odd and even wavelength into upper and lower sub-band signals and finally the bandsplit filters 76 combine the lower and upper bands”).
McKenzie further teaches multiple divider-to-switch and switch-to-combiner paths (col. 2, ll. 5–10: “Each demultiplexer 102 can receive and parallelize a different incoming signal on a bit-by-bit basis, whereby every mth bit of the incoming signal is transmitted to the same parallel switch 104”; col. 2, ll. 19–24: “Each switch 104 switches the corresponding subset of each incoming signal to a different output multiplexer 106”; col. 2, ll. 26–40: “Each output multiplexer 106 serializes the eight parallel streams of bits received from the eight switches 104 to form a single serial stream corresponding to the output signal”).
Testa, McKenzie, and Chang do not expressly teach output the first data through the first output end of the divider when a destination die of the first data is the first die or the second die, or output the first data through the second output end of the divider when a destination die of the first data is the third die or the fourth die; or output the second data through a first output end of the switching unit when a destination die of the second data is the first die, or output the second data through the second output end of the switching unit when a destination die of the second data is the second die.
Kalkunte teaches selecting an output path based on a destination (col. 4, l. 50–col. 5, l. 25: “The fabric will forward the packet to the egress port in the fabric, which is the path to the destination module”; further, “the fabric may have to choose an egress port based on the fabric ingress port and the destination module id” and “the selection of the fabric egress port is based on destination module”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply Kalkunte’s destination-based egress-port selection to the divider and switching unit of the Testa-McKenzie-Chang four-die arrangement, thereby selecting each output path according to the destination die and improving routing efficiency (Kalkunte, col. 4, l. 50–col. 5, l. 25).
Regarding Claim 14:
For purposes of examination, “interface” encompasses a port, terminal, or physical connection through which data is communicated; “divider” encompasses a splitter or demultiplexer; and “combiner” encompasses a multiplexer or signal-combining structure.
Testa teaches a data switching method, applied to a data switching apparatus comprising a plurality of dies, by disclosing a method of routing optical signals through a switch fabric and that the switch fabric may be constructed from connected semiconductor dies (paragraph [0093] “different parts of the switch fabric 68 may be constructed from several connected semiconductor dies”).
Testa further teaches receiving, by the divider, first data through the input end of the divider”; receiving, by the switching unit, second data; and receiving, by the combiner, third data through the first input end . . . and outputting the third data through the output end of the combiner (paragraph [0079] “Each bandsplit filter 62 is arranged to receive a wavelength multiplexed input optical signal from the respective input port 12 and is configured to split the received input optical signal into two sub-band signals”), supplying optical signals to switch matrix 68 (paragraph [0085] “The individual optical signals, at wavelengths λ1 to λ48, are coupled into respective rows of the switch matrix 68”), and multiplexing and combining the switched signals for output (paragraph [0090] “all of the optical signals travelling to a respective output port 18 are multiplexed by a respective AWG 66, then the interleavers 64 combine the odd and even wavelength into upper and lower sub-band signals and finally the bandsplit filters 76 combine the lower and upper bands”).
Testa does not expressly teach wherein each of the plurality of dies comprises a divider, a switching unit, a combiner, a first interface, a second interface, a third interface, and a fourth interface; an input end of the divider is coupled to the first interface, a first output end of the divider is coupled to a first input end of the switching unit, a second output end of the divider and a second input end of the switching unit are both coupled to the second interface, a first output end of the switching unit is coupled to a first input end of the combiner, a second output end of the switching unit and a second input end of the combiner are both coupled to the third interface, and an output end of the combiner is coupled to the fourth interface.
McKenzie teaches a divider-switching-unit-combiner arrangement having multiple signal paths (col. 1, l. 65–col. 2, l. 2: “Switch fabric 100 has a column of n input demultiplexers 102, a column of m switches 104, and a column of n output multiplexers 106”). McKenzie further discloses (col. 2, ll. 5–10: “Each demultiplexer 102 can receive and parallelize a different incoming signal on a bit-by-bit basis, whereby every mth bit of the incoming signal is transmitted to the same parallel switch 104”), (col. 2, ll. 19–24: “Each switch 104 switches the corresponding subset of each incoming signal to a different output multiplexer 106”), and (col. 2, ll. 26–40: “Each output multiplexer 106 serializes the eight parallel streams of bits received from the eight switches 104 to form a single serial stream corresponding to the output signal”).
Testa and McKenzie do not expressly teach the plurality of dies comprise a first die, a second die, a third die, and a fourth die, a third interface of the first die is coupled to a third interface of the second die, a third interface of the third die is coupled to a third interface of the fourth die, a second interface of the first die is coupled to a second interface of the fourth die, and a second interface of the second die is coupled to a second interface of the third die.
Chang teaches four switching components having separate ports coupled to adjacent switching components (col. 17, ll. 35–46: “the switch fabric 2200 comprises four 8 by 8 switch fabric components denoted as: SF1 2202a, SF2 2202b, SF3 2202c, and SF4 2202d”). Chang further discloses (col. 17, l. 60–col. 18, l. 10: “each switch fabric component has two ports coupled to the two adjacent switch fabric components”; further, “ports 5/1 and 6/1 of SF1 2202a are coupled to ports 2/2 and 1/2 of SF2 2202b, respectively, and ports 7/1 and 8/1 of SF1 2202a are coupled to ports 4/3 and 3/3 of SF3 2202c, respectively”; see also Fig. 22).
Testa, McKenzie, and Chang do not expressly teach outputting the first data through the first output end of the divider when a destination die of the first data is the first die or the second die, or outputting the first data through the second output end of the divider when a destination die of the first data is the third die or the fourth die; or outputting the second data through the first output end of the switching unit when a destination die of the second data is the first die, or outputting the second data through the second output end of the switching unit when a destination die of the second data is the second die.
Kalkunte teaches selecting an output path according to destination information (col. 4, l. 50–col. 5, l. 25: “The fabric will forward the packet to the egress port in the fabric, which is the path to the destination module”; further, “the fabric may have to choose an egress port based on the fabric ingress port and the destination module id” and “the selection of the fabric egress port is based on destination module”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement McKenzie’s parallel divider-switch-combiner arrangement in Testa’s connected dies, interconnect four such dies using Chang’s adjacent-port arrangement, and select the divider and switching-unit outputs according to Kalkunte’s destination-based egress selection, thereby providing parallel paths directed toward the identified destination die (McKenzie, col. 1, ll. 48–55; Chang, col. 17, ll. 35–46 and col. 17, l. 60–col. 18, l. 10; Kalkunte, col. 4, l. 50–col. 5, l. 25).
Regarding Claim 15: Testa, McKenzie, Chang, and Kalkunte disclose the method of Claim 14
Testa teaches wherein the die is one of a plurality of dies, by disclosing (paragraph [0093]: “different parts of the switch fabric 68 may be constructed from several connected semiconductor dies”).
Testa, McKenzie, and Kalkunte do not expressly teach wherein the die is one of a plurality of dies comprising a plurality of die sets, wherein each of the plurality of die sets comprises a first interface, a second interface, a third interface, and a further interface; wherein, for two respective dies in a same die set, third interfaces of the two dies are coupled, and wherein for two respective dies in different die sets, second interfaces of the two dies are coupled.
Chang discloses switching components arranged in stages and coupled through independent conduits (col. 6, ll. 5–29: “a three-stage or layer Clos network topology having a middle stage of switch fabric components . . . connecting a pair of outer stages of switch fabric components”) and further discloses (col. 6, ll. 29–46: “each outer stage switch fabric component . . . is directly coupled via independent conduits to each of the middle stage switch fabric components”; further, “each of the middle stage switch fabric components . . . is directly coupled via independent conduits to each of the outer stage switch fabric components”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to organize Testa’s connected dies into die sets corresponding to Chang’s switching-component stages and to use Chang’s independent conduits for the claimed intra-set third-interface and inter-set second-interface couplings, thereby providing separate communication paths among the dies (Chang, col. 6, ll. 5–46).
Claims 5–7 are rejected under 35 U.S.C. 103 as being unpatentable over Testa, McKenzie and Chang, and further in view of Blumrich et al. (US 2021/0344616 A1).
Regarding Claim 5: Testa, McKenzie, and Chang disclose the apparatus of Claim 1
Testa, McKenzie, and Chang do not expressly teach wherein each die comprises M×N switching slices, each of the M×N switching slices comprises a splitter, a respective switching unit, a respective combiner, a respective first interface, a respective second interface, a respective third interface, and a respective fourth interface, and M and N are positive integers; and wherein the respective second interfaces of respective switching slices that belong to a same row in the M×N switching slices are coupled through a first bus, and the respective third interfaces of respective switching slices that belong to a same column are coupled through a second bus.
Blumrich teaches wherein each die comprises M×N switching slices by disclosing (paragraph [0024] “a two-dimensional array of identical crossbar tiles, with R rows and C columns”), wherein each tile includes inputs, outputs, and switching elements (see also Fig. 2) and further teaches wherein the respective second interfaces of respective switching slices that belong to a same row in the M×N switching slices are coupled through a first bus, and the respective third interfaces of respective switching slices that belong to a same column are coupled through a second bus, by disclosing row-wise interconnections between tiles in the same row and column-wise interconnections between tiles in the same column (paragraphs [0025]–[0027]; Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to arrange the splitter, switching unit, combiner, and interface structures of the Testa-McKenzie-Chang apparatus as Blumrich’s M×N tiled array and to connect slices in the same row and column through respective buses, thereby providing a regular and scalable switching architecture with simplified interconnection (Blumrich, paragraphs [0024]–[0027]; Fig. 2).
Regarding Claim 6: Testa, McKenzie, Chang, and Blumrich disclose the apparatus of Claim 5
Testa teaches wherein the plurality of dies comprise a first die and a second die, by disclosing (paragraph [0093] “different parts of the switch fabric 68 may be constructed from several connected semiconductor dies”).
Testa, McKenzie, and Chang do not expressly teach wherein the M×N switching slices comprised in the first die are in a one-to-one correspondence with the M×N switching slices comprised in the second die.
Blumrich teaches a two-dimensional arrangement of identical switching tiles, by disclosing (paragraph [0024] “a two-dimensional array of identical crossbar tiles, with R rows and C columns”; see also Fig. 2).
Testa, McKenzie, and Blumrich do not expressly teach wherein the respective third interfaces of two corresponding switching slices are coupled.
Chang teaches ports of a switching component coupled to adjacent switching components, (col. 17, l. 60–col. 18, l. 2: “each switch fabric component has two ports coupled to the two adjacent switch fabric components”). Chang further discloses (col. 18, ll. 2–10: “ports 5/1 and 6/1 of SF1 2202a are coupled to ports 2/2 and 1/2 of SF2 2202b, respectively, and ports 7/1 and 8/1 of SF1 2202a are coupled to ports 4/3 and 3/3 of SF3 2202c, respectively”; see also Fig. 22).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide first and second dies with matching M×N tiled arrays, as taught by Blumrich, and to couple interfaces of corresponding slices using Chang’s adjacent-port arrangement, thereby providing one-to-one inter-die communication paths while preserving a regular tiled architecture (Blumrich, paragraph [0024]; Chang, col. 17, l. 60–col. 18, l. 2).
Regarding Claim 7: Testa, McKenzie, Chang, and Blumrich disclose the apparatus of Claim 5
Testa teaches wherein the plurality of dies comprise a first die and a third die, by disclosing (paragraph [0093] “different parts of the switch fabric 68 may be constructed from several connected semiconductor dies”).
Testa, McKenzie, and Chang do not expressly teach wherein the M×N switching slices comprised in the first die are in a one-to-one correspondence with the M×N switching slices comprised in the third die.
Blumrich teaches a two-dimensional arrangement of identical switching tiles, (paragraph [0024]: “a two-dimensional array of identical crossbar tiles, with R rows and C columns”; see also Fig. 2).
Testa, McKenzie, and Blumrich do not expressly teach wherein the respective second interfaces of two corresponding switching slices are coupled.
Chang teaches ports of a switching component coupled to adjacent switching components, (col. 17, l. 60–col. 18, l. 2: “each switch fabric component has two ports coupled to the two adjacent switch fabric components”) and further discloses (col. 18, ll. 2–10: “ports 5/1 and 6/1 of SF1 2202a are coupled to ports 2/2 and 1/2 of SF2 2202b, respectively, and ports 7/1 and 8/1 of SF1 2202a are coupled to ports 4/3 and 3/3 of SF3 2202c, respectively”; see also Fig. 22).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide first and third dies with matching M×N tiled arrays, as taught by Blumrich, and to couple interfaces of corresponding slices using Chang’s adjacent-port arrangement, thereby providing one-to-one inter-die communication paths while preserving a regular tiled architecture (Blumrich, paragraph [0024]; Chang, col. 17, l. 60–col. 18, l. 2).
Claims 10, 12, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Testa, McKenzie and Chang, and further in view of Kumar et al. (US 2016/0127267 A1).
Regarding Claim 10: Testa, McKenzie, and Chang disclose the apparatus of Claim 9
Testa, McKenzie, and Chang do not expressly teach wherein data switched between two dies that belong to different die sets is written into a die in a die set in which a destination die is located.
Kumar teaches destination-side storage of switched data (paragraph [0027] “The egress tile 106 also includes a core 134 with a packet output buffer 136, which provides another point of distributed buffering in the switch architecture”; further, enqueue circuitry 138 is provided “to place cells in the output buffer 136”) and (paragraph [0041] “the egress tile receives the cell data (1234), and links the cell data to a queue in the output buffer 136 (1236)”; see also Fig. 12).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply Kumar’s destination-side buffering to the inter-die-set arrangement of Testa, McKenzie, and Chang so that data switched between different die sets is written into a die in the die set containing the destination die, thereby preserving the data for subsequent destination-side transmission (Kumar, paragraphs [0027] and [0041]).
Regarding Claim 12: Testa, McKenzie, and Chang disclose the apparatus of Claim 9
Testa, McKenzie, and Chang do not expressly teach wherein data switched between two dies that belong to a same die set is written into a source die.
Kumar teaches source-side storage of data before transmission through a switching fabric (paragraph [0027] “The ingress tile 104 includes a core 108 with a packet input buffer 110, which provides one of the several distributed buffers in the switch architecture”; further, enqueue circuitry 112 is provided “to place cells in the input buffer 110”) and (paragraph [0030]: “The input buffer 110 provides a primary buffering point for arriving packets that is located in the same tile containing the ingress port from which the packet was received”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply Kumar’s source-side buffering to the same-die-set arrangement of Testa, McKenzie, and Chang so that data switched between dies in the same die set is written into the source die, thereby preserving the data before transmission through the intra-set path (Kumar, paragraphs [0027] and [0030]).
Regarding Claim 13: Testa, McKenzie, and Chang disclose the apparatus of Claim 1
Testa, McKenzie, and Chang do not expressly teach wherein the data switching apparatus is part of a chip.
Kumar teaches wherein the data switching apparatus is part of a chip, by disclosing implementation of multiple switching-tile instances in a single integrated circuit (paragraph [0020] “when the multiple instances are fabricated into a single integrated circuit, the resulting switch architecture achieves extremely low latency transfer of packets through a distributed buffering architecture that supports both SAF and CT modes”) and discloses that the switch architecture “may be fabricated on a single die” (paragraph [0021]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to fabricate the Testa-McKenzie-Chang data switching apparatus as part of a chip, as taught by Kumar, thereby providing an integrated switching architecture with reduced latency (Kumar, paragraphs [0020]–[0021]).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Testa, McKenzie, Chang, and Kumar, and further in view of Blumrich et al. (US 2021/0344616 A1).
Regarding Claim 11: Testa, McKenzie, Chang, and Kumar disclose the apparatus of Claim 10
Testa, McKenzie, Chang, and Kumar do not expressly teach wherein when a source die and the destination die in the two dies belong to a same row or column” or “when a source die and the destination die in the two dies belong to different rows or columns.
Blumrich discloses a two-dimensional arrangement of switching tiles in rows and columns (paragraph [0024] “a two-dimensional array of identical crossbar tiles, with R rows and C columns”) further discloses (paragraph [0025]: “Each row of crossbar tiles is supplied by I switch input ports, and each switch input port is coupled to all C tiles in a row of the crossbar array. The outputs from the R crossbar tiles in each column are point-to-point connections that are each connected to a column bus”; see also Fig. 2).
Testa, McKenzie, Chang, and Blumrich do not expressly teach the data is written into the destination die; or . . . the data is written into a die that is in the die set in which the destination die is located and that is in a same row or column as the source die.
Kumar discloses receipt and storage of switched data at an egress tile, (paragraph [0041]: “the egress tile receives the cell data (1234), and links the cell data to a queue in the output buffer 136 (1236)”; see also Fig. 12).
Neither Blumrich nor Kumar expressly discloses the complete limitation wherein when a source die and the destination die in the two dies belong to a same row or column, the data is written into the destination die; or when a source die and the destination die in the two dies belong to different rows or columns, the data is written into a die that is in the die set in which the destination die is located and that is in a same row or column as the source die.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply Blumrich’s row-and-column paths to Kumar’s destination-side buffering so that data is written into the destination die when the source and destination share a row or column, or into an aligned die in the destination die set when they do not, thereby simplifying routing through the established row-and-column paths (Blumrich, paragraphs [0024]–[0025]; Kumar, paragraph [0041]).
Claims 16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Testa, McKenzie, Chang, further in view of Kalkunte et al. (US 6,950,430 B2), and further in view of Kumar et al. (US 2016/0127267 A1).
Regarding Claim 16: Testa, McKenzie, Chang, and Kalkunte disclose the method of Claim 15
Testa, McKenzie, Chang, and Kalkunte do not expressly teach wherein data switched between two dies that belong to different die sets is written into a die in a die set in which a destination die is located.
Kumar teaches destination-side receipt and storage of switched data an egress tile having an output buffer (paragraph [0027] “The egress tile 106 also includes a core 134 with a packet output buffer 136, which provides another point of distributed buffering in the switch architecture”; further, enqueue circuitry 138 is provided “to place cells in the output buffer 136”) and (paragraph [0041]: “the egress tile receives the cell data (1234), and links the cell data to a queue in the output buffer 136 (1236)”; see also Fig. 12).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply Kumar’s destination-side buffering to the inter-die-set arrangement of Testa, McKenzie, Chang, and Kalkunte so that data switched between different die sets is written into a die in the die set containing the destination die, thereby preserving the data for continued destination-side forwarding (Kumar, paragraphs [0027] and [0041]).
Regarding Claim 19: Testa, McKenzie, Chang, and Kalkunte disclose the method of Claim 15
Testa, McKenzie, Chang, and Kalkunte do not expressly teach wherein data switched between two dies that belong to a same die set is written into a source die.
Kumar teaches source-side storage of data before transmission through a switching fabric (paragraph [0027] “The ingress tile 104 includes a core 108 with a packet input buffer 110, which provides one of the several distributed buffers in the switch architecture”; further, enqueue circuitry 112 is provided “to place cells in the input buffer 110”) and (paragraph [0030] “The input buffer 110 provides a primary buffering point for arriving packets that is located in the same tile containing the ingress port from which the packet was received”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply Kumar’s source-side buffering to the intra-die-set arrangement of Testa, McKenzie, Chang, and Kalkunte so that data switched between dies in the same die set is written into the source die, thereby preserving the data before transmission through the intra-set path (Kumar, paragraphs [0027] and [0030]).
Claims 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Testa, McKenzie, Chang, further in view of Kalkunte et al. (US 6,950,430 B2, further in view of Kumar et al. (US 2016/0127267 A1), and further in view of Blumrich et al. (US 2021/0344616 A1).
Regarding Claim 17: Testa, McKenzie, Chang, Blumrich, Kalkunte, and Kumar disclose the method of Claim 16
Testa, McKenzie, Chang, Kalkunte, and Kumar do not expressly teach wherein a source die and the destination die in the two dies belong to a same row or column.
Blumrich discloses a two-dimensional arrangement of switching tiles in rows and columns (paragraph [0024] “a two-dimensional array of identical crossbar tiles, with R rows and C columns”) and further discloses (paragraph [0025] “Each row of crossbar tiles is supplied by I switch input ports, and each switch input port is coupled to all C tiles in a row of the crossbar array. The outputs from the R crossbar tiles in each column are point-to-point connections that are each connected to a column bus”; see also Fig. 2).
Testa, McKenzie, Chang, Kalkunte, and Blumrich do not expressly teach and the data is written into the destination die.
Kumar discloses receipt and storage of cell data at an egress tile, (paragraph [0041] “the egress tile receives the cell data (1234), and links the cell data to a queue in the output buffer 136 (1236)”; see also Fig. 12).
Neither Blumrich nor Kumar expressly discloses the complete limitation wherein a source die and the destination die in the two dies belong to a same row or column, and the data is written into the destination die.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the receipt and storage disclosed by Kumar to the row-and-column arrangement disclosed by Blumrich such that “a source die and the destination die in the two dies belong to a same row or column, and the data is written into the destination die,” using Blumrich’s row and column connections to direct the data to the egress-side storage disclosed by Kumar (Blumrich, paragraphs [0024]–[0025] and Fig. 2; Kumar, paragraph [0041] and Fig. 12).
Regarding Claim 18: Testa, McKenzie, Chang, Blumrich, Kalkunte, and Kumar disclose the method of Claim 16
Testa, McKenzie, Chang, Kalkunte, and Kumar do not expressly teach wherein a source die and the destination die in the two dies belong to different rows or columns, and the data is written into a die that is in the die set in which the destination die is located and that is in a same row or column as the source die.
Blumrich discloses a two-dimensional arrangement of switching tiles in rows and columns (paragraph [0024] “a two-dimensional array of identical crossbar tiles, with R rows and C columns”) and further discloses (paragraph [0025] “Each row of crossbar tiles is supplied by I switch input ports, and each switch input port is coupled to all C tiles in a row of the crossbar array. The outputs from the R crossbar tiles in each column are point-to-point connections that are each connected to a column bus”; see also Fig. 2).
Kumar discloses receipt and storage of cell data at an egress tile, (paragraph [0041]: “the egress tile receives the cell data (1234), and links the cell data to a queue in the output buffer 136 (1236)”; see also Fig. 12).
Neither Blumrich nor Kumar expressly discloses the complete limitation wherein a source die and the destination die in the two dies belong to different rows or columns, and the data is written into a die that is in the die set in which the destination die is located and that is in a same row or column as the source die.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the receipt and storage disclosed by Kumar to the row-and-column arrangement disclosed by Blumrich such that “a source die and the destination die in the two dies belong to different rows or columns, and the data is written into a die that is in the die set in which the destination die is located and that is in a same row or column as the source die,” using Blumrich’s row and column connections to direct the data to the egress-side storage disclosed by Kumar (Blumrich, paragraphs [0024]–[0025] and Fig. 2; Kumar, paragraph [0041] and Fig. 12).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HASAN CHEEMA whose telephone number is (571)272-8722. The examiner can normally be reached Mon-Fri 8:00-5:00 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ayman Abaza can be reached at (571) 270-0422. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/H.A.C./Examiner, Art Unit 2465
/YEE F LAM/Primary Examiner, Art Unit 2465
Prosecution Insights