DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 16-21 is rejected under 35 U.S.C. 102(a)(b) as being anticipated by
Bulzacchelli et al. (US 2018/10097383 B1).
Regarding claim 16: Bulzacchelli, Fig. 4, teaches a method of decision feedback equalization comprising: sampling a current symbol (represented by differential input voltages VIP, VIN received at input stage 401) on an edge of a clock signal (CLK90) (column 9, lines 52- 63); converting the sampled current symbol (received as differential input voltages VIP, VIN at input stage 401) into a first current (from input stage 401 to current injection node 420A) and a second current (from input stage 401 to current injection node 420B) (column 9, lines 52- column 10, line 2); receiving a first digital code (Qo[0], QBo[0] indicating a level decision for a first previous symbol) (column 10, lines 48-50, 54-56); generating a third current (from DFE 460 to current injection node 420A) and a fourth current (from DFE 460 to current injection node 420B) based on the first digital code (Qo[0], QBo[0] indicating a level decision for a first previous symbol) (column 10, lines 27-30, 42- 45); combining the first current (current generated by input stage 401 and delivered to current at injection node 420A) and the third current (current generated by DFE 460 and delivered to current at injection node 420A) to obtain a first combined current (Fig. 4, combined current at current injection node 420A) (column 10, lines 42-45); combining the second current (current generated by input stage 401 and delivered to current at injection node 420B) and the fourth current (current generated by DFE 460 and delivered to current at injection node 420B) to obtain a second combined-current (Fig. 4, combined current at current injection node 420B) (column 10, lines 42-45); converting the first combined current (combined current at current injection node 420A) into a first output voltage (QN) using a transimpedance amplifier (latch 403); and converting the second combined current (combined current at current injection node 420B) into a second output voltage (QP) using the transimpedance amplifier (latch 403) (column 10, lines 8-13, 42-45).
Regarding claim 17: Bulzacchelli, Fig. 4, teaches a generating the first digital code (Qo[0], QB0[0]) on the edge of the clock signal (CLK90) (column 9, lines 23-26, lines 37-50; column 10, lines 48-56).
Regarding claim 18: Bulzacchelli teaches the edge of the clock signal (CLK90) is a rising edge (Fig. 6, column 3, lines 1-13).
Regarding claim 19: Bulzacchelli teaches receiving a sequence of symbols including the current symbol (received by input stage 401 as a PAM4) (column 9, lines 30-31; column 10, lines 30-32, 55-56) and the first previous symbol (feedback data Qo[2:0]; column 10, lines 27-30), wherein half a period of the clock signal is equal to a unit interval (UI) of the sequence of symbols (Fig. 6, column 14, lines 32-39).
Regarding claim 20: Bulzacchelli teaches the first previous symbol (H1) is delayed from the current symbol by the UI (column 3, lines 6-12; column 4, lines 26-40; column 14, lines 31-36).
Regarding claim 21: Bulzacchelli teaches the first digital code comprises a first thermometer code (Qo[2:0]) indicating a first one of four pulse amplitude modulation 4-level (PAM-4) levels (column 5, lines 60-61; column 10, lines 27-30; column 9 lines 30-31).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Bulzacchelli et al. (US 2018/10097383 B1) in view of Pertijs (US 2010/7834685 B1).
Regarding claim 1. Bulzacchelli, Fig. 4, teaches an a summer (400) comprising: an adding slicer 400 comprising decision-making slicer circuit 450 and 1st-tap DFE feedback circuit (460) (column 8, lines 42-46); a first transconductance amplifier (401) (column 9, lines 52-53, lines 60-61) wherein input stage 401 generates currents at current injection nodes (420A and 420B) to receive a differential input voltage (VIP/VIN); a transimpedance amplifier (Latch 403 is an equivalent summing/output stage as a TIA. It receives summed currents at injection nodes 420A/420B and produces output voltages QN/QP), wherein a first output (current injection node 420A) of the first transconductance amplifier (401) is coupled to a first input (420A) of the transimpedance amplifier (latch 403) and a second output (current injection node 420B) of the first transconductance amplifier (401) is coupled to a second input (420B) of the transimpedance amplifier (latch 403) (column 8, lines 57-60, and column 10, lines 41-45); a second transconductance amplifier (feedback circuit 460 comprising adder circuits 430(0)-430(2) configured to receive a digital code representing a previously decided symbol and generate differential currents injected into current injection nodes 420A and 420B), wherein a tap input (Qo[0]/QBo[0]) of the second transconductance amplifier (DFE 460) is configured to receive a first digital code (Qo[0]/QBo[0]) indicating a level decision for a first previous symbol (column 10, lines 48-59, column 11, lines 1-12); a first output (420A) of the second transconductance amplifier (DFE 460) is coupled to the first input (corresponds to current injection node 420A) of the transimpedance amplifier (latch 403), and a second output (420B) of the second transconductance amplifier (DFE 460) is coupled to the second input (corresponds to current injection node 420B) of the transimpedance amplifier (latch 403) (column 10, lines 57-59). However, Bulzacchelli does not disclose sampling input differential signal switches.
Pertijs, Fig. 1, teaches a first switch (110) coupled between a first input of the summer and a first input of the first transconductance amplifier (102) wherein the received input signal is coupled through switching/sampling circuitry to the transconductance stage (column 2, lines 53-56); a second switch (114) coupled between a second input of the summer and a second input of the first transconductance amplifier (104) wherein the differential input signal is coupled through switching/sampling circuitry to the transconductance stage (column 2, lines 53-54, column 3, lines 1-3).
It would have been obvious to one of having ordinary skill in the art at the time the invention was effectively filed to modify input stage of Bulzacchelli’s to include the input-side switching circuitry of Pertijs in order to provide controlled clocked sampling and coupling of the differential input signal to the transconductance stage, thereby improving signal conditioning and reducing offset/noise effects.
Regarding claim 2: Bulzacchelli doesn’t disclose a first and second switch are driven by a clock signal. Pertijs, Fig. 1, teaches the first switch (110) and the second switch (114) are driven by a clock signals (column 3, lines 6-12).
It would have been obvious to one of having ordinary skill in the art at the time the invention was effectively filed to modify Bulzacchelli to utilize the clock-driven switches of Pertijs in order to provide predictable timing control of signal transfer through the input switching circuitry, thereby allowing signal processing operations to occur in synchronization with a clock signal
Regarding claim 3: Bulzacchelli, Fig. 4, further discloses the first digital code ((Qo[0]/QBo[0]) indicating a level decision for a first previous symbol (column 10, lines 48-59, column 11, lines 1-12), comprises a thermometer code ((Qo[2:0] controlling adder circuits 430(0)-430(2) for a PAM4 input signal) indicating one of four pulse amplitude modulation 4-level (PAM-4) levels (column 10, lines 25-30).
Regarding claim 4: Bulzacchelli, Fig. 4, further discloses the transimpedance amplifier (latch 403) (column 10, lines 7-13, column 11, lines 1-24) comprises: a first inverter amplifier (transistors 410A, 414A), wherein an input (corresponding to current injection node 420A) of the first inverter amplifier (transistors 410A, 414A) is coupled to the first input (corresponds to current injection node 420A) of the transimpedance amplifier (latch 403), and an output (QN) of the first inverter amplifier (transistors 410A, 414A) is coupled to a first output (QN) of the transimpedance amplifier (latch 403); and a second inverter amplifier (transistors 410B, 414B), wherein an input (corresponding to current injection node 420B) of the second inverter amplifier (transistors 410B, 414B) is coupled to the second input (corresponds to current injection node 420B) of the transimpedance amplifier (latch 403), and an output (QP) of the second inverter amplifier (transistors 410B, 414B) is coupled to a second output (QP) of the transimpedance amplifier (latch 403).
Claims 5, 6 are rejected under 35 U.S.C. 103 as being unpatentable over Bulzacchelli et al. (US 2018/10097383 B1) in view of Pertijs (US 2010/7834685 B1) as applied to claim above, and further in view of Cevrero et al. (US 2019/0081600 A1).
Regarding claim 5: Bulzacchelli as modified by Pertijs does not disclose the first inverter amplifier comprises a first feedback resistor coupled between the input of the first inverter amplifier and the output of the first inverter amplifier; and the second inverter amplifier comprises a second feedback resistor coupled between the input of the second inverter amplifier and the output of the second inverter amplifier.
Cevrero, Fig. 2, (paragraph [0040]) teaches a first feedback resistor (Rf1) coupled between inverting output port 240 of the transimpedance (TIA) stage 220 and inverting output port 105 of the transadmittance amplifier 100; and a second feedback resistor (Rf2) coupled between non-inverting output (port 241 of the TIA stage 220) and non-inverting output (port 106) of the transadmittance amplifier (100).
It would have been obvious to one of having ordinary skill in the art at the time the invention was effectively filed to incorporate the feedback resistor arrangement of Cevrero into the combination of Bulzacchelli and Pertijs to provide tunable driving capability and improved amplifier performance (Cevrero, paragraph [0041]-[0042]).
Regarding claim 6: Bulzacchelli as modified by Pertijs does not disclose the first feedback resistor comprises a first variable resistor, and the second feedback resistor comprises a second variable resistor.
Cevrero, Fig. 2, the first feedback resistor (Rf1) and the second feedback resistor (RF2) depicted as variable resistors, wherein the resistors are tunable to tune driving capability and their resistance values may be adjusted (paragraphs [0041]-[0042]).
It would have been obvious to one of having ordinary skill in the art at the time the invention was effectively filed to modify the combination of Bulzacchelli and Pertijs with a first and second variable resistors as taught by Cevrero in order to tune driving capability, therefore, give independent control over gain and bandwidth, improving amplifier performance.
Claims 14, 15 are rejected under 35 U.S.C. 103 as being unpatentable over
Bulzacchelli et al. (US 2018/10097383 B1) in view of Pertijs (US 2010/7834685 B1) as applied to claim 1 above, and further in view of Dong et al. (US 2020/10848353 B1).
Regarding claim 14, Bulzacchelli as modified, fig. 4, further teaches a third transconductance amplifier (adder circuits 430(0)-430(2)) wherein a first output (first current injection node 420A) of the third transconductance amplifier (adder circuits 430(0)-430(2)) is coupled to the first input (first current injection node 420A) of the transimpedance amplifier (decision-making slicer/latch 450/403), and a second output (second current injection node 420B) of the third transconductance amplifier (adder circuits 430(0)-430(2)) is coupled to the second input (second current injection node 420B) of the transimpedance amplifier (decision-making slicer/latch 450/403). However, Bulzacchelli as modified by Pertijs does not teach a second digital code indicating a level decision for a second previous symbol.
Dong, fig. 5, teaches wherein a tap input (tap2_n, Tap2_p) of a third transconductance amplifier is configured to receive a second digital code (h(2)) indicating a level decision for a second previous symbol (tap2_n, Tap2_p represent a second time delayed signal of the detected symbol; column 10, lines 45-56).
It would have been obvious to one of having ordinary skill in the art at the time the invention was effectively filed to modify the combination of Bulzacchelli and Pertijs to utilize Dong’s second delayed-symbol feedback tap in order to compensate for intersymbol interference associated with symbols occurring further in the past, thereby improving equalization performance.
Regarding claim 15: Bulzacchelli as modified, fig. 4, further teaches the first digital code (Qo[2:0] is also first thermometer code) (column 10, Lines 27-30), indicating a first one of four pulse amplitude modulation 4-level (PAM-4) levels (column 5, lines 60-61) and comprises a second thermometer indicating a second one of the four PAM-4 levels (column 9, lines 30-31, column 11, lines 25-27). However, Bulzacchelli as modified by Pertijs does not teach the second digital code indicating a level decision for a second previous symbol.
Dong, fig. 5, teaches the second digital code (Tap2/h(2)) indicating a level decision for a second previous symbol, wherein Tap2_n and Tap2_p represent a second time delayed signal of the detected symbol and weighted feedback tap h(2) is generated from the second time delayed signal. (column 10, lines 45-50).
It would have been obvious to one of having ordinary skill in the art at the time the invention was effectively filed to modify the feedback circuitry of the combination of Bulzacchelli and Pertijs to utilize Dong’s second delayed-symbol feedback path in order to provide additional compensation for intersymbols occurring further in the past, thereby improving equalization performance.
Claims 22, 23 are rejected under 35 U.S.C. 103 as being unpatentable over Bulzacchelli et al. (US 2018/10097383 B1) in view of Dong et al. (US 2020/10848353 B1).
Regarding claim 22: Bulzacchelli Fig. 5, further discloses receiving a first digital code representing a previously decided symbol and generating currents therefrom using adder circuits (430(0)-430(2)), which inject currents into current injection nodes 420A and 420B (column 10, lines 27-30) and combining multiple current contributions at the injection nodes prior to the decision-making slicer/latch. However, Bulzacchelli does not teach receiving a second digital code indicating a level decision for a second previous symbol and generating additional currents therefrom for inclusion in the combined current paths.
Dong teaches receiving a second digital code (Tap2_n and Tap2_p) indicating a level decision for a second previous symbol; wherein Tap2_n and Tap2_p are associated with delay element L2 and weighted feedback tap h(2) is generated from a signal delayed by two time instances (column 6, lines 54-60, column 7, lines 11-23), and generating current 513 from h(2), whereas current 514 is the sum of currents 511, 512 and 513 (column 10, lines 45-50).
It would have been obvious to one of having ordinary skill in the art at the time the invention was effectively filed to modify Bulzacchelli’s feedback circuitry to incorporate Dong’s second-delayed-symbol feedback tap h(2) because Dong teaches that additional delayed-symbol feedback currents may be summed with existing feedback currents to compensate for intersymbol interference associated with symbols occurring further in the past, thereby reducing residual intersymbol interference distortion, improving symbol detection accuracy and equalization performance.
Regarding claim 23: Bulzacchelli further discloses the first digital code comprises a first thermometer code (Qo[2:0]) indicating a first one of four pulse amplitude modulation 4-level (PAM-4) levels (column 5, lines 60-61; column 10, lines 27-30; column 9 lines 30-31); and the second digital code comprises a second thermometer code indicating a second one of the four PAM-4 levels because the thermometer-coded symbol decisions are likewise applicable to subsequently delayed symbol decisions. (column 10, lines 27-30).
Allowable Subject Matter
Claims 7-13 are objected to as being dependent upon a rejected base claim,
but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATASHA Y MARANO whose telephone number is (571)272-9512. The examiner can normally be reached Mon - Fri 7:30am - 3:30pm.
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/Jessica Han/Supervisory Patent Examiner, Art Unit 2843
/NATASHA Y. MARANO/
Examiner
Art Unit 2843
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