Prosecution Insights
Last updated: July 17, 2026
Application No. 18/412,683

IMAGING DEVICE

Final Rejection §103§112
Filed
Jan 15, 2024
Priority
Aug 05, 2021 — JP 2021-129386 +1 more
Examiner
RAHAMAN, SHAHAN UR
Art Unit
2426
Tech Center
2400 — Computer Networks
Assignee
Panasonic Holdings Corporation
OA Round
2 (Final)
76%
Grant Probability
Favorable
3-4
OA Rounds
4m
Est. Remaining
89%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allowance Rate
498 granted / 654 resolved
+18.1% vs TC avg
Moderate +13% lift
Without
With
+12.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
35 currently pending
Career history
698
Total Applications
across all art units

Statute-Specific Performance

§101
0.9%
-39.1% vs TC avg
§103
74.4%
+34.4% vs TC avg
§102
2.6%
-37.4% vs TC avg
§112
2.3%
-37.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 654 resolved cases

Office Action

§103 §112
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Following prior arts are considered pertinent to applicant's disclosure. US20160079297 A1 (Sato97) US 20180315786 A1 (Hirase) WO2020137188 A1 (WO88; US 20210288115 A1 is the equivalent English document) US 20180083004 A1 (Sato04) US 20190371839 A1 (Fig.4 shows different width and area of gate ) Response to Remarks/Arguments Applicant’s arguments with respect to claim rejection have been fully considered but they are not persuasive for following reason. Re: Prior art rejection of independent claims Applicant argued in substance that the prior art does not teach that a thickness of the first gate-insulating film is greater than a thickness of the second gate-insulating film . Specifically, because Hirase also teaches the opposite. Examiner respectfully disagrees with such conclusion. In fact, given that Hirase teaches a thickness of the first gate-insulating film is greater than a thickness of the second gate-insulating film or the opposite, indicates that having a thickness of the first gate-insulating film is greater than a thickness of the second gate-insulating film is not patentable feature. Such feature is well known and easily used at will in the art. In fact, applicant claim also casually mentioned this without tying to any specific patentably distinct features. Therefore, applicant’s arguments are not persuasive Re: Prior art rejection of dependent claims Applicant has presented no additional argument, other than arguments already presented with respect to independent claims. Therefore, the arguments are similarly not persuasive. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(d): (d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers. The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph: Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers. Claim 15 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to include all the limitations of the claim upon which it depends. For instance, a first thickness of 6.5 nm and second thickness of 11 nm does not satisfy claim 1. Each point of the range should satisfy the constrained provided in claim 1. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements. Claim Objection (Allowable Subject Matter) Claims 15-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1-4, 10-14 are rejected under 35 U.S.C. 103 as being unpatentable over Sato97 in view of Hirase. Regarding Claim 1. Sato97 teaches an imaging device [(Figs 1 and Fig.8)] comprising: a semiconductor substrate [(#31)] : an impurity region that is located in the semiconductor substrate and that holds electric charge generated through photoelectric conversion [(para 62-63)] : a first transistor including a first source, a first drain, a first gate, and a first gate-insulating film, one of the first source and the first drain including the impurity region, the first gate being electrically connected to the impurity region, the first gate-insulating film being located between the first gate and the semiconductor substrate:[(Fig.8 and para 115; burn-in prevention transistor 60; gate 39D is connected to the charge accumulation region through 45 {Fig.8} )] and a second transistor including a second gate and a second gate-insulating film, the second gate being electrically connected to the impurity region, the second gate-insulating film being located between the second gate and the semiconductor substrate,:[(Fig.8 and para 64; the feedback amplifying transistor 11; gate 39B is connected to the charge accumulation region through 45 {Fig.8}; also see para 34 )] Sato97 does not explicitly show wherein a thickness of the first gate-insulating film is greater than a thickness of the second gate-insulating film However, in the same/related field of endeavor, Hirase teaches a thickness of the first gate-insulating film is greater than a thickness of the second gate-insulating film [(para 122 “the film thickness itself of the first gate insulating film 38g of the feedback transistor 38 may be smaller than the film thickness of the second gate insulating film 36g of the reset transistor 36”; “The film thickness of the first gate insulating film 38g may become larger than the thickness of the second gate insulating film 36g,”; also see para 121)] Therefore, in light of above discussion it would have been obvious to one of the ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teaching of the prior arts because as can be seen from Hirase two transistor can have different gate insulator thickness, Hirase teaches either one can be thicker than other [(Hirase para 121-122)] depending on the design and material, therefore such well known design choice can easily be incorporated into Sato97. [(Hirase also teaches the thickness can be same in para 88)] Claim 2. The imaging device according to claim 1, further comprising a photoelectric converter that is located above the semiconductor substrate and that generates the electric charge through photoelectric conversion. [(Sato97 #10; Fig.2 or 8)] Claim 3. The imaging device according to claim 1, further comprising a third transistor including a third source, a third drain, a third gate, and a third gate-insulating film, one of the third source and the third drain including the impurity region, the third gate-insulating film being located between the third gate and the semiconductor substrate. [(Sato97 #10; Fig.1 & 8)] Claim 4. The imaging device according to claim 3, wherein a thickness of the third gate-insulating film is greater than the thickness of the second gate-insulating film. [(Hirase Fig.3 shows three transistors with different gate thickness)] Claim 10. The imaging device according to claim 1, wherein the second transistor is an amplification transistor. [(Sato97 para 64)] Claim 11. The imaging device according to claim 3, wherein the thickness of the first gate-insulating film is greater than a thickness of the third gate-insulating film. [(Hirase Fig.3 shows three transistors with different gate thickness)] Claim 12. The imaging device according to claim 3, wherein the thickness of the second gate-insulating film is equal to a thickness of the third gate-insulating film [(Sato97 Fig.2 and Hirase describing any transistor thickness can be thicker)] Claim 13. The imaging device according to claim 2, wherein the photoelectric converter is constantly electrically connected to the impurity region. [(Sato97 Figs 1 and Fig.8)] Claim 14. The imaging device according to claim 2, wherein no switch element is located between the photoelectric converter and the impurity region. [(Sato97 Figs 1 and Fig.8)] Claims 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Sato97 in view of Hirase in view of WO88. Regarding Claim 5. Sato97 in view of Hirase does not explicitly show a width of the first gate is less than a width of the second gate. However, in the same/related field of endeavor, WO88 teaches a width of the first gate is less than a width of the second gate [(see Fig.4 and Fig.3; Fig.4 shows 22e and 27e have different width Fig.3 shows these are the width of the respective gate insulations)] Therefore, in light of above discussion it would have been obvious to one of the ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teaching of the prior arts because such combination would provide predictable result with no change of their respective functionalities. Claim 6. The imaging device according to claim 1, wherein an area of the first gate is less than an area of the second gate in a plan view. [(see Fig.4)] Claim 7. The imaging device according to claim 1, wherein a ratio of a length of the first gate relative to a width of the first gate is greater than a ratio of a length of the second gate relative to a width of the second gate. [( see Fig.4 )] Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Sato97 in view of Hirase in view of Sato04. Regarding Claim 8. Sato97 in view of Hirase teaches a thickness of the first part is greater than a thickness of the second part (see analysis of claim 1) Sato97 in view of Hirase does not explicitly show an insulating layer, wherein the insulating layer includes a first part and a second part, the first part including the first gate-insulating film, the second part including the second gate-insulating film, a thickness of the first part is greater than a thickness of the second part, and when a shortest line segment connecting the first gate and the second gate in a plan view is defined as a specific line segment and a middle point of the specific line segment is defined as a specific point, the specific point is located on the first part in the plan view However, in the same/related field of endeavor, Sato04 teaches an insulating layer, wherein the insulating layer includes a first part and a second part, the first part including the first gate-insulating film, the second part including the second gate-insulating film, a thickness of the first part is greater than a thickness of the second part, and when a shortest line segment connecting the first gate and the second gate in a plan view is defined as a specific line segment and a middle point of the specific line segment is defined as a specific point, the specific point is located on the first part in the plan view [(Figs. 5-8 and also see Figs. 21-32)] Therefore, in light of above discussion it would have been obvious to one of the ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teaching of the prior arts because such combination would provide predictable result with no change of their respective functionalities. Claim 9. The imaging device according to claim 1, further comprising: an insulating layer: and a wire electrically connected to the first gate, wherein the insulating layer includes a first part and a second part, the first part including the first gate-insulating film, the second part including the second gate-insulating film, a thickness of the first part is greater than a thickness of the second part, and when a region in which the semiconductor substrate, the first part, and the wire are arranged in the stated order in a thickness direction of the semiconductor substrate is defined as a specific region, the specific region extends from inside of the first gate to outside of the first gate in a plan view. [(see analysis of claim 8 and Figs. 5-8 and also see Figs. 21-32 of Sato04)] Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shahan Rahaman whose telephone number is (571)270-1438. The examiner can normally be reached on 7am - 3:30pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Nasser Goodarzi can be reached at telephone number (571) 272-4195. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300. Information regarding the status of an application may be obtained from Patent Center. Status information for published applications may be obtained from Patent Center. Status information for unpublished applications is available through Patent Center for authorized users only. Should you have questions about access to Patent Center, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) Form at https://www.uspto.gov/patents/uspto-automated- interview-request-air-form. /SHAHAN UR RAHAMAN/Primary Examiner, Art Unit 2426
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Prosecution Timeline

Jan 15, 2024
Application Filed
Mar 04, 2026
Non-Final Rejection mailed — §103, §112
May 28, 2026
Response Filed
Jun 26, 2026
Final Rejection mailed — §103, §112 (current)

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Prosecution Projections

3-4
Expected OA Rounds
76%
Grant Probability
89%
With Interview (+12.6%)
2y 10m (~4m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 654 resolved cases by this examiner. Grant probability derived from career allowance rate.

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