Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to application No. 18412793 filed on 01/15/2024.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Election/Restrictions
Applicants’ election with traverse of (species 1 with figures 6 & 7) claims 1-17 in the reply filed on 6/26/2026 is acknowledged.
The traversal is on the ground(s) that “With regard the election requirement between Species I and II, Applicants note that there is a substantial overlap of common elements (a channel layer, a ferroelectric layer, a gate electrode, and a reduced layer) between the alleged species. In view of the substantial overlap, Applicants believe that a significant portion of the patents classified in either one of Species I and II would naturally be found when searching another of Species I and II. In view of the above, Applicants submit that the search and examination of all the alleged Species (e.g., Species I through Species II) may be made without serious burden.
This is not found persuasive because the species require a different field of search (e.g., searching for different classes/subclasses or electronic resources or non-patent language, or deploying different search queries); and/or the prior art applicable to one species would not likely be applicable to another species.
Therefore, the requirement is still deemed proper and is therefore made FINAL.
Allowable subject matter
Claims 5 and 6 are objected to as being dependent upon a rejected base claim
(Independent claim 1), but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is an examiner' s statement of reasons for allowance: The closest prior art known to the Examiner is listed on the PTO 892 forms of record. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Tanaka et al. (US Pat US 2022/0059570 A1).
With respect to dependent claims 5-6, the cited prior art does not anticipate or make obvious, inter alia, the step of: “the reduced layer is spaced apart from one of the n-type oxide semiconductor layer and the p- type oxide semiconductor layer, and in contact with the other one of the n-type oxide semiconductor layer and the p-type oxide semiconductor layer”.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Claim 9 recites the limitation “the reduced layer is between the ferroelectric layer and the channel layer”. The metes and bounds of the claimed limitation cannot be determined for the following reasons: It is unclear what is meant by this limitation as it appears that the elected species (figs. 6 & 7) discloses the reduced layer 340 is between the ferroelectric layer 350 and the pillar 305.
Claim 9 will be interpreted as the reduced layer 340 is between the ferroelectric layer 350 and the pillar 305.
Drawings
The drawings filed on 01/15/2024 are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: Fig. 7 element 302 needs to be corrected as element 301. Corrected drawing sheets in compliance with 37 CFR 1.211(d), or amendment to the specification to add the reference character in the description in complacence with 37 CFR 1.211(b) are required in reply to the office action.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 7, 10 & 12-17 are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka et al. (US 2022/0059570 A1).
Regarding independent claim 1, Tanaka et al. teach a semiconductor device comprising:
a channel layer (fig. 7, elements 102 & 103 [0058]) including an n-type oxide semiconductor layer (fig. 7, element 103 [0058]) and a p- type oxide semiconductor layer (fig. 7, element 102 [0058]);
a ferroelectric layer (fig. 7, element 104 [0051]) on the channel layer;
a gate electrode (figs. 7, element 22 [0056]) on the ferroelectric layer;
a reduced layer (fig. 7, element 105 [0058], paragraph [0058] discloses that the intermediate layer element 105 comprises silicon oxide which is the same material as the instant application) on the channel layer and including an element having greater reducing power than a metal included in the channel layer (element 105 comprises silicon oxide or InGaSiO which has greater reducing power than the metal included in the element 23 which are tin, nickel or indium [0053] [0054] [0058]).
Regarding claim 2, Tanaka et al. teach a semiconductor device,
wherein the element included in the reduced layer is metal having greater reducing power than a metal included in the channel layer (element 105 comprises silicon oxide or InGaSiO and the metal included in the element 23 comprises tin or nickel oxide which are the same material as the instant application [0053] [0054] [0058]).
Regarding claim 3, Tanaka et al. teach a semiconductor device, wherein
the n-type oxide semiconductor layer and the p-type oxide semiconductor layer include different oxygen contents (n-type oxide semiconductor layer element 103 is IGZO an indium gallium zinc oxide or titanium oxide and p-type oxide semiconductor layer element 102 comprises copper oxide, tin oxide or nickel oxide which are the same material as the instant application [0053] [0054]).
Regarding claim 4, Tanaka et al. teach a semiconductor device, wherein
the reduced layer is in contact with one of the n-type oxide semiconductor layer and the p-type oxide semiconductor layer that has a relatively low oxygen content (fig. 7).
Regarding claim 7, Tanaka et al. teach a semiconductor device, wherein
a thickness of the reduced layer is less than or equal to a thickness of one of the n-type oxide semiconductor layer and the p-type oxide semiconductor layer (fig. 7).
Regarding claim 10, Tanaka et al. teach a semiconductor device, wherein
the n-type oxide semiconductor layer and the p-type oxide semiconductor layer are parallel to each other in a thickness direction of the channel layer (fig. 7).
Regarding claim 12, Tanaka et al. teach a semiconductor device, wherein
at least one of the n-type oxide semiconductor layer and the p-type oxide semiconductor layer includes at least one of indium oxide, zinc oxide, tin oxide, nickel oxide, and gallium oxide ([0053] [0054]).
Regarding claim 13, Tanaka et al. teach a semiconductor device, wherein
the reduced layer includes at least one of aluminum oxide, hafnium oxide, and silicon oxide ([0058]).
Regarding claim 14, Tanaka et al. teach a semiconductor device, further comprising:
a source electrode (fig. 7, element SL [0045]) on the channel layer and spaced
apart (fig. 7) from the gate electrode;
and a drain electrode (fig. 2, element 36 [0021]) on the channel layer and spaced apart (fig. 2) from the gate electrode and the source electrode.
Regarding claim 15, Tanaka et al. teach a semiconductor device further comprising:
a pillar (figs. 7, element 101 [0052]) extending in a first direction, wherein
the channel layer surrounds (fig. 7) the pillar,
the ferroelectric layer surrounds (fig. 7) the channel layer,
the gate electrode (figs. 7, element 22 [0056]) surrounds (fig. 7) the ferroelectric layer, and
the reduced layer is between the pillar and the channel layer (fig. 7).
Regarding claim 16, Tanaka et al. teach a semiconductor device, wherein
the n-type oxide semiconductor layer and the p-type oxide semiconductor layer are parallel in a direction perpendicular to the first direction (fig. 7).
Regarding claim 17, Tanaka et al. teach a semiconductor device, wherein
the gate electrode includes a plurality (fig.7) of gate electrodes being apart from each other in the first direction (fig. 7, insulating layer element 21 [0041] separates gate electrodes element 22 apart from each other).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Tanaka et al. (US 2022/0059570 A1) in view of Chang et al. (US 2022/0223741 A1).
Regarding claim 8, Tanaka et al. teach all the limitations as discussed above. Tanka et al. do not explicitly teach the n-type oxide semiconductor layer and the p-type oxide semiconductor layer include same metal.
However, Chang et al. is a pertinent art which teaches a ferroelectric field-effect transistor (FeFET) device comprises n-type oxide semiconductor layer (fig. 19, element 106 [0046]) and p-type oxide semiconductor layer (fig 19, element 112 [0049]) include same metal [0046] [0049].
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Tanaka et al. to include same metal in n-type and p-type semiconductor layer as taught by Chang et al. for any number of reasons such as design considerations, balancing manufacturing cost and time, and the like.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Tanaka et al. (US 2022/0059570 A1) in view of Wang et al. (US 2021/0399137 A1).
Regarding claim 11, Tanaka et al. teach all the limitations as discussed above.
Tanka et al. do not explicitly teach a thickness of the reduced layer is 1 nm or less.
However, Wang et al. is a pertinent art which teaches a ferroelectric field effect transistor comprising oxide material layer (fig. 13, element 151, paragraph [0066] discloses “the thickness of the oxide material layer may be in a range from 0.1 nm to 0.5 nm”).
“In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. MPEP 2144.05.
Cited Prior Art
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARIFUR RAHMAN whose telephone number is (571) 895-1534. The examiner can normally be reached on Monday-Friday, 9:00 AM - 5:00 PM (Eastern Time). If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571) 270-0373. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at (866) 217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call (800) 786-9199 (IN USA OR CANADA) or (571) 272-1000.
/ARIFUR RAHMAN/
Examiner, Art Unit 2813
/SHAHED AHMED/Primary Examiner, Art Unit 2813
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