DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgement is made to a claim of foreign priority to Korean application KR10-2023-0102046 filed on August 4th,2023. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restrictions
Applicant's election without traverse of Species A drawn to figures 4A-B (claims 1-15) in the reply filed on June 8th, 2026 is acknowledged.
The requirement is made FINAL, claims 1-15 are being examined on their merits at this time.
Information Disclosure Statement
The information disclosure statement (IDS) filed on January 15th,2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Specification
The following guidelines illustrate the preferred layout for the specification of a utility application. These guidelines are suggested for the applicant’s use.
Arrangement of the Specification
As provided in 37 CFR 1.77(b), the specification of a utility application should include the following sections in order. Each of the lettered items should appear in upper case, without underlining or bold type, as a section heading. If no text follows the section heading, the phrase “Not Applicable” should follow the section heading:
(a) TITLE OF THE INVENTION.
(b) CROSS-REFERENCE TO RELATED APPLICATIONS.
(c) STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT.
(d) THE NAMES OF THE PARTIES TO A JOINT RESEARCH AGREEMENT.
(e) INCORPORATION-BY-REFERENCE OF MATERIAL SUBMITTED ON A READ-ONLY OPTICAL DISC, AS A TEXT FILE OR AN XML FILE VIA THE PATENT ELECTRONIC SYSTEM.
(f) STATEMENT REGARDING PRIOR DISCLOSURES BY THE INVENTOR OR A JOINT INVENTOR.
(g) BACKGROUND OF THE INVENTION.
(1) Field of the Invention.
(2) Description of Related Art including information disclosed under 37 CFR 1.97 and 1.98.
(h) BRIEF SUMMARY OF THE INVENTION.
(i) BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S).
(j) DETAILED DESCRIPTION OF THE INVENTION.
(k) CLAIM OR CLAIMS (commencing on a separate sheet).
(l) ABSTRACT OF THE DISCLOSURE (commencing on a separate sheet).
(m) SEQUENCE LISTING. (See MPEP § 2422.03 and 37 CFR 1.821 - 1.825). A “Sequence Listing” is required on paper if the application discloses a nucleotide or amino acid sequence as defined in 37 CFR 1.821(a) and if the required “Sequence Listing” is not submitted as an electronic document either on read-only optical disc or as a text file via the patent electronic system.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (US11145594B2).
Regarding claim 1;
Park et al. teaches A memory device (e.g. Fig. 7, Detailed description [0060]-[0062] “FIG. 7 is a diagram for describing memory blocks included in a semiconductor device…the semiconductor device may include a plurality of memory blocks BLK1 to BLKz…each of the plurality of memory blocks BLK1 to BLKz may include the plurality of channel plugs and the dummy plugs as described above with reference to FIGS. 2A and 2B or 6.”) comprising: a stack structure (e.g. Fig.2B ref ST1+ST2) including a plurality of conductive layers and a plurality of interlayer insulating layers, which are alternately stacked along a first direction (e.g. Fig.2B ref 111,102,106; Detailed description [0037] “The first stack ST1 is a structure in which word line conductive film 111 and an interlayer insulating film 102 are alternately stacked, and the second stack ST2 is a structure in which the word line conductive film 111 and an interlayer insulating film 106 are alternately stacked on the first stack ST1.”); an opening extending in the first direction from at least one conductive layer, among the plurality of conductive layers, in the stack structure (e.g. see examiner markup); and a contact plug in the opening (e.g. Fig. 2B ref 109+110; Detailed description [0036] “…plurality of channel plugs may be vertically arranged through the first stack ST1 and the second stack ST2.”), wherein the opening includes a protrusion portion protruding in a second direction intersecting the first direction (e.g. see examiner markup).
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Regarding claim 2;
Park et al. further teaches in figure 2B that the opening includes a first opening and a second opening below the first opening (e.g. see examiner markup).
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Regarding claim 3;
Park et al. further teaches in figure 2B that a width of a top end of the second opening is greater than a width of a bottom end of the first opening (e.g. see examiner markup in claim 2 rejection).
Regarding claim 4;
Park et al. further teaches in figure 2B that a width of a top end of each of the first and second openings is greater than a width of a bottom end of each of the first and second openings (e.g. see examiner markup in claim 2 rejection).
Regarding claim 5;
Park et al. further teaches in figure 2B that, due to the protrusion portion, a top end of each of the first and second openings protrudes into the stack structure as compared with a bottom surface of each of the first and second openings (under BRI examiner is interpreting this limitation to mean that the top end of the first and second openings separate adjacent ends of the conductive layers farther apart compared to the spacing cause by the bottom surface of the first and second openings, please see examiner markup in claim 2 rejection).
Regarding claim 6;
Park et al. further teaches in figure 2B that the stack structure includes a first sub-stack structure including a first conductive layer and a first interlayer insulating layer, the first conductive layer being on top of the first interlayer insulating layer, on top of the at least one conductive layer (e.g. Detailed description [0037] “The first stack ST1 is a structure in which word line conductive film 111 and an interlayer insulating film 102 are alternately stacked…”) and a second sub-stack structure including a second conductive layer and a second interlayer insulating layer, the second conductive layer being on top of the second interlayer insulating layer, on the top of the first sub-stack structure (e.g. Detailed description [0037] “…the second stack ST2 is a structure in which the word line conductive film 111 and an interlayer insulating film 106 are alternately stacked on the first stack ST1.”), and wherein the second sub-stack structure includes the first opening, and the first sub-stack structure includes the second opening (e.g. see examiner markup).
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Regarding claim 7;
Park et al. further teaches in figure 2B that an interface between the first sub-stack structure and the second sub-stack structure corresponds to an interface between the second opening and the first opening (e.g. see examiner markup in claim 6 rejection).
Regarding claim 8;
Park et al. further teaches in figure 2B that a portion of a top surface of the second opening is in contact with a bottom surface of the second interlayer insulating layer (e.g. see examiner markup in claim 6 rejection).
Regarding claim 9;
Park et al. further teaches in figure 2B that a spacer formed along an inner wall of the opening (e.g. Fig. 2B ref 108; Detailed description [0049] “the memory patterns 108 may be formed in the first channel hole H1 and the second channel hole H2. For example, the memory patterns 108 may include at least one of a charge blocking film, a data storage film, and a tunnel insulating film, and the data storage film may include a floating gate such as silicon, a charge trap material such as nitride, a phase change material, a nano-dot, and the like.”, see examiner markup).
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Regarding claim 10;
Park et al. further teaches in figure 2B that the spacer covers a sidewall of the contact plug (e.g. see examiner markup in claim 9 rejection).
Regarding claim 11;
Park et al. further teaches in figure 2B that the spacer allows the contact plug to be spaced apart from conductive layers and interlayer insulating layers, which are located above the at least one conductive layer, among the plurality of conductive layers and the plurality of interlayer insulating layers (e.g. see examiner markup in claim 9 rejection).
Regarding claim 12;
Park et al. further teaches in figure 2B that the contact plug is in contact with a top surface of the at least one conductive layer (e.g. Detailed description [0049] “The memory pattern 108, the channel pattern 109, and the gap fill film 110 formed in the first channel hole H1 and the second channel hole H2 may be defined as a channel plug.”; see examiner markup).
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Regarding claim 13;
Park et al. further teaches in figure 2B that the contact plug includes a protrusion portion protruding in the second direction (e.g. see examiner markup).
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Regarding claim 14;
Park et al. further teaches in figure 2B that a sidewall of the contact plug includes an uneven surface (e.g. see examiner markup in claim 13 rejection).
Regarding claim 15;
Park et al. further teaches in figure 2B that a width of the contact plug at a first position is less than a width of the contact plug at a second position below the first position (e.g. see examiner markup in claim 13 rejection).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Gwon et al. (US20210066341A1) teaches a memory device with a stacked structure with a plurality of sub-stack structures, openings, contact plugs, and alternating conductive and interlayer insulating layers.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM ROBERT MANN whose telephone number is (571)270-0210. The examiner can normally be reached Monday thru Thursday 0800-1800 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM ROBERT MANN/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights