DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgement is made to a claim of foreign priority to Korean application filed on February 21st, 2023. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) filed on January 16th, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is being considered by the examiner.
Election/Restrictions
Applicant's election with traverse of Group I (Claims 1-10) in the reply filed on June 3rd, 2026 is acknowledged. The traversal is on the ground(s) that product groups I-III share a clear genus-species relationship and are not mutually exclusive. Examiner concedes that each product is a “semiconductor packaging”, but maintains that each contains structural elements which meaningfully make each distinct from one another (e.g. the specification of a type/form of vertical connection structure and/or inclusion of additional elements not common to all groups). Further, the incomplete burden statement for Group III in the restriction/election requirement dated April 8th, 2026 is meant to be “Group III requires searching for a Semiconductor packaging which contain a redistribution structure on and electrically connected to conductive posts”.
The requirement is still deemed proper and is therefore made FINAL, and all non-elected claims (i.e. claims 11-20) are withdrawn from consideration at this time.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4, and 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sharan et al. (US11031288B2).
Regarding claim 1;
Sharan et al. teaches A semiconductor package (e.g. Fig. 8 ref 802; Detailed Description “Fig. 8 … a 3-D stacked F2B package 802…”), comprising: a package substrate (e.g. Fig. 8 ref 804); an upper chip on the package substrate (e.g. Fig. 8 ref 808; Detailed Description “…top die 808.”); a passive element chip (e.g. Fig. 8 ref 822; Detailed Description “A redistribution layer 822 may be formed on the back side of the die…”) between the upper chip and the package substrate; and a lower chip between the passive element chip and the package substrate (e.g. Fig. 8 ref 806; Detailed Description “The bottom die is also coupled to a substrate 804…”), wherein: the passive element chip includes: a through electrode connected to the lower chip (e.g. Fig. 8 ref 820); and a plurality of passive elements on the through electrode (e.g. Fig. 8 ref 810, 812, 826), and an upper surface of the passive element chip is in contact with a lower surface of the upper chip.
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Regarding claim 4;
Sharan et al. further teaches a semiconductor package wherein the passive element includes an integrated stacked capacitor (e.g. Fig. 8 ref 812; Detailed Description “…3D MIM capacitors 812 integrated in the 3D-stacked system using a face-to-back stacking.”).
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Regarding claim 5;
Sharan et al. in figure 8 further teaches a semiconductor package wherein: a width of the passive element chip in a horizontal direction is the same as a width of the upper chip in the horizontal direction, and a side surface of the passive element chip is aligned with a side surface of the upper chip (e.g. Fig. 8, see examiner’s markup).
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Sharan et al. (US11031288B2) in view of Zhang et al. (US11557479B2) for the following reasons:
Regarding claim 2;
Sharan et al. is silent to a semiconductor package wherein a widest surface of the lower chip is wider than the widest surface of the passive element chip as claimed.
However, Zhang et al. teaches semiconductor package in figure 4 where the passive element chip’s widest area (e.g. 104-2, see examiner markup) is less than the widest area of the packages lower chip (e.g. ref 104-1).
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At the effective time of filing, it would have been obvious to someone having ordinary
skill in the art to form the semiconductor package taught in Sharan et al. with a narrower passive element chip as taught in Zhang et al. because the reduced profile of the passive element area improves the systems noise reduction at higher frequency due to limiting of the capacitor size in the passive element layer.
Regarding claim 3;
Sharan et al. is silent to a semiconductor package further comprising a chip connection terminal on a lower surface of the passive element chip, wherein the chip connection terminal as claimed.
However, Zhang et al. further teaches in figure 4 a chip connection terminal on the lower surface of the passive element chip (ref 196) wherein the chip connection terminal connects the through electrode to the lower chip (see examiner markup).
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At the effective time of filing, it would have been obvious to someone having ordinary
skill in the art to incorporate the chip connection terminal taught in Zhang et al. into the semiconductor package taught in Sharan et al. because the connection terminal provides an area of low contact resistance and ohmic character to couple the passive element layer to the lower chip.
Claims 6-8, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Sharan et al. (US11031288B2) in view of Xie et al. (US20220344249A1) for the following reasons:
Regarding claim 6;
Sharan et al. is silent to the inclusion of a bonding pad in the semiconductor package as claimed.
However, Xie et al. implicitly teaches a semiconductor package wherein: the passive element chip includes a first bonding pad at an upper surface thereof (e.g. Fig. 6 ref 412), the upper chip includes a second bonding pad at a lower surface thereof (e.g. Fig. 6 ref 422), and an upper surface of the first bonding pad is bonded to a lower surface of the second bonding pad (e.g. Fig. 6 ref 430).
At the effective time of filing, it would have been obvious to someone having ordinary
skill in the art to incorporate the bond pads taught in Xie et al. into the semiconductor package taught by Sharan et al. because they provide a dedicated region of electrical contact and signal transmission between the upper chip/die, passive element chip/die, and lower chip/die.
Regarding claim 7;
Xie et al. is silent to a first and second bonding pads being integrally made of the same material (under BRI “integrally made” is being interpreted as “formed from”) as claimed.
However, forming the first and second bonding pads using the same materials would allow for a stronger bond to be made between the two bonded chips, since bonds between two pieces of the same material can more easily form bonds (e.g. diffusion and contact bonding between metals) via coherent interface formation.
At the effective time of filing, it would have been obvious to one having ordinary skill in the art to form the first and second bonding pads from the same material for at least the previously described reason as it has been held to be within the general skill of worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design variation and choice. In re Leshin, 125 USPQ 416.
Regarding claim 8;
Xie et al. in figure 6 further teaches a semiconductor package wherein: the upper surface of the first bonding pad is on the same plane as the upper surface of the passive element chip, and the lower surface of the second bonding pad is on the same plane as the lower surface of the upper chip (e.g. see examiner markup).
Regarding claim 10;
Sharan et al. is silent to the inclusion of a logic element in upper chip of the semiconductor package as claimed.
However, Xie et al. teaches a semiconductor package wherein the upper chip includes a logic element (e.g. Fig. 6 ref 440; Detailed Description [0034] “…active circuitry 440 (e.g., a logic circuit).”).
At the effective time of filing, it would have been obvious to someone having ordinary
skill in the art to incorporate the internal logic element in the upper chip taught in Xie et al. into the semiconductor package taught by Sharan et al. because such a device would have improved logic functions due to the more effective capacitive decoupling effects (e.g. Description [0034]).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Sharan et al. (US11031288B2) in view of Xie et al. (US20220344249A1), further in view of Cui et al. (US20220045005A1) for the following reasons:
Regarding claim 9;
Sharan et al. and Xie et al. are both silent to a first and second bonding pad having the same width in a horizontal direction as claimed.
However, Cui et al. in figure 28 teaches a first bonding pad (ref 118) and a second bonding pad (ref 788) having equal lengths in a horizontal direction (e.g. see examiner markup) which bond the first semiconductor die (ref 1000) and second semiconductor die (ref 700) to one another.
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At the effective time of filing, it would have been obvious to someone having ordinary
skill in the art to form the bonding pads between the upper surface of the passive element chip and lower surface of the upper chip taught in Xie et al. to have equal widths in a horizontal direction as taught in Cui et al. in a semiconductor package taught in Sharan et al. since it was known in the art that doing so serves to reduce the contact resistance between the two pads via a reduction in the non-overlapping area of the two bond pads and a change in size of a component is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM ROBERT MANN whose telephone number is (571)270-0210. The examiner can normally be reached Monday thru Thursday 0800-1800 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM ROBERT MANN/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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