DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments in regard to claims 1 and 15 filed 07/31/2026 have been fully considered and are persuasive. However, a new rejection has been made in view of Jhan et al. (US 2023/0060454 A1).
Applicant’s arguments with respect to claims 14 and 26 have been fully considered, the previous 112(b) rejection has been withdrawn.
Examiner acknowledges the title of the invention has been changed and is clearly indicative of the invention to which the claims are directed. Therefore the specification objection has been withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-8, 10-11, 15-16, 19-20 and 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw (US 2024/0250027 A1; hereinafter “Liaw027”), in view of Liaw (US 2024/0170535 A; hereinafter “Liaw535”) and Jhan et al. (US 2023/0060454 A1; hereinafter “Jhan”).
In regard to claim 1, Liaw027 teaches a semiconductor structure (a wafer including a front-side interconnect structure and a back-side interconnect structure) (Fig. 1 and paragraph 24), comprising:
a semiconductor substrate (a layer containing a semiconductive layer 248a/248b and STI structure 251) having a top surface and a bottom surface (the semiconductive layer 248a/248b are shown with a top and bottom surface in Fig. 3E) (Fig. 3E and paragraph 35);
a first well region (the semiconductive layer 248a annotated as 1st in Fig. 3E below) and a second well region (the semiconductive layer 248a annotated as 2nd in Fig. 3E below) arranged in the semiconductor substrate and separated from each other (the semiconductive layers 248a annotated as 1st and 2nd are shown spaced apart in Fig. 3E), wherein top and bottom surfaces of the first and second well regions are aligned with the top and bottom surfaces of the semiconductor substrate (the semiconductive layer 248a/248b is shown to be aligned with its top and bottom surfaces in Fig. 3E);
a first gate-all-around (GAA) field-effect transistor device (the GAA formed over the semiconductive layer 248a annotated as 1st ) formed over the first well region (the transistors may be GAA FETs on the front-side surface 248f/248s of the semiconductive layer 248a/248b) (annotated Fig. 3E, Fig. 3H and paragraph 29), wherein the first GAA field-effect transistor device comprises:
a first gate structure (semiconductor sheets 210 wrapped around by the gate electrodes 220 on the semiconductive layer 248a annotated as 1st) (annotated Fig. 3E and paragraph 31); and
first epitaxial source/drain features (source/drain regions 218a/218b) disposed on opposite sides of the first gate structure (the source/drain regions 218a/218b are shown on the left and right sides of the semiconductor sheets 210 wrapping around by the gate electrodes 220 on the semiconductive layer 248a annotated as 1st in Fig. 3E); and
a second gate-all-around (GAA) field-effect transistor device (the GAA over the device formed over the semiconductive layer 248a annotated as 2nd) formed over the second well region (the transistors may be GAA FETs on the front-side surface 248f/248s of the semiconductive layer 248a/248b) (annotated Fig. 3E, Fig. 3H and paragraph 29), wherein the second GAA field-effect transistor device comprises:
a second gate structure (semiconductor sheets 210 wrapping around by the gate electrodes 220 on the semiconductive layer 248a annotated as 2nd) (annotated Fig. 3E and paragraph 31); and
second epitaxial source/drain features (source/drain regions 218a/218b) disposed on opposite sides of the second gate structure (the source/drain regions 218a/218b are shown on the left and right sides of the semiconductor sheets 210 wrapping around by the gate electrodes 220 on the semiconductive layer 248a annotated as 1st in Fig. 3E); and
wherein the second epitaxial source/drain features are electrically connected to a ground terminal (the source/drain regions 218a be electrically coupled to overlying power supply voltage line F-M1-Vss through a power supply voltage contact 244 and a conductive via 246) (Fig. 2A, Fig. 3E and paragraph 31).
However, Liaw027 doesn’t explicitly teach wherein the first gate structure is electrically connected to a power supply terminal, wherein all the first epitaxial source/drain features are electrically connected to the second gate structure through a single interconnect feature completely formed on a first dielectric layer covering the first and second gate structures.
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Liaw535 teaches a semiconductor structure (a wafer including a front-side interconnect structure and a back-side interconnect structure) (Fig. 1 and paragraph 24), wherein a first gate structure is electrically connected to a power supply terminal (a gate of PMOSFET2 is shown electrically connected to the VDD in the NOR logic circuit in Fig. 6D) (Fig. 6D and paragraphs 21 and 27).
It would’ve been obvious to one skilled in the art to combine the teachings of Liaw027 with the teachings of Liaw535 to have the first gate structure electrically connected to a power supply terminal, since this layout allows for the device to have increased functionality by allowing specific circuits such as a NOR circuit as described in Liaw535 (paragraph 27).
Jhan teaches a semiconductor structure (an IC device 10) (Fig. 1D and paragraph 11), wherein all first epitaxial source/drain features (source/drain contacts 120 to the right of gate structure 200H) are electrically connected to a second gate structure (gate structure 200B) through a single interconnect feature (interconnect structure 182) completely formed on a first dielectric layer (dielectric layers 181) covering the first and second gate structures (the dielectric layer 181 is shown on the gate structure 200H and gate structure 200B in Fig. 1D) (Fig. 1D and paragraph 90).
It would have been obvious to combine the teachings of Liaw027 with the teachings of Jhan to have all the first epitaxial source/drain features are electrically connected to the second gate structure through a single interconnect feature completely formed on a first dielectric layer covering the first and second gate structures as this allows the device to form electrical connections on the substrate 110, such as the GAA devices and source/drain contacts, as well as to IC devices external to the IC device 10 as taught by Jhan (paragraph 90).
In regard to claim 2, Liaw027 in view of Liaw535 teaches wherein the first epitaxial source/drain features are electrically connected to each other (the source/drain regions 218a/218b of the PMOSFET2 corresponding to the set (S) input are shown electrically connected in Liaw535 Fig. 6D).
In regard to claim 3, Liaw027 in view of Liaw535 teaches wherein the second epitaxial source/drain features are electrically connected to each other (the source/drain regions 218a/218b of the PMOSFET2 corresponding to the reset (R) input are shown electrically connected in Liaw535 Fig. 6D).
In regard to claim 4, Liaw027 wherein the first gate structure and the first epitaxial source/drain features and a first portion of a first dielectric layer (gate spacers 233) between the first gate structure and first epitaxial source/drain features form a first capacitor (the gate spacers 233 and the surrounding gate electrode layer 220 along with the source/drain regions 218a/218b on the semiconductive layer 248a annotated as 1st would form a capacitor as shown in Fig. 3E) (Fig. 3E and paragraph 52).
In regard to claim 5, Liaw027 teaches wherein the second gate structure and the second epitaxial source/drain features and a second portion of the first dielectric layer between the second gate structure and second epitaxial source/drain features form a second capacitor (the gate spacers 233 and the surrounding gate electrode layer 220 along with the source/drain regions 218a/218b on the semiconductive layer 248a annotated as 2nd would form a capacitor as shown in Fig. 3E).
In regard to claim 7, Liaw027 teaches a second dielectric layer (an ILD layer 262) covering the first and second GAA field-effect transistor devices (the ILD layer 262 is shown over the GAA transistors in annotated Fig. 3E);
a first front-side gate contact (gate vias 250) passing through the second dielectric layer and electrically connected to the first gate structure (Fig. 3C and paragraph 31); and
first front-side source/drain contacts (source/drain vias 242) passing through the second dielectric layer and electrically connected to the first epitaxial source/drain features (Fig. 3B and paragraph 31).
In regard to claim 8, Liaw027 teaches a second front-side gate contact passing through the second dielectric layer and electrically connected to the second gate structure (as gate vias 250 can be disposed over the gate electrodes as needed and therefore the gate vias 250 would be disposed and connected to the gate electrode layer 220 on the semiconductive layer 248a annotated as 2nd ) (paragraph 101); and
second front-side source/drain contacts passing through the second dielectric layer and electrically connected to the second epitaxial source/drain features (source/drain vias 242 can be disposed over source/drain regions 218a/218b as needed and therefore the source/drain vias 242 would be disposed and connected to the gate electrode layer 220 on the semiconductive layer 248a annotated as 2nd ) (paragraph 101).
In regard to claim 10, Liaw027 teaches wherein the first and second source/drain epitaxial features have a first conductivity type, and wherein the first and second well regions have a second conductivity type that is different from the first conductivity type (the semiconductive layer 248a/248b may be doped with a dopant having a different conductivity type than the source/drain region 218a formed subsequently overlying thereof, and the dopant can be either n-type or p-type doping species) (paragraph 35).
In regard to claim 11, Liaw027 wherein the semiconductor substrate has the first conductivity type (the semiconductive layer 248a of the semiconductor substrate can be p-type).
In regard to claim 15, Liaw027 teaches a semiconductor structure (a wafer including a front-side interconnect structure and a back-side interconnect structure) (Fig. 1 and paragraph 24), comprising:
a semiconductor substrate (a layer containing a semiconductive layer 248a/248b and STI structure 251) having a top surface and a bottom surface (the semiconductive layer 248a/248b are shown with a top and bottom surface in Fig. 3E) (Fig. 3E and paragraph 35);
a first well region (the semiconductive layer 248a annotated as 1st in Fig. 3E above) and a second well region (the semiconductive layer 248a annotated as 2nd in Fig. 3E above) arranged in the semiconductor substrate (the semiconductive layers 248a annotated as 1st and 2nd are shown spaced apart in Fig. 3E), wherein bottom surfaces of the first and second well regions are exposed from a bottom surface of the semiconductor substrate (the semiconductive layers 248a annotated as 1st and 2nd are shown forming a bottom surface in annotated Fig. 3E above);
a first gate-all-around (GAA) field-effect transistor device (the GAA formed over the semiconductive layer 248a annotated as 1st ) formed over the first well region (the transistors may be GAA FETs on the front-side surface 248f/248s of the semiconductive layer 248a/248b) (annotated Fig. 3E, Fig. 3H and paragraph 29), wherein the first GAA field-effect transistor device comprises:
a first fin structure protruding from the semiconductor substrate (the fin structure would be formed above the semiconductive layer 248a annotated as 1st as shown in annotated Fig. 3E), wherein the first fin structure comprises first channel layers and a first gate structure that is wrapped around the first channel layer (semiconductor sheets 210 are wrapped around by the gate electrodes 220 on the semiconductive layer 248a annotated as 1st) (annotated Fig. 3E and paragraph 31); and
first epitaxial source/drain features (source/drain regions 218a/218b) connected to opposite sides of the first channel layers (the source/drain regions 218a/218b are shown on the left and right sides of the semiconductor sheets 210 wrapping around by the gate electrodes 220 on the semiconductive layer 248a annotated as 1st in Fig. 3E);
a second gate-all-around (GAA) field-effect transistor device (the GAA over the device formed over the semiconductive layer 248a annotated as 2nd) formed over the second well region (the transistors may be GAA FETs on the front-side surface 248f/248s of the semiconductive layer 248a/248b) (annotated Fig. 3E, Fig. 3H and paragraph 29), wherein the second GAA field-effect transistor device comprises:
a second fin structure protruding from the semiconductor substrate (the fin structure would be formed above the semiconductive layer 248a annotated as 2nd as shown in annotated Fig. 3E), wherein the second fin structure comprises second channel layers and a second gate structure that is wrapped around the second channel layer (semiconductor sheets 210 are wrapped around by the gate electrodes 220 on the semiconductive layer 248a annotated as 2nd) (annotated Fig. 3E and paragraph 31); and second epitaxial source/drain features (source/drain regions 218a/218b) disposed on opposite sides of the second channel layers (the source/drain regions 218a/218b are shown on the left and right sides of the semiconductor sheets 210 wrapping around by the gate electrodes 220 on the semiconductive layer 248a annotated as 2nd in Fig. 3E); and
a first dielectric layer (an ILD layer 262) covering the first and second gate structures devices (the ILD layer 262 is shown over the GAA transistors in annotated Fig. 3E); and wherein the first gate structure, the first epitaxial source/drain features, and a first portion of the first dielectric layer between the first gate structure and first epitaxial source/drain features form a first capacitor (the gate spacers 233 and the surrounding gate electrode layer 220 along with the source/drain regions 218a/218b on the semiconductive layer 248a annotated as 1st would form a capacitor as shown in Fig. 3E).
However, Liaw027 doesn’t explicitly teach wherein all the first epitaxial source/drain features are electrically connected to the second gate structure through a single interconnect feature completely formed on the first dielectric layer
Liaw535 teaches a semiconductor structure (a wafer including a front-side interconnect structure and a back-side interconnect structure) (Fig. 1 and paragraph 24), wherein a first epitaxial source/drain features are electrically connected to a second gate structure (the source/drain regions 218a/218b of the PMOSFET2 corresponding to the set (S) input is shown electrically connected to a gate electrodes 220 of PMOSFET2 corresponding to the reset (R) input in Fig. 6D) (Fig. 6D and paragraphs 27-30).
It would’ve been obvious to one skilled in the art to combine the teachings of Liaw027 with the teachings of Liaw535 to have the first epitaxial source/drain features are electrically connected to the second gate structure since this layout allows for the device to have increased functionality by allowing specific circuits such as a NOR circuit as described in Liaw535 (paragraph 27).
Jhan teaches a semiconductor structure (an IC device 10) (Fig. 1D and paragraph 11), wherein all first epitaxial source/drain features (source/drain contacts 120 to the right of gate structure 200H) are electrically connected to a second gate structure (gate structure 200B) through a single interconnect feature (interconnect structure 182) completely formed on a first dielectric layer (dielectric layers 181) covering the first and second gate structures (the dielectric layer 181 is shown on the gate structure 200H and gate structure 200B in Fig. 1D) (Fig. 1D and paragraph 90).
It would have been obvious to combine the teachings of Liaw027 with the teachings of Jhan to have all the first epitaxial source/drain features are electrically connected to the second gate structure through a single interconnect feature completely formed on a first dielectric layer covering the first and second gate structures as this allows the device to form electrical connections on the substrate 110, such as the GAA devices and source/drain contacts, as well as to IC devices external to the IC device 10 as taught by Jhan (paragraph 90).
In regard to claim 16, Liaw027 teaches wherein the first fin structure and the second fin structure are separated from each other (the fin structures formed above the semiconductive layer 248a annotated as 1st and 2nd are shown separated in annotated Fig. 3E).
In regard to claim 17, Liaw027 in view of Liaw535 and Jhan teaches wherein the second epitaxial source/drain features are electrically connected to each other (the source/drain regions 218a/218b of the PMOSFET2 corresponding to the reset (R) input are shown electrically connected in Liaw535 Fig. 6D), and wherein the second gate structure and the second epitaxial source/drain features and a second portion of the first dielectric layer between the second gate structure and second epitaxial source/drain features form a second capacitor (the gate spacers 233 and the surrounding gate electrode layer 220 along with the source/drain regions 218a/218b on the semiconductive layer 248a annotated as 2nd would form a capacitor as shown in Fig. 3E).
In regard to claim 19, Liaw027 in view of Liaw535 and Jhan teaches wherein a first gate structure is electrically connected to a power supply terminal (a gate of PMOSFET2 is shown electrically connected to the VDD in the NOR logic circuit in Fig. 6D) (Fig. 6D and paragraphs 21 and 27), and wherein the second epitaxial source/drain features are electrically connected to a ground terminal (the source/drain regions 218a are electrically coupled to overlying power supply voltage line F-M1-Vss through a power supply voltage contact 244 and a conductive via 246) (Fig. 2A, Fig. 3E and paragraph 31).
In regard to claim 20, Liaw027 teaches a second dielectric layer (an ILD layer 262) covering the first and second GAA field-effect transistor devices (the ILD layer 262 is shown over the GAA transistors in annotated Fig. 3E);
a first front-side gate contact (gate vias 250) passing through the second dielectric layer and electrically connected to the first gate structure of the first GAA field-effect transistor device (Fig. 3C and paragraph 31); and
first front-side source/drain contacts (source/drain vias 242) passing through the second dielectric layer and electrically connected to the first epitaxial source/drain features of the first GAA field-effect transistor device (Fig. 3B and paragraph 31);
a second front-side gate contact passing through the second dielectric layer and electrically connected to the second gate structure of the second GAA field-effect transistor device (as gate vias 250 can be disposed over the gate electrodes as needed and therefore the gate vias 250 would be disposed and connected to the gate electrode layer 220 on the semiconductive layer 248a annotated as 2nd ) (paragraph 101); and
second front-side source/drain contacts passing through the second dielectric layer and electrically connected to the second epitaxial source/drain features of the second GAA field-effect transistor device (source/drain vias 242 can be disposed over source/drain regions 218a/218b as needed and therefore the source/drain vias 242 would be disposed and connected to the gate electrode layer 220 on the semiconductive layer 248a annotated as 2nd ) (paragraph 101).
In regard to claim 22, Liaw027 teaches wherein the first and second source/drain epitaxial features have a first conductivity type, and wherein the first and second well regions have a second conductivity type that is different from the first conductivity type (the semiconductive layer 248a/248b may be doped with a dopant having a different conductivity type than the source/drain region 218a formed subsequently overlying thereof, and the dopant can be either n-type or p-type doping species) (paragraph 35).
In regard to claim 23, wherein the semiconductor substrate has the first conductivity type (the semiconductive layer 248a of the semiconductor substrate can be p-type).
Claims 6 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw027 in view of Liaw535 and Jhan as applied to claim 5 and 17, and further in view of Chang et al. (US 2023/0343838 A1; hereinafter “Chang”).
In regard to claim 6, Liaw027 in view of Liaw535 and Jhan doesn’t explicitly teach wherein the first capacitor and the second capacitor are connected in series.
Chang teaches a semiconductor structure (a semiconductor device) (Fig. 1C and paragraph 4), wherein a first capacitor and a second capacitor are connected in series (first and second capacitors annotated as C1 and C2 in Fig. 1C are shown connected in series).
It would’ve been obvious to one skilled in the art to combine the teachings of Liaw027 in view of Liaw535 and Jhan with the teachings of Chang to have the first capacitor and the second capacitor are connected in series since this allows for increased signal transfer within the device and functionality of the device as taught by Chang (paragraphs 38-39).
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In regard to claim 18, Liaw027 in view of Liaw535 and Jhan doesn’t explicitly teach wherein the first capacitor and the second capacitor are connected in series.
Chang teaches a semiconductor structure (a semiconductor device) (Fig. 1C and paragraph 4), wherein a first capacitor and a second capacitor are connected in series (first and second capacitors annotated as C1 and C2 in Fig. 1C are shown connected in series).
It would’ve been obvious to one skilled in the art to combine the teachings of Liaw027 in view of Liaw535 and Jhan with the teachings of Chang to have the first capacitor and the second capacitor are connected in series since this allows for increased signal transfer within the device and functionality of the device as taught by Chang (paragraphs 38-39).
Claims 9, 14 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw027 as taught in Fig. 3E in view of Liaw535 and Jhan as applied to claims 1 and 15, and further in view of Liaw027 as taught in Fig. 4B.
In regard to claim 9, Liaw027 as taught in Fig. 3E and further in view of Liaw535 and Jhan don’t explicitly teach the semiconductor substrate is electrically floating.
Liaw027 as taught in Fig. 4B, teaches the semiconductor substrate is electrically floating (the semiconductive layer 248a/248b and STI structure 251 are shown electrically floating due to a dielectric layer 335 formed on the back-side contact 252 and a back-side dielectric layer 331 formed under the semiconductive layer 248a/248b and STI structure 251) (Fig. 4B, Fig. 4C, Fig. 4H, 4K and paragraphs 42 and 57-58).
It would have been obvious to one skilled in the art to combine the teachings of Liaw027 as taught in Fig. 3E and further in view of Liaw535 with the teachings of Liaw027 as taught in Fig. 4B to have the semiconductor substrate electrically floating since this layout allows for the use of dielectric materials which is known to prevent unwanted shorts and connections within the device, therefore, improving device functionality (paragraph 22-23).
In regard to claim 14, Liaw027 in view of Liaw535 and Jhan teaches the third epitaxial source/drain features of the third GAA field-effect transistor device is not used as the first epitaxial source/drain features or the second epitaxial source/drain features (as shown in 2B and annotated Fig. 3H the source/drain regions 218a/218b mapped for the first epitaxial source/drain features are different from those used for the GAA over the device formed over the semiconductive layer 248a annotated as 3rd).
In regard to claim 21, Liaw027 as taught in Fig. 3E and further in view of Liaw535 and Jhan don’t explicitly teach the semiconductor substrate is electrically floating.
Liaw027 as taught in Fig. 4B, teaches the semiconductor substrate is electrically floating (the semiconductive layer 248a/248b and STI structure 251 are shown electrically floating due to a dielectric layer 335 formed on the back-side contact 252 and a back-side dielectric layer 331 formed under the semiconductive layer 248a/248b and STI structure 251) (Fig. 4B, Fig. 4C, Fig. 4H, 4K and paragraphs 42 and 57-58).
It would have been obvious to one skilled in the art to combine the teachings of Liaw027 as taught in Fig. 3E and further in view of Liaw535 with the teachings of Liaw027 as taught in Fig. 4B to have the semiconductor substrate electrically floating since this layout allows for the use of dielectric materials which is known to prevent unwanted shorts and connections within the device, therefore, improving device functionality (paragraph 22-23).
Claims 12-13, 24-26 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw027 in view of Liaw535 and Jhan as applied to claim 12, and further in view of Khaderbad et al. (US 2023/0062940 A1; hereinafter “Khaderbad”)
In regard to claim 12, Liaw027 teaches a third well region (the semiconductive layer 248b annotated as 3rd in Fig. 3H below) arranged in the semiconductor substrate (Fig. 3E and paragraph 35), wherein top and bottom surfaces of the third well region are aligned with the top and bottom surfaces of the substrate (the semiconductive layer 248a/248b is shown to be aligned with its top and bottom surfaces in Fig. 3H);
a third gate-all-around (GAA) field-effect transistor device (the GAA over the device formed over the semiconductive layer 248b annotated as 3rd) formed over the third well region (the transistors may be GAA FETs on the front-side surface 248f/248s of the semiconductive layer 248a/248b) (annotated Fig. 3E, Fig. 3H and paragraph 29), wherein the third GAA field-effect transistor device comprises:
a third gate structure (semiconductor sheets 210 wrapped around the gate electrodes 220 on the semiconductive layer 248a annotated as 3rd) (annotated Fig. 3H and paragraph 31); and third epitaxial source/drain features (source/drain regions 218a/218b) disposed on opposite sides of the third gate structure (the source/drain regions 218a/218b are shown on the left and right sides of the semiconductor sheets 210 wrapping around by the gate electrodes 220 on the semiconductive layer 248a annotated as 3rd in annotated Fig. 3H).
However, Liaw027 in view of Liaw535 and Jhan doesn’t explicitly teach a third back-side gate contact passing through the semiconductor substrate and electrically connected to the third gate structure.
Khaderbad teaches a semiconductor structure (semiconductor device 200) (Fig. 8 and paragraph 20), wherein a third back-side gate contact (gate electrodes 816 in the far right of the semiconductor device 200) passing through a semiconductor substrate (substrate 106 can be doped depending on design requirements) and electrically connected to the third gate structure (gate electrodes 816 between adjacent semiconductor layers 122 and gate electrodes 816 formed in substrate 106 are electrically coupled to each other) (Fig. 8 and paragraphs 21 and 42).
It would’ve been obvious to one skilled in the art to combine the teachings of Liaw027 in view of Liaw535 and Jhan with the teachings of Khaderbad to have a third back-side gate contact passing through the semiconductor substrate and electrically connected to the third gate structure since this layout allows for the manufacture of a more compact device due to increased circuit density as taught by Khaderbad (paragraphs 1 and 17-18).
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In regard to claim 13, Liaw027 teaches a third back-side source/drain contact (a contact 252) passing through the semiconductor substrate and electrically connected to one of the third epitaxial source/drain features (the contact 252 is shown connected to the source/drain regions 218a/218b on the semiconductive layer 248a annotated as 3rd in Fig. 3H) (annotated Fig. 3H and paragraph 34).
In regard to claim 24, Liaw027 teaches a third well region (the semiconductive layer 248b annotated as 3rd in Fig. 3H above) arranged in the semiconductor substrate (Fig. 3E and paragraph 35), wherein top and bottom surfaces of the third well region are aligned with the top and bottom surfaces of the substrate (the semiconductive layer 248a/248b is shown to be aligned with its top and bottom surfaces in Fig. 3H);
a third gate-all-around (GAA) field-effect transistor device (the GAA over the device formed over the semiconductive layer 248b annotated as 3rd) formed over the third well region (the transistors may be GAA FETs on the front-side surface 248f/248s of the semiconductive layer 248a/248b) (annotated Fig. 3E, Fig. 3H and paragraph 29), wherein the third GAA field-effect transistor device comprises:
a third fin structure protruding from the semiconductor substrate (the fin structure would be formed above the semiconductive layer 248a annotated as 3rd as shown in annotated Fig. 3H), wherein the third fin structure comprises third channel layers and a third gate structure that is wrapped around the third channel layer (semiconductor sheets 210 are wrapped around the gate electrodes 220 on the semiconductive layer 248a annotated as 3rd) (annotated Fig. 3H and paragraph 31); and
third epitaxial source/drain features (source/drain regions 218a/218b) disposed on opposite sides of the third channel layers (the source/drain regions 218a/218b are shown on the left and right sides of the semiconductor sheets 210 wrapping around by the gate electrodes 220 on the semiconductive layer 248a annotated as 3rd in annotated Fig. 3H).
However, Liaw027 in view of Liaw535 and Jhan doesn’t explicitly teach a third back-side gate contact passing through the semiconductor substrate and electrically connected to the third gate structure.
Khaderbad teaches a semiconductor structure (semiconductor device 200) (Fig. 8 and paragraph 20), wherein a third back-side gate contact (gate electrodes 816 in the far right of the semiconductor device 200) passing through a semiconductor substrate (substrate 106 can be doped depending on design requirements) and electrically connected to the third gate structure (Gate electrodes 816 between adjacent semiconductor layers 122 and gate electrodes 816 formed in substrate 106 are electrically coupled to each other) (Fig. 8 and paragraphs 21 and 42).
It would’ve been obvious to one skilled in the art to combine the teachings of Liaw027 in view of Liaw535 and Jhan with the teachings of Khaderbad to have a third back-side gate contact passing through the semiconductor substrate and electrically connected to the third gate structure since this layout allows for the manufacture of a more compact device due to increased circuit density as taught by Khaderbad (paragraphs 1 and 17-18).
In regard to claim 25, Liaw027 teaches a third back-side source/drain contact (a contact 252) passing through the semiconductor substrate and electrically connected to one of the third epitaxial source/drain features (the contact 252 is shown connected to the source/drain regions 218a/218b on the semiconductive layer 248a annotated as 3rd in Fig. 3H) (annotated Fig. 3H and paragraph 34).
In regard to claim 26, Liaw027 in view of Liaw535 and Jhan teaches the third epitaxial source/drain features of the third GAA field-effect transistor device are not used as the first, second source/drain feature (as shown in 2B and annotated Fig. 3H the source/drain regions 218a/218b mapped for the first epitaxial source/drain features are different from those used for the GAA over the device formed over the semiconductive layer 248a annotated as 3rd).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Tsao et al. (US 2023/0223276 A1).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEYON ALI-SIMAH PUNCHBEDDELL whose telephone number is (571)270-0078. The examiner can normally be reached Mon-Thur: 7:30AM-3:30 PM.
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/SEYON ALI-SIMAH PUNCHBEDDELL/ Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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