Prosecution Insights
Last updated: July 17, 2026
Application No. 18/413,290

DISTORTION CORRECTION FOR FAST SUPPLY VOLTAGE CHANGES IN POWER AMPLIFIER

Non-Final OA §103§112
Filed
Jan 16, 2024
Priority
Mar 15, 2023 — provisional 63/452,199
Examiner
BARTOL, LANCE TORBJORN
Art Unit
Tech Center
Assignee
Qorvo US Inc.
OA Round
1 (Non-Final)
78%
Grant Probability
Favorable
1-2
OA Rounds
9m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
39 granted / 50 resolved
+18.0% vs TC avg
Strong +30% interview lift
Without
With
+29.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
23 currently pending
Career history
82
Total Applications
across all art units

Statute-Specific Performance

§103
91.6%
+51.6% vs TC avg
§102
0.9%
-39.1% vs TC avg
§112
7.0%
-33.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 50 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification The abstract of the disclosure is objected to because it refers to the merits of the invention (see sentences 2 and 4-5). A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b). Applicant is reminded of the proper content of an abstract of the disclosure. A patent abstract is a concise statement of the technical disclosure of the patent and should include that which is new in the art to which the invention pertains. The abstract should not refer to purported merits or speculative applications of the invention and should not compare the invention with the prior art. If the patent is of a basic nature, the entire technical disclosure may be new in the art, and the abstract should be directed to the entire disclosure. If the patent is in the nature of an improvement in an old apparatus, process, product, or composition, the abstract should include the technical disclosure of the improvement. The abstract should also mention by way of example any preferred modifications or alternatives. Where applicable, the abstract should include the following: (1) if a machine or apparatus, its organization and operation; (2) if an article, its method of making; (3) if a chemical compound, its identity and use; (4) if a mixture, its ingredients; (5) if a process, the steps. Extensive mechanical and design details of an apparatus should not be included in the abstract. The abstract should be in narrative form and generally limited to a single paragraph within the range of 50 to 150 words in length. See MPEP § 608.01(b) for guidelines for the preparation of patent abstracts. The use of the term BLUETOOTH® (see Paragraph 27, line 4), which is a trade name or a mark used in commerce, has been noted in this application. The term should be accompanied by the generic terminology; furthermore the term should be capitalized wherever it appears or, where appropriate, include a proper symbol indicating use in commerce such as ™, SM , or ® following the term. Although the use of trade names and marks used in commerce (i.e., trademarks, service marks, certification marks, and collective marks) are permissible in patent applications, the proprietary nature of the marks should be respected and every effort made to prevent their use in any manner which might adversely affect their validity as commercial marks. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 9-10 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claims 9 and 10 recite that the bias circuit includes a diode varactor and a FET varactor, respectively. However, the instant specification and drawings only describe varactors as being part of the analog predistortion circuit, not the bias circuit. Therefore, the specification and drawings fail to disclose the bias circuit including a diode varactor or a FET varactor. Claims 9-10 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claims contain subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. Claims 9 and 10 recite that the bias circuit includes a diode varactor and a FET varactor, respectively. However, the instant specification and drawings do not describe implementing the bias circuit as either a diode or FET varactor, so therefore one of ordinary skill in the art would require undue experimentation to arrive at the claimed invention, particularly as the instant specification and drawings suggest implementing the bias circuit as a bipolar transistor circuit (see Fig. 10, element 622), so there is no reason, based on applicant’s disclosure to use either a diode or FET varactor to implement the claimed bias circuit. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 9-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 9 and 10 recite that the bias circuit includes a diode varactor and a FET varactor, respectively. However, as described in the instant specification (Paragraph 47) and drawings (Fig. 8), the analog predistortion circuit is the element that includes the diode varactor and the FET varactor. Therefore, it is unclear whether claims 9 and 10 refer to the bias circuit including a varactor, or the analog predistortion circuit including a varactor. Amending claims 9 and 10 to refer to “the APD circuit” instead of “the bias circuit” is sufficient to overcome this rejection, which is how the claims will be treated for examination purposes. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-8, 11-12, 14-17, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Khlat (Patent Publication Number US 2022/0231640 A1), hereafter referred to as Khlat, in view of Lyalin (Patent Publication Number US 2022/0231640 A1), hereafter referred to as Lyalin. Regarding claim 1, Khlat discloses: A power amplifier circuit (Khlat, Fig. 2, 60) comprising: an amplifier stage (Fig. 2, 42N(1)) configured to receive a transmit signal (Fig. 2, 36(N)) and amplify the transmit signal (Fig. 2, see connection between 36(N) and 42N(1)); a supply voltage input (Fig. 2, see connection between 42N(1) and Vcc1) configured to receive a signal containing information relating to a supply voltage being provided to the power amplifier circuit (Fig. 2, consider that Vcc1 is the supply voltage); an analog predistortion (APD) circuit (Fig. 2, 74) configured to predistort the transmit signal based at least in part on the signal (Paragraph 37, lines 1-9); but fails to disclose a bias circuit coupled to the amplifier stage and configured to provide a bias signal to the amplifier stage based at least in part on the signal. However, Lyalin teaches a bias circuit (Lyalin, Fig. 5, 120) coupled to the amplifier stage (Fig. 5, see connection between 120 and 104) and configured to provide a bias signal to the amplifier stage based at least in part on the signal (Fig. 5, see connection between V_supply and 120). Khlat and Lyalin are both considered to be analogous to the claimed invention because they are in the same field of improving power amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Khlat to incorporate the teachings of Lyalin to include the bias circuit of Lyalin in the circuit of Khlat, which would have the effect of providing a temperature-dependent bias signal to the power amplifier of Lyalin (Khlat, Paragraph 58, lines 1-5). Regarding claim 2, Khlat further discloses: wherein the APD circuit comprises an amplitude modulation (AM)-to-AM (AM-AM) predistortion circuit (Khlat, Fig. 2, 74). Regarding claim 3, Khlat fails to disclose: wherein the APD circuit comprises an amplitude modulation (AM)-to-phase modulation (PM) (AM-PM) predistortion circuit. However, Lyalin further teaches wherein the APD circuit comprises an amplitude modulation (AM)-to-phase modulation (PM) (AM-PM) predistortion circuit (Lyalin, Fig. 5, 110, consider also that Fig. 6 shows AM-PM modulation provided by APD circuit 110). Khlat and Lyalin are both considered to be analogous to the claimed invention because they are in the same field of improving power amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Khlat to incorporate the teachings of Lyalin to include the AM-PM predistortion circuit of Lyalin in the circuit of Khlat, which would have the effect of providing AM-PM predistortion for the circuit of Lyalin (Khlat, Fig. 6, see AM-PM modulation provided by APD circuit 110). Regarding claim 4, Khlat in view of Lyalin further discloses: further comprising a supply voltage correction circuit (Khlat, Fig. 2, 68) configured to receive the signal (Fig. 2, consider input of 68) and provide control signals to the bias circuit and the APD circuit based on the signal (Fig. 2, consider that output of 68 provides supply signal for APD circuit and that the bias circuit of Lyalin, Fig. 5 takes the supply voltage as an input). Regarding claim 5, Khlat further discloses: wherein the amplifier stage comprises an output amplifier stage (Khlat, Fig. 2, 38(N)). Regarding claim 6, Khlat further discloses: wherein the amplifier stage comprises a driver amplifier stage (Khlat, Fig. 2, 42N(1)). Regarding claim 7, Khlat further discloses: wherein the signal comprises the supply voltage (Khlat, Fig. 2, see Vcc1). Regarding claim 8, Khlat further discloses: wherein the signal comprises a predistorted version of the supply voltage (Khlat, Fig. 2, consider that Vcc1 is formed from predistortion circuit 74). Regarding claim 11, Khlat in view of Lyalin further discloses: wherein the APD circuit provides an adjustment signal to the bias circuit (Khlat, Fig. 2, consider that APD circuit 74 adjusts supply voltage, and that the supply voltage is provided to the bias circuit in Lyalin, Fig 5). Regarding claim 12, Khlat discloses: A mobile communication device (Khlat, Fig. 2, 60) comprising, a transmit circuit (Fig. 2, 60) comprising: a power management circuit (Fig. 2, 64) configured to: receive a signal (Fig. 2, see connection between 64 and 70) from a baseband processor (Fig. 2, 70) relating to a power level for a transmit signal (Fig. 2, consider power level of signal 14); and output a supply voltage signal (Fig. 2, consider output of envelope detector 72); a power amplifier circuit (Fig. 2, 60) comprising: an amplifier stage (Fig. 2, 42N(1)) configured to: receive the transmit signal (Fig. 2, 36(N)) and amplify the transmit signal (Fig. 2, see connection between 36(N) and 42N(1)); and receive the supply voltage signal (Fig. 2, see connection between Vcc1 and envelope detector 72 via 68); and an analog predistortion (APD) circuit (Fig. 2, 74) configured to predistort the transmit signal based at least in part on the supply voltage signal (Paragraph 37, lines 1-9); but fails to disclose a bias circuit coupled to the amplifier stage and configured to provide a bias signal to the amplifier stage based at least in part on the supply voltage signal. However, Lyalin teaches a bias circuit (Lyalin, Fig. 5, 120) coupled to the amplifier stage (Fig. 5, see connection between 120 and 104) and configured to provide a bias signal to the amplifier stage based at least in part on the supply voltage signal (Fig. 5, see connection between V_supply and 120). Khlat and Lyalin are both considered to be analogous to the claimed invention because they are in the same field of improving power amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Khlat to incorporate the teachings of Lyalin to include the bias circuit of Lyalin in the circuit of Khlat, which would have the effect of providing a temperature-dependent bias signal to the power amplifier of Lyalin (Khlat, Paragraph 58, lines 1-5). Regarding claim 14, Khlat further discloses: wherein the power management circuit comprises an envelope tracking (ET) circuit (Khlat, Fig. 2, 72). Regarding claim 15, Khlat in view of Lyalin further discloses: wherein the power amplifier circuit further comprises a voltage supply correction circuit (Khlat, Fig. 2, 68) coupled to the power management circuit (Fig. 2, see connection between 68 and 64) and configured to receive the supply voltage signal (Fig. 2, consider input of 68) and send control signals to the bias circuit and the APD circuit based on the supply voltage signal (Fig. 2, consider that output of 68 provides supply signal for APD circuit and that the bias circuit of Lyalin, Fig. 5 takes the supply voltage as an input). Regarding claim 16, Khlat further discloses: wherein the power management circuit is further configured to provide a predistorted supply voltage signal to the power amplifier circuit (Khlat, Fig. 2, consider that Vcc1 is formed from predistortion circuit 74). Regarding claim 17, Khlat further discloses: wherein the power amplifier circuit further comprises a voltage supply correction circuit (Khlat, Fig. 2, 68) coupled to the power management circuit (Fig. 2, see connection between 68 and 64) and configured to receive the predistorted supply voltage signal (Fig. 2, consider signal predistortion by 74). Regarding claim 19, Khlat discloses: A method of managing predistortion in a transmit circuit (Khlat, Fig. 2, 60), comprising: receiving, at an amplifier stage (Fig. 2, 42N(1)), a transmit signal (Fig. 2, 36(N)); amplifying the transmit signal (Fig. 2, see connection between 36(N) and 42N(1)); receiving a signal containing information relating to a supply voltage being provided to the amplifier stage (Fig. 2, consider that Vcc1 is the supply voltage); and predistorting the transmit signal with an analog predistortion (APD) circuit (Fig. 2, 74) based at least in part on the signal (Paragraph 37, lines 1-9), but fails to disclose providing a bias signal to the amplifier stage based at least in part on the signal. However, Lyalin teaches providing a bias signal to the amplifier stage based at least in part on the signal (Lyalin, Fig. 5, see connection between V_supply and 120). Khlat and Lyalin are both considered to be analogous to the claimed invention because they are in the same field of improving power amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Khlat to incorporate the teachings of Lyalin to include the bias circuit of Lyalin in the circuit of Khlat, which would have the effect of providing a temperature-dependent bias signal to the power amplifier of Lyalin (Khlat, Paragraph 58, lines 1-5). Regarding claim 20, Khlat further discloses: wherein amplifying the transmit signal comprises imposing a distortion on the transmit signal that is offset at least in part by the predistorting (Khlat, Paragraph 21, lines 1-6). Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Khlat in view of Lyalin as applied to claim 1 above, and further in view of Su et al. (Patent Publication Number US 2022/0416730 A1), hereafter referred to as Su. Regarding claim 9, Khlat and Lyalin fail to disclose: wherein the bias circuit comprises a diode varactor. However, Su teaches wherein the bias circuit comprises a diode varactor (Su, Fig. 1, D0). Khlat, Lyalin, and Su are all considered to be analogous to the claimed invention because they are in the same field of improving power amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Khlat to incorporate the teachings of Su to include the diode varactor of Su in the circuit of Khlat, which would have the effect of providing AM-PM compensation for the circuit of Khlat (Su, Paragraph 66, lines 13-20). Regarding claim 10, Khlat and Lyalin fail to disclose: wherein the bias circuit comprises a field effect transistor (FET) varactor. However, Su teaches wherein the bias circuit comprises a field effect transistor (FET) varactor (Su, Fig. 4, D1). Khlat, Lyalin, and Su are all considered to be analogous to the claimed invention because they are in the same field of improving power amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Khlat to incorporate the teachings of Su to include the FET varactor of Su in the circuit of Khlat, which would have the effect of providing AM-PM compensation for the circuit of Khlat (Su, Paragraph 96, lines 1-5). Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Khlat in view of Lyalin as applied to claim 12 above, and further in view of Peng et al. (Patent Publication Number US 2015/0236877 A1), hereafter referred to as Peng. Regarding claim 13, Khlat and Lyalin fail to disclose: wherein the power management circuit comprises an average power tracking (APT) circuit. However, Peng teaches wherein the power management circuit comprises an average power tracking (APT) circuit (Peng, Fig. 1, 110). Khlat, Lyalin, and Peng are all considered to be analogous to the claimed invention because they are in the same field of improving power amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Khlat to incorporate the teachings of Peng to include the average power tracking circuit of Peng in the circuit of Khlat, which would have the effect of improving efficiency and linearity of the circuit of Khlat (Peng, Paragraphs 7-8). Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Khlat in view of Lyalin as applied to claim 12 above, and further in view of Tsfaty et al. (Patent Publication Number US 2007/0223365 A1), hereafter referred to as Tsfaty. Regarding claim 18, Khlat and Lyalin fail to disclose: wherein the power management circuit is configured to receive the signal during a cyclic prefix (CP) time before a symbol in the transmit signal. However, Tsfaty teaches wherein the power management circuit is configured to receive the signal during a cyclic prefix (CP) time before a symbol in the transmit signal (Tsfaty, Paragraph 11, lines 6-11). Khlat, Lyalin, and Tsfaty are all considered to be analogous to the claimed invention because they are in the same field of improving power amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Khlat to incorporate the teachings of Tsfaty to include a cyclic prefix time in the signal of Khlat, which would have the effect of reducing signal interference (Tsfaty, Paragraph 11, lines 6-11). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Woo et al. (Patent Publication Number US 2009/0174473 A1) discloses (Fig. 1B) a predistortion and envelope tracking for a power amplifier circuit. Omid-Zohoor et al. (Patent Number US 10,796,629 B2) discloses (Fig. 3) a supply voltage correction circuit. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lance T Bartol whose telephone number is (703)756-1267. The examiner can normally be reached Monday - Thursday 6:30 a.m. - 4:00 p.m. CT, Alternating Fridays 6:30 - 3:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached at 571-272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LANCE TORBJORN BARTOL/Examiner, Art Unit 2843 /ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
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Prosecution Timeline

Jan 16, 2024
Application Filed
Jun 26, 2026
Non-Final Rejection mailed — §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
78%
Grant Probability
99%
With Interview (+29.7%)
3y 3m (~9m remaining)
Median Time to Grant
Low
PTA Risk
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