DETAILED ACTION
Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1-20 are currently pending in this application.
Priority
2. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
3. The information disclosure statement (IDS) submitted on 1/16/2024 was received. The submission is in compliance with the provisions of 37 CFR 1.97 and 37 CFR 1.98. Accordingly, the information disclosure statement has being considered by the examiner.
Drawings
4. The drawings submitted on 1/16/2024 are in compliance with 37 CFR § 1.81 and 37 CFR § 1.83 and have been accepted by the examiner.
Claim Rejections - 35 USC § 101 Non-Statutory
5. 35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
6. Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter.
Specifically, representative Claim 1 recites:
1. A glitch detector comprising:
a sensing unit configured to generate a glitch voltage and at least one reference voltage based on a power supply voltage;
a clock generator configured to receive a monitoring voltage corresponding to at least one from among the power supply voltage and the glitch voltage, and to output a clock signal comprising a plurality of pulse signals while a voltage change occurs in the monitoring voltage, wherein the plurality of pulse signals have a predetermined period; and
a comparison unit configured to operate based on each of the plurality of pulse signals, and to compare the glitch voltage with the at least one reference voltage and output a detection voltage based on determining that a glitch has occurred.
The claim limitations in the abstract idea have been highlighted in bold above; the remaining limitations are “additional elements.”
Similar limitations comprise the abstract ideas of Claims 11 and 16.
Under Step 1 of the analysis, claim 1 does belong to a statutory category, namely it is a device claim. Likewise, claim 11 is a process claim and claim 16 is also a device claim.
Under Step 2A, prong 1, claim 1 is found to include at least one judicial exception, that being a mathematical concept and/or mental process. This can be seen in the claim limitation of “a clock generator configured to receive a monitoring voltage corresponding to at least one from among the power supply voltage and the glitch voltage, and to output a clock signal comprising a plurality of pulse signals while a voltage change occurs in the monitoring voltage, wherein the plurality of pulse signals have a predetermined period; and a comparison unit configured to operate based on each of the plurality of pulse signals, and to compare the glitch voltage with the at least one reference voltage and output a detection voltage based on determining that a glitch has occurred.”, which is the judicial exception of a mental process and/or a mathematical concept because it is merely a data evaluation including calculations, and/or judgements capable of being performed mentally.
Similar limitations comprise the abstract ideas of Claims 11 and 16.
Step 2A, prong 2 of the eligibility analysis evaluates whether the claim as a whole integrates the recited judicial exception(s) into a practical application of the exception. This evaluation is performed by (a) identifying whether there are any additional elements recited in the claim beyond the judicial exception, and (b) evaluating those additional elements individually and in combination to determine whether the claim as a whole integrates the exception into a practical application.
In addition to the abstract ideas recited in claim 1, the claimed method recites additional elements including “a sensing unit configured to generate a glitch voltage and at least one reference voltage based on a power supply voltage;” (claims 1, 11, and 16) which are merely data gathering steps recited at a high level of generality and therefore merely amount to “insignificant extra-solution” activity(ies). See MPEP 2106.05(g) “Insignificant Extra-Solution Activity,”. The claim also recites a “processor” (claim16) however the “processor” is recited at a high level of generality, e.g. Spec. [0172] describing a variety of different types of “processors” that may be used, and merely amounts to the use of computer technology as a tool to apply the abstract idea (see MPEP 2106.05(f)) and/or the use of a “processor” to perform the predictions, that are otherwise abstract, is merely an attempt at limiting the abstract to a particular field of use (See MPEP 2106.05(h)).
The generic data gathering, processing, and output steps, and other elements, are recited so generically (no details whatsoever are provided) that it represents no more than mere instructions to apply the judicial exceptions on a computer. It can also be viewed as nothing more than an attempt to generally link the use of the judicial exceptions to the technological environment of a computer. Noting MPEP 2106.04(d)(I): “It is notable that mere physicality or tangibility of an additional element or elements is not a relevant consideration in Step 2A Prong Two. As the Supreme Court explained in Alice Corp., mere physical or tangible implementation of an exception does not guarantee eligibility. Alice Corp. Pty. Ltd. v. CLS Bank Int’l, 573 U.S. 208, 224, 110 USPQ2d 1976, 1983-84 (2014) ("The fact that a computer ‘necessarily exist[s] in the physical, rather than purely conceptual, realm,’ is beside the point")”.
Thus, under Step 2A, prong 2 of the analysis, even when viewed in combination, these additional elements do not integrate the recited judicial exception into a practical application and the claim is directed to the judicial exception. No specific practical application is associated with the claimed system. For instance, nothing is done after the glitch determination has been made.
Under Step 2B, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional elements, as described above with respect to Step 2A Prong 2, merely amount to a general purpose computer system that attempts to apply the abstract idea in a technological environment, limiting the abstract idea to a particular field of use, and/or merely insignificant extra-solution activity (claims 1, 11, and 16). Such insignificant extra-solution activity, e.g. data gathering and output, when re-evaluated under Step 2B is further found to be well-understood, routine, and conventional as evidenced by MPEP 2106.05(d)(II) (describing conventional activities that include transmitting and receiving data over a network, electronic recordkeeping, storing and retrieving information from memory, and electronically scanning or extracting data from a physical document).
Therefore, similarly the combination and arrangement of the above identified additional elements when analyzed under Step 2B also fails to necessitate a conclusion that claim 1, as well as claims 11 and 16, amount to significantly more than the abstract idea.
With regards to the dependent claims, claims 2-10, 12-15, and 17-20, merely further expand upon the algorithm/abstract idea and do not set forth further additional elements therefore these claims are found ineligible for the reasons described for independent claims 1,11, and 16.
See Supreme court decision in Alice Corporation Pty. Ltd. V. CLS Bank International, et al.
Claim Rejections - 35 USC § 102
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
8. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
9. Claims 1-7 an 9-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Heo et al. US Pat# 11,486,912.
With regards to claim 1, Heo et al. US Pat# 11,486,912 teaches a glitch detector comprising:
a sensing unit configured to generate a glitch voltage and at least one reference voltage based on a power supply voltage;(figure 1)
a clock generator configured to receive a monitoring voltage corresponding to at least one from among the power supply voltage and the glitch voltage, and to output a clock signal comprising a plurality of pulse signals while a voltage change occurs in the monitoring voltage, wherein the plurality of pulse signals have a predetermined period;(300; figure 1) and
a comparison unit configured to operate based on each of the plurality of pulse signals, and to compare the glitch voltage with the at least one reference voltage and output a detection voltage based on determining that a glitch has occurred. (400; figure 1)
With regards to claims 2, 12 and 17, Heo et al. US Pat# 11,486,912 teaches a pulse generator configured to generate a pulse voltage while the voltage change occurs; (col. 4, liens 45-50)and an oscillator/ clock generation circuit configured to generate the plurality of pulse signals having the predetermined period while the generated pulse voltage is maintained. (glitch to pulse generator interpreted as oscillator; Col. 6, lines 9-20)
With regards to claims 3, 13 and 18, Heo et al. US Pat# 11,486,912 teaches the oscillator is further configured to: receive external clock signals having the predetermined period from an external clock generator; and while the pulse voltage is maintained, output the external clock signals as the clock signal. (glitch to pulse generator interpreted as oscillator; Col. 6, lines 9-20)
With regards to claims 4, 15 and 20, Heo et al. US Pat# 11,486,912 teaches the comparison unit comprises: a first comparator configured to determine that an up-glitch has occurred based on the glitch voltage being greater than a first reference voltage from among the at least one reference voltage, and to output a first detection voltage; and a second comparator configured to determine that a down-glitch has occurred based on the glitch voltage being less than a second reference voltage from among the at least one reference voltage, and to output a second detection voltage, wherein the second reference voltage is lower than the first reference voltage. (Col. 10, lines 25-37)
With regards to claim 5, Heo et al. US Pat# 11,486,912 teaches the sensing unit comprises: a first circuit configured to generate the glitch voltage based on the power supply voltage; and a second circuit configured to generate the at least one reference voltage based on the power supply voltage. (Col. 4, lines 14-44)
With regards to claim 6, Heo et al. US Pat# 11,486,912 teaches the first circuit comprises: a first resistor connected in parallel with a first capacitor between a first node and a power supply voltage node corresponding to the power supply voltage, wherein the glitch voltage is output from the first node; and a second resistor connected in parallel with a second capacitor between the first node and a ground node. (Col. 19, lines 40-45)
With regards to claim 7, Heo et al. US Pat# 11,486,912 teaches the second circuit comprises a third resistor and a fourth resistor connected in series between the power supply voltage node and the ground node, and wherein the sensing unit is further configured to generate the first reference voltage by applying a first low pass filter to a signal output from a second node connected to the third resistor and the fourth resistor. (Col. 20, lines 35-40)
With regards to claim 9, Heo et al. US Pat# 11,486,912 teaches a the pulse generator comprises: a first P-type metal oxide semiconductor (PMOS) transistor connected to a first clock node from which a first sensing voltage is output based on the voltage change of the monitoring voltage; a first N-type metal oxide semiconductor (NMOS) transistor connected between the first clock node and a ground node; a second NMOS transistor connected between a second clock node and the ground node wherein a gate electrode of the second NMOS transistor is connected to the second clock node; a first monitoring resistor connected between the second clock node and a gate electrode of the first NMOS transistor; a second monitoring resistor connected to a gate electrode of the first PMOS transistor; a first monitoring capacitor connected between a monitoring voltage node corresponding to the monitoring voltage and the gate electrode of the first NMOS transistor; and a second monitoring capacitor connected between the monitoring voltage node and the gate electrode of the first PMOS transistor. (Col. 7-8, lines 59-69 and 1-24)
With regards to claim 10, Heo et al. US Pat# 11,486,912 teaches the pulse generator is configured to activate the second NMOS transistor and deactivate the first PMOS transistor in response to the voltage change occurring in the monitoring voltage. (Col. 9, lines 55-65)
With regards to claim 11, Heo et al. US Pat# 11,486,912 teaches a glitch detection method comprising:
generating, using a sensing unit, a glitch voltage and at least one reference voltage based on a power supply voltage; (figure 1)
outputting, using a clock generator, a clock signal comprising a plurality of pulse signals while a voltage change occurs in a monitoring voltage corresponding to at least one from among the power supply voltage or the glitch voltage, wherein the plurality of pulse signals have a predetermined period; (300; figure 1)
comparing, suing a comparison unit, the glitch voltage with the at least one reference voltage based on each of the plurality of pulse signals; (400; figure 1)and
outputting a detection voltage based on determining that a glitch has occurred in the power supply voltage, based on a result of the comparison. (Col. 5, lines 21-25)
With regards to claim 14 and 19, Heo et al. US Pat# 11,486,912 teaches: a first P-type metal oxide semiconductor (PMOS) transistor connected between a first clock node, from which the pulse voltage is output, and a power supply voltage node corresponding to the power supply voltage; and a first N-type metal oxide semiconductor (NMOS) transistor connected between the first clock node and a ground node, and wherein the generating the pulse voltage comprises activating the first NMOS transistor and deactivating the first PMOS transistor in response to the voltage change. (Col 9, lines 50-67)
With regards to claim 16, Heo et al. US Pat# 11,486,912 teaches security device comprising:
a security memory configured to store secure data; (Col. 15, lines 64-65)
a security processor configured to process the secure data and reset based on a reset signal; (Col. 15, lines 65-66)
a glitch detector configured to generate at least one detection voltage in response to a glitch occurring in a power supply voltage; (figure 1) and
a reset signal generator configured to generate the reset signal based on the at least one detection voltage,(1400; Col. 15, lines 65-67)wherein the glitch detector comprises:
a sensing unit configured to generate a glitch voltage and at least one reference voltage based on the power supply voltage; ( figure 1)
a clock generator configured to receive a monitoring voltage corresponding to at least one from among the power supply voltage and the glitch voltage, and to output a clock signal comprising a plurality of pulse signals while a voltage change occurs in the monitoring voltage, wherein the plurality of pulse signals have a predetermined period; (figure 1)and
a comparison unit configured to operate based on each of the plurality of pulse signals and to compare the glitch voltage with the at least one reference voltage and output a detection voltage based on determining that the glitch has occurred. (400; figure 1)
Claim Rejections - 35 USC § 103
10. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
11. Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Heo et al. US Pat# 11,486,912
Heo et al. US Pat# 11,486,912 discloses the claimed invention except for the fifth and sixth resistors. It would have been obvious to one having ordinary skill. in the art at the time the invention was made to include the additional resistors, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Conclusion
12. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Sharma et al. US 2023/0049371 teaches a reference less glitch detection circuitry with autocalibration.
13. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADITYA S BHAT whose telephone number is (571)272-2270. The examiner can normally be reached on Monday-Friday 8 am-6pm.
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15. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Shelby Turner can be reached on 571-272-6334. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ADITYA S BHAT/Primary Examiner, Art Unit 2857 June 8, 2026
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