DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1 and 4 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 19 of U.S. Patent No. 11,450,752 hereinafter “752 Patent”. Although the claims at issue are not identical, they are not patentably distinct from each other because...
Current Application
1. A semiconductor device comprising: a chip which has a main surface; a diode region which is arranged in the main surface; trench structures which are formed in the main surface at an interval in the diode region, the trench structures each having an electrode structure that includes an upper electrode and a lower electrode which are embedded in a trench across an insulator in an up/down direction; and a diode which has a pn-junction portion that is formed in a surface layer portion of the main surface at a region between the trench structures.
752 Patent
1. A semiconductor device comprising: a substrate which has a main surface; a trench gate structure which has a gate trench formed in the main surface, a gate insulation layer formed on an inner wall of the gate trench and an embedded electrode embedded in the gate trench across the gate insulation layer; and a temperature-sensitive diode structure which has a trench formed in the main surface at an interval from the gate trench, a polysilicon layer embedded in the trench, a p-type anode region formed in the polysilicon layer, and an n-type cathode region formed in the polysilicon layer; wherein the trench of the temperature-sensitive diode structure has a depth equal to or more than a depth of the gate trench of the trench gate structure.
19. The semiconductor device according to Claim 1, wherein the embedded electrode has an insulated separation-type electrode structure which includes a bottom-side electrode embedded in a bottom wall side of the gate trench across the gate insulation layer, an opening-side electrode embedded in an opening side of the gate trench across the gate insulation layer, and an intermediate insulation layer interposed between the bottom-side electrode and the opening-side electrode.
Claim 2 is anticipated by claims 1 and 4 of the 752 Patent.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5 and 7-9 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Okuda et al. (US 2018/0226480) hereinafter “Okuda”.
Regarding claim 1, Fig. 2 of Okuda teaches a semiconductor device comprising: a chip (Paragraph 0038) which has a main surface; a diode region (Item 6) which is arranged in the main surface; trench structures which are formed in the main surface at an interval in the diode region, the trench structures each having an electrode structure that includes an upper electrode (Item 32) and a lower electrode (Item 30) which are embedded in a trench across an insulator (Combination of Items 31 and 29) in an up/down direction; and a diode which has a pn-junction portion (Combination of Items 45, 46 and 47) that is formed in a surface layer portion of the main surface at a region between the trench structures.
Regarding claim 2, Fig. 2 of Okuda further teaches a first conductive type (P-type) body region (Item 45) which is formed in the surface layer portion of the main surface in the diode region (Item 6); wherein the trench structures are formed in the main surface so as to penetrate through the body region, and the diode includes a first conductive type first polarity region (Combination of Items 45 and 47) which is formed in the body region and a second conductive type (N-type) second polarity region (Item 46) which is formed in the body region so as to form the pn-junction portion with the first polarity region (Combination of Items 45 and 47).
Regarding claim 3, Fig. 2 of Okuda further teaches where the first polarity region (Combination of Items 45 and 47) includes a high concentration region (Item 47) which has an impurity concentration higher than that of the body region and a low concentration region (Item 45) which has an impurity concentration lower than that of the high concentration region (Item 47), and the second polarity region (Item 46) forms the pn-junction portion with the low concentration region (Item 45) of the first polarity region (Combination of Items 45 and 47).
Regarding claim 4, Fig. 2 of Okuda further teaches where the low concentration region (Item 45) is constituted of a part of the body region (Item 45).
Regarding claim 5, Fig. 2 of Okuda further teaches where the upper electrodes (Item 32) of the trench structures are embedded on the main surface side with respect to a bottom portion of the body region (Item 45), and the lower electrodes (Item 30) of the trench structures are embedded on the bottom wall side of the trench with respect to the bottom portion of the body region (Item 45).
Regarding claim 7, Fig. 2 of Okuda further teaches where the insulator (Combination of Items 29 and 31) includes an upper insulating film (Item 31) which covers an upper wall surface of the trench with a first thickness and a lower insulating film (Item 29) which covers a lower wall surface of the trench with a second thickness exceeding the first thickness, the upper electrode (Item 32) is embedded on the upper wall surface side of the trench across the upper insulating film (Item 31), and the lower electrode (Item 30) is embedded on the lower wall surface side of the trench across the lower insulating film (Item 29).
Regarding claim 8, Fig. 4 of Okuda further teaches a separation structure (Item 61) which is formed in the main surface so as to electrically separate the diode region (Item 6) from another region (Item 7).
Regarding claim 9, Fig. 4 of Okuda further teaches where the separation structure (Item 61) includes a separation electrode (Item 66) which is embedded in a separation trench across a separation insulator (Item 65).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Okuda et al. (US 2018/0226480) hereinafter “Okuda” in view of Katou et al. (US 2013/0256783) hereinafter “Katou”.
Regarding claim 6, Okuda teaches all of the elements of the claimed invention as stated above except where the first polarity region is fixed at the same potential as one of or both of the upper electrode and the lower electrode of the trench structures.
Katou teaches where a gate electrode buried in a trench has the same potential as a cathode or anode of a temperature sensitive diode (Paragraph 0137).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the first polarity region be fixed at the same potential as one of or both of the upper electrode and the lower electrode of the trench structures because this prevents the characteristics of the diode from varying and improves the performance of the semiconductor device (Katou Paragraph 0217).
Claims 10-12, 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Okuda et al. (US 2018/0226480) hereinafter “Okuda” in view of Williams et al. (US 6,046,470) hereinafter “Williams”.
Regarding claim 10, Okuda teaches all of the elements of the claimed invention as stated above except where the diode region is a temperature detecting region, and the diode is a temperature sensitive diode.
Fig. 6 of Williams teaches a structure similar to Okuda, where a P+ region (Item 114) is surrounded by two N+ regions (Item 110) in the cross section, all of which are buried in a P well region (Item 116), all of that being over an N-epi region (Item 106), with gate trench structures (Item 105) surrounding the p-well structures in the cross section, where the diode formed by the elements recited above form a temperature detection diode (Column 5, Lines 54-56).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the diode region be a temperature detecting region and the diode be a temperature sensitive diode because the structure taught by Okuda having a pn junction diode in a p-well is known to act as a temperature detection diode (Williams Column 5, Lines 54-56).
Regarding claim 11, Okuda teaches all of the elements of the claimed invention as stated above except where the temperature-sensitive diode has temperature characteristics in which a forward direction voltage linearly changes in response to a change in temperature.
Williams further teaches where the temperature-sensitive diode has temperature characteristics in which a forward direction voltage linearly changes in response to a change in temperature (Column 2, Lines 65-67).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the temperature-sensitive diode has temperature characteristics in which a forward direction voltage linearly changes in response to a change in temperature because this relationship is known to be characteristic of a temperature detection diode (Williams Column 2, Lines 65-67).
Regarding claim 12, the combination of Okuda and Williams teaches all of the elements of the claimed invention as stated above.
Fig. 2 of Okuda does not teach where a device region which is arranged in the main surface; and a functional device which is formed in the device region; wherein the temperature detecting region is arranged so as to be adjacent to the device region, and the temperature-sensitive diode detects a temperature of the device region.
However, Fig. 1 of Okuda teaches where the semiconductor device includes a device region (Item 6) which is arranged in the main surface; and a functional device which is formed in the device region; wherein the temperature detecting region (Item 8; Paragraph 0042) is arranged so as to be adjacent to the device region (Item 6), and the temperature-sensitive diode detects a temperature of the device region (Paragraph 0043).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a device region which is arranged in the main surface; and a functional device which is formed in the device region; wherein the temperature detecting region is arranged so as to be adjacent to the device region, and the temperature-sensitive diode detects a temperature of the device region because the temperature sensor circuit protects the semiconductor device from excessive temperature rise (Okuda Paragraph 0043).
Regarding claim 14, Fig. 2 of Okuda further teaches where a functional device includes a trench gate structure which has an electrode structure including an upper gate electrode (Item 32) and a lower gate electrode (Item 30) which are embedded in a gate trench across a gate insulator in an up/down direction.
Regarding claim 15, Fig. 2 of Okuda further teaches where the functional device includes a plural-system gate divided transistor that includes system transistors, each of which is formed in the main surface so as to be individually controlled, and that generates a single output signal by selectively controlling the system transistors.
Claims 1-5, 7-12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Williams et al. (US 6,046,470) hereinafter “Williams” in view of Okuda et al. (US 2018/0226480) hereinafter “Okuda”.
Regarding claim 1, Fig. 6 of Williams teaches a semiconductor device comprising: a chip which has a main surface; a diode region which is arranged in the main surface; trench structures (Item 105) which are formed in the main surface at an interval in the diode region; and a diode which has a pn-junction portion (Combination of Items 114 and 110) that is formed in a surface layer portion of the main surface at a region between the trench structures.
Williams does not teach the trench structures each having an electrode structure that includes an upper electrode and a lower electrode which are embedded in a trench across an insulator in an up/down direction.
Okuda teaches where trench structures each have an electrode structure that include an upper electrode (Item 32) and a lower electrode (Item 30) which are embedded in a trench across an insulator (Combination of Items 31 and 29) in an up/down direction.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the trench structures each having an electrode structure that includes an upper electrode and a lower electrode which are embedded in a trench across an insulator in an up/down direction because this allows for reduction in on-resistance of a semiconductor layer in which the trench is embedded which suppresses power consumption (Okuda Paragraph 0061).
Regarding claim 2, Fig. 6 of Williams further teaches a first conductive type (P-type) body region (Item 116) which is formed in the surface layer portion of the main surface in the diode region; wherein the trench structures are formed in the main surface so as to penetrate through the body region (Item 116), and the diode includes a first conductive type first polarity region (Combination of Items 114 and 116) which is formed in the body region and a second conductive type (N-type) second polarity region (Item 110) which is formed in the body region so as to form the pn-junction portion with the first polarity region (Combination of Items 114 and 116).
Regarding claim 3, Fig. 6 of Williams further teaches where the first polarity region (Combination of Items 114 and 116) includes a high concentration region (Item 114) which has an impurity concentration higher than that of the body region and a low concentration region (Item 116) which has an impurity concentration lower than that of the high concentration region (Item 114), and the second polarity region (Item 110) forms the pn-junction portion with the low concentration region (Item 116) of the first polarity region (Combination of Items 114 and 116).
Regarding claim 4, Fig. 6 of Williams further teaches where the low concentration region (Item 116) is constituted of a part of the body region (Item 116).
Regarding claim 5, the combination of Williams and Okuda teaches all of the elements of the claimed invention as stated above except where the upper electrodes of the trench structures are embedded on the main surface side with respect to a bottom portion of the body region, and the lower electrodes of the trench structures are embedded on the bottom wall side of the trench with respect to the bottom portion of the body region.
Fig. 2 of Okuda further teaches where the upper electrodes (Item 32) of the trench structures are embedded on the main surface side with respect to a bottom portion of the body region (Item 45), and the lower electrodes (Item 30) of the trench structures are embedded on the bottom wall side of the trench with respect to the bottom portion of the body region (Item 45).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the upper electrodes of the trench structures are embedded on the main surface side with respect to a bottom portion of the body region, and the lower electrodes of the trench structures are embedded on the bottom wall side of the trench with respect to the bottom portion of the body region because this allows for reduction in on-resistance of a semiconductor layer in which the trench is embedded which suppresses power consumption (Okuda Paragraph 0061).
Regarding claim 7, the combination of Williams and Okuda teaches all of the elements of the claimed invention as stated above except where the insulator includes an upper insulating film which covers an upper wall surface of the trench with a first thickness and a lower insulating film which covers a lower wall surface of the trench with a second thickness exceeding the first thickness, the upper electrode is embedded on the upper wall surface side of the trench across the upper insulating film, and the lower electrode is embedded on the lower wall surface side of the trench across the lower insulating film.
Fig. 2 of Okuda further teaches where the insulator (Combination of Items 29 and 31) includes an upper insulating film (Item 31) which covers an upper wall surface of the trench with a first thickness and a lower insulating film (Item 29) which covers a lower wall surface of the trench with a second thickness exceeding the first thickness, the upper electrode (Item 32) is embedded on the upper wall surface side of the trench across the upper insulating film (Item 31), and the lower electrode (Item 30) is embedded on the lower wall surface side of the trench across the lower insulating film (Item 29).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the insulator includes an upper insulating film which covers an upper wall surface of the trench with a first thickness and a lower insulating film which covers a lower wall surface of the trench with a second thickness exceeding the first thickness, the upper electrode is embedded on the upper wall surface side of the trench across the upper insulating film, and the lower electrode is embedded on the lower wall surface side of the trench across the lower insulating film because this allows for reduction in on-resistance of a semiconductor layer in which the trench is embedded which suppresses power consumption (Okuda Paragraph 0061).
Regarding claim 8, the combination of Williams and Okuda teaches all of the elements of the claimed invention as stated above except a separation structure which is formed in the main surface so as to electrically separate the diode region from another region.
Fig. 4 of Okuda further teaches a separation structure (Item 61) which is formed in the main surface so as to electrically separate the diode region (Item 6) from another region (Item 7).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a separation structure which is formed in the main surface so as to electrically separate the diode region from another region because this structure is known to electrically separate devices all present on the same chip surface (Okuda Paragraph 0095).
Regarding claim 9, the combination of Williams and Okuda teaches all of the elements of the claimed invention as stated above except where the separation structure includes a separation electrode which is embedded in a separation trench across a separation insulator.
Fig. 4 of Okuda further teaches where the separation structure (Item 61) includes a separation electrode (Item 66) which is embedded in a separation trench across a separation insulator (Item 65).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the separation structure includes a separation electrode which is embedded in a separation trench across a separation insulator because this structure is known to electrically separate devices all present on the same chip surface (Okuda Paragraph 0095).
Regarding claim 10, Fig. 6 of Williams further teaches where the diode region is a temperature detecting region, and the diode is a temperature sensitive diode (Column 5, Lines 54-56).
Regarding claim 11, Williams further teaches where the temperature-sensitive diode has temperature characteristics in which a forward direction voltage linearly changes in response to a change in temperature (Column 2, Lines 65-67).
Regarding claim 12, the combination of Williams and Okuda teaches all of the elements of the claimed invention as stated above.
Williams does not teach where a device region which is arranged in the main surface; and a functional device which is formed in the device region; wherein the temperature detecting region is arranged so as to be adjacent to the device region, and the temperature-sensitive diode detects a temperature of the device region.
Fig. 1 of Okuda teaches where the semiconductor device includes a device region (Item 6) which is arranged in the main surface; and a functional device which is formed in the device region; wherein the temperature detecting region (Item 8; Paragraph 0042) is arranged so as to be adjacent to the device region (Item 6), and the temperature-sensitive diode detects a temperature of the device region (Paragraph 0043).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a device region which is arranged in the main surface; and a functional device which is formed in the device region; wherein the temperature detecting region is arranged so as to be adjacent to the device region, and the temperature-sensitive diode detects a temperature of the device region because the temperature sensor circuit protects the semiconductor device from excessive temperature rise (Okuda Paragraph 0043).
Regarding claim 14, the combination of Williams and Okuda teaches all of the elements of the claimed invention as stated above.
Williams does not teach where the functional device includes a trench gate structure which has an electrode structure including an upper gate electrode and a lower gate electrode which are embedded in a gate trench across a gate insulator in an up/down direction.
Fig. 2 of Okuda further teaches where a functional device includes a trench gate structure which has an electrode structure including an upper gate electrode (Item 32) and a lower gate electrode (Item 30) which are embedded in a gate trench across a gate insulator in an up/down direction.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the functional device includes a trench gate structure which has an electrode structure including an upper gate electrode and a lower gate electrode which are embedded in a gate trench across a gate insulator in an up/down direction because this allows for reduction in on-resistance of a semiconductor layer in which the trench is embedded which suppresses power consumption (Okuda Paragraph 0061).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Williams et al. (US 6,046,470) hereinafter “Williams” in view of Okuda et al. (US 2018/0226480) hereinafter “Okuda” and in further view of Katou et al. (US 2013/0256783) hereinafter “Katou”.
Regarding claim 6, the combination of Williams and Okuda teaches all of the elements of the claimed invention as stated above except where the first polarity region is fixed at the same potential as one of or both of the upper electrode and the lower electrode of the trench structures.
Katou teaches where a gate electrode buried in a trench has the same potential as a cathode or anode of a temperature sensitive diode (Paragraph 0137).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the first polarity region be fixed at the same potential as one of or both of the upper electrode and the lower electrode of the trench structures because this prevents the characteristics of the diode from varying and improves the performance of the semiconductor device (Katou Paragraph 0217).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Okuda et al. (US 2018/0226480) hereinafter “Okuda” in view of Williams et al. (US 6,046,470) hereinafter “Williams” and in further view of Hoshi (US 2021/0013196) hereinafter “Hoshi”.
Regarding claim 13, the combination of Okuda and Williams teaches all of the elements of the claimed invention as stated above except where the temperature detecting region is arranged in a region which is surrounded by the device region.
Figs. 11 and 12 of Hoshi teaches where a temperature detecting region (Item 35b) is arranged in a region which is surrounded by a device region (Item 50).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the temperature detecting region be arranged in a region which is surrounded by the device region because this allows for accuracy of a temperature measurement to be enhanced (Hoshi Paragraph 0052).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Williams et al. (US 6,046,470) hereinafter “Williams” in view of Okuda et al. (US 2018/0226480) hereinafter “Okuda” and in further view of Hoshi (US 2021/0013196) hereinafter “Hoshi”.
Regarding claim 13, the combination of Williams and Okuda teaches all of the elements of the claimed invention as stated above except where the temperature detecting region is arranged in a region which is surrounded by the device region.
Figs. 11 and 12 of Hoshi teaches where a temperature detecting region (Item 35b) is arranged in a region which is surrounded by a device region (Item 50).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the temperature detecting region be arranged in a region which is surrounded by the device region because this allows for accuracy of a temperature measurement to be enhanced (Hoshi Paragraph 0052).
Claims 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Okuda et al. (US 2018/0226480) hereinafter “Okuda” in view of Williams et al. (US 6,046,470) hereinafter “Williams” and in further view of Yedinak (US 2022/0181480) hereinafter “Yedinak”.
Regarding claim 16, the combination of Okuda and Williams teaches all of the elements of the claimed invention as stated above except a device region which is arranged in the main surface; and a functional device which is formed in the device region; wherein the diode region is a protection region, and the diode is an electrostatic breakdown protection diode.
However, Okuda teaches a device region (Portion of Item 6) which is arranged in the main surface; a functional device (Paragraph 0040) which is formed in the device region (Portion of Item 6) and a protection circuit region (Item 8) where the protection circuit region (Item 8) includes a diode region (Paragraph 0043).
Okuda does not teach where the diode is an electrostatic breakdown protection diode.
Yedinak teaches where a protection circuit diode is an electrostatic breakdown protection diode (Paragraph 0021).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the diode region be an electrostatic breakdown protection diode because this structure is known to protect the device region from electrostatic discharge (Yedinak Paragraph 0021).
Regarding claim 17, the combination of Okuda, Williams and Yedinak teaches all of the elements of the claimed invention as stated above.
Okuda does not teach the device further comprising a terminal electrode which is arranged on the main surface so as to be electrically connected to the functional device; wherein the electrostatic breakdown protection diode is electrically connected to the terminal electrode.
Fig. 3C of Yedinak further teaches a terminal electrode (Item 304) which is arranged on the main surface so as to be electrically connected to the functional device (Item 320); wherein the electrostatic breakdown protection diode (Item 324) is electrically connected to the terminal electrode (Item 304).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a terminal electrode which is arranged on the main surface so as to be electrically connected to the functional device; wherein the electrostatic breakdown protection diode is electrically connected to the terminal electrode because this allows the protection device to protect the functional device from electrostatic discharge (Yedinak Paragraph 0021).
Claims 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Williams et al. (US 6,046,470) hereinafter “Williams” in view of Okuda et al. (US 2018/0226480) hereinafter “Okuda” and in further view of Yedinak (US 2022/0181480) hereinafter “Yedinak”.
Regarding claim 16, the combination of Williams and Okuda teaches all of the elements of the claimed invention as stated above except a device region which is arranged in the main surface; and a functional device which is formed in the device region; wherein the diode region is a protection region, and the diode is an electrostatic breakdown protection diode.
Okuda teaches a device region (Portion of Item 6) which is arranged in the main surface; and a functional device (Paragraph 0040) which is formed in the device region (Portion of Item 6) and a protection circuit region (Item 8) where the protection circuit region (Item 8) includes a diode region (Paragraph 0043).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a device region which is arranged in the main surface; and a functional device which is formed in the device region; wherein the diode region is a protection region because the diode in the protection region protects the functional device in the device region (Okuda Paragraph 0042).
Williams does not teach where the diode is an electrostatic breakdown protection diode.
Yedinak teaches where a protection circuit diode is an electrostatic breakdown protection diode (Paragraph 0021).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the diode region be an electrostatic breakdown protection diode because this structure is known to protect the device region from electrostatic discharge (Yedinak Paragraph 0021).
Regarding claim 17, the combination of Williams, Okuda and Yedinak teaches all of the elements of the claimed invention as stated above.
Williams does not teach the device further comprising a terminal electrode which is arranged on the main surface so as to be electrically connected to the functional device; wherein the electrostatic breakdown protection diode is electrically connected to the terminal electrode.
Fig. 3C of Yedinak further teaches a terminal electrode (Item 304) which is arranged on the main surface so as to be electrically connected to the functional device (Item 320); wherein the electrostatic breakdown protection diode (Item 324) is electrically connected to the terminal electrode (Item 304).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a terminal electrode which is arranged on the main surface so as to be electrically connected to the functional device; wherein the electrostatic breakdown protection diode is electrically connected to the terminal electrode because this allows the protection device to protect the functional device from electrostatic discharge (Yedinak Paragraph 0021).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Williams et al. (US 6,046,470) hereinafter “Williams” in view of Yedinak (US 2022/0181480) hereinafter “Yedinak” and in further view of Okuda et al. (US 2018/0226480) hereinafter “Okuda”.
Regarding claim 1, Fig. 6 of Williams teaches a semiconductor device comprising: a chip which has a main surface; a temperature detecting region (Item 104) which is arranged in the main surface; first trench structures (Items 105) which are formed in the main surface at an interval in the temperature detecting region, the first trench structures each having an electrode structure including a first electrode which are embedded in a first trench across a first insulator in an up/down direction; a temperature-sensitive diode (Item D1’) which has a first pn-junction portion that is formed in a surface layer portion of the main surface at a region between the first trench structures (Items 105).
Williams does not teach a protection region which is arranged in a region different from the temperature detecting region in the main surface.
Yedinak teaches where a protection circuit diode and a temperature sensing circuit diode may be present in the main surface of a device chip (Paragraph 0021).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a protection region which is arranged in a region different from the temperature detecting region in the main surface because the protection region is known to protect the device region from electrostatic discharge (Yedinak Paragraph 0021) while the temperature detecting region is known to sense a device temperature which can be attached to a control circuit (Paragraphs 0021 and 0076).
Williams does not teach where the protection circuit includes an electrostatic breakdown protection diode that has a second pn-junction portion which is formed in the surface layer portion of the main surface at a region between second trench structures which are formed in the main surface at an interval in the protection region.
Yedinak teaches where a protection circuit diode is an electrostatic breakdown protection diode (Paragraph 0021) which includes a pn-junction between trench structures.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the protection circuit includes an electrostatic breakdown protection diode that has a second pn-junction portion which is formed in the surface layer portion of the main surface at a region between second trench structures which are formed in the main surface at an interval in the protection region structures because this structure is known to protect the device region from electrostatic discharge (Yedinak Paragraph 0021).
Williams does not teach the first trench structures each having an electrode structure including a first upper electrode and a first lower electrode which are embedded in a first trench across an first insulator in an up/down direction nor the second trench structures each having an electrode structure including a second upper electrode and a second lower electrode which are embedded in a second trench across a second insulator in an up/down direction.
Okuda teaches where trench structures each have an electrode structure that include an upper electrode (Item 32) and a lower electrode (Item 30) which are embedded in a trench across an insulator (Combination of Items 31 and 29) in an up/down direction.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the first trench structures each having an electrode structure including a first upper electrode and a first lower electrode which are embedded in a first trench across an first insulator in an up/down direction and the second trench structures each having an electrode structure including a second upper electrode and a second lower electrode which are embedded in a second trench across a second insulator in an up/down direction because this allows for reduction in on-resistance of a semiconductor layer in which the trench is embedded which suppresses power consumption (Okuda Paragraph 0061).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Williams et al. (US 6,046,470) hereinafter “Williams” in view of Yedinak (US 2022/0181480) hereinafter “Yedinak” and Okuda et al. (US 2018/0226480) hereinafter “Okuda” and in further view of Okuda et al. (US 2019/0115290) hereinafter “Okuda2”.
Regarding claim 19, the combination of Williams, Yedinak and Okuda teaches all of the elements of the claimed invention as stated above.
Williams further teaches where the device comprises a control region and a control circuit which is formed in the control region (Column 3, Lines 25-26).
Williams does not explicitly teach where the control region is arranged in the main surface.
Okuda2 teaches a circuit protection portion (Item 42) having a temperature sensitive device (Paragraph 0070) and a control region (Item 13) arranged in a main surface; and a control circuit (Item 16) which is formed in the control region (Paragraph 0032).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the control region be arranged in the main surface because this allows a number of devices to be incorporated on the same chip in a single package being an intelligent power device (Okuda2 Paragraph 0029) which reduces the length of connections between control and protection regions.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Okuda et al. (US 2018/0226480) hereinafter “Okuda” in view of Okuda et al. (US 2019/0115290) hereinafter “Okuda2”.
Regarding claim 20, Figs. 1 and 4 of Okuda teach a semiconductor module comprising: the semiconductor device according to claim 1 (See the rejection of claim 1 above; For brevity the rejection of claim 1 will not be repeated here in its entirety).
Okuda does not explicitly teach a control device which is electrically connected to the semiconductor device and controls the semiconductor device.
Okuda2 teaches a circuit protection portion (Item 42) having a temperature sensitive device (Paragraph 0070) and a control device (Item 16) which is electrically connected to a semiconductor device and controls the semiconductor device (Paragraph 0033).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include a control device which is electrically connected to the semiconductor device and controls the semiconductor device because the control device controls the active devices elsewhere on a chip (Okuda2 Paragraph 0033).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Williams et al. (US 6,046,470) hereinafter “Williams” in view of Okuda et al. (US 2018/0226480) hereinafter “Okuda” and in further view of Okuda et al. (US 2019/0115290) hereinafter “Okuda2”.
Regarding claim 20, the combination of Williams and Okuda teaches a semiconductor module comprising: the semiconductor device according to claim 1 (See the rejection of claim 1 above; For brevity the rejection of claim 1 will not be repeated here in its entirety).
Williams teaches where a control circuit is used in tandem with active devices on the chip (Column 2, Lines 24-27). However, Williams does not explicitly teach a control device which is electrically connected to the semiconductor device and controls the semiconductor device.
Okuda2 teaches a circuit protection portion (Item 42) having a temperature sensitive device (Paragraph 0070) and a control device (Item 16) which is electrically connected to a semiconductor device and controls the semiconductor device (Paragraph 0033).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include a control device which is electrically connected to the semiconductor device and controls the semiconductor device because the control device controls the active devices elsewhere on a chip (Okuda2 Paragraph 0033).
Conclusion
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/ERIC K ASHBAHIAN/Primary Examiner, Art Unit 2891
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