DETAILED ACTION
This office action is in response to the remarks filed on 01/23/206.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 6-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kado in view of Xiao et al. US 2023/0412088.
Regarding Claim 1, Kado teaches (Figures 1-8) a switching power supply device with synchronous rectification (Fig. 1), comprising: a transformer (10) that receives an input voltage (Vin) on a primary side; a synchronous rectifier element (S0) that conducts/breaks a current of a secondary-side coil of the transformer (Ls of 10); and a synchronous rectifier control circuit (20) that drives the synchronous rectifier element to be on/off, wherein the synchronous rectifier control circuit (Fig. 2) includes: an ON-timing detection circuit (21) that detects a turn-on timing to turn on the synchronous rectifier element based on a terminal voltage of the synchronous rectifier element (with 21); an OFF-timing detection circuit (22 and g1) that detects a turn-off timing to turn off the synchronous rectifier element by comparing the terminal voltage of the synchronous rectifier element with a predetermined turn-off threshold voltage (Vthoff); and an ON/OFF control circuit (28) that generates an ON/OFF control signal for the synchronous rectifier element based on an output signal of the ON-timing detection circuit and an output signal of the OFF-timing detection circuit (Fig. 2); a voltage adjustment circuit (27) that, based on a change in the terminal voltage of the synchronous rectifier element (inputs at 27 include OFFsig, VDP, DCMsig and judge sig), corrects the turn-off threshold voltage (Figs. 7a-b) such that the turn-off timing of the synchronous rectifier element gets closer to a point at which a current flowing in the synchronous rectifier element becomes zero (Par. 68-71 and 82), the turn-off threshold voltage being used by the OFF-timing detection circuit to detect the turn-off timing of the synchronous rectifier element (Fig. 2 output of 27 sent to 22); a voltage decrease detection circuit (with 23 and 24) that detects a decrease in the terminal voltage of the synchronous rectifier element (Vd), and wherein the voltage adjustment circuit adjusts the turn-off threshold voltage in accordance with a result of the detection by the voltage decrease detection circuit (27 receives VDP, DCMsig and Judge sig signals to modify the Vthoff). (For example: Par. 57-62, 64-71 and 82)
Kado does not teach a discharge circuit that performs discharge of releasing a charge of a gate terminal of the synchronous rectifier element before the turn-off timing of the synchronous rectifier element to reduce a gate voltage of the gate terminal; the decrease in the terminal voltage being caused by the gate voltage of the synchronous rectifier element by the discharge of the discharge circuit.
Xiao teaches (Figures 1-4) a discharge circuit (21) that performs discharge of releasing a charge of a gate terminal of the synchronous rectifier element (SR) before the turn-off timing of the synchronous rectifier element to reduce a voltage of the gate terminal (see fig. 4); the decrease in the terminal voltage (Vdss) being caused by the gate voltage (Vg) of the synchronous rectifier element (Sr) by the discharge of the discharge circuit (21). (For Example: Par. 22-27)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Kado to include a discharge circuit that performs discharge of releasing a charge of a gate terminal of the synchronous rectifier element before the turn-off timing of the synchronous rectifier element to reduce a voltage of the gate terminal; the decrease in the terminal voltage being caused by the gate voltage of the synchronous rectifier element by the discharge of the discharge circuit, as taught by Xiao to provide operation of the switch without causing the drain-source voltage of the rectifier device to have excessive disturbance and resulting in false turn-off.
Regarding Claim 3, Kado teaches (Figures 1-8) a device.
Kado does not teach wherein after starting the discharge, the discharge circuit stops the discharge before a control voltage for the synchronous rectifier element decreases to a potential at which the synchronous rectifier element is put in an OFF state to shift the synchronous rectifier element from a low ON-resistance state as a state before the discharge circuit starts the discharge to a high ON-resistance state.
Xiao teaches (Figures 1-4) wherein after starting the discharge (see fig. 4 Vgs being reduce), the discharge circuit stops the discharge before a control voltage for the synchronous rectifier element decreases to a potential at which the synchronous rectifier element is put in an OFF state (see fig. 4 the I1 current is being applied to the gate of the SR switch and at P3 is no longer provided before the Vdss reaches Voff) to shift the synchronous rectifier element from a low ON-resistance state as a state before the discharge circuit starts the discharge to a high ON-resistance state (turning of the SR switch). (For Example: Par. 22-27)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Kado to include wherein after starting the discharge, the discharge circuit stops the discharge before a control voltage for the synchronous rectifier element decreases to a potential at which the synchronous rectifier element is put in an OFF state to shift the synchronous rectifier element from a low ON-resistance state as a state before the discharge circuit starts the discharge to a high ON-resistance state; as taught by Xiao to provide operation of the switch without causing the drain-source voltage of the rectifier device to have excessive disturbance and resulting in false turn-off.
Regarding Claim 6, Kado teaches (Figures 1-8) wherein in a case where the voltage decrease detection circuit detects a decrease in the terminal voltage of the synchronous rectifier element (with 23 and 24), the voltage adjustment circuit adjusts the turn-off threshold voltage such that the turn-off timing is delayed (Fig. 7a operation, par. 64). (For example: Par. 57-62, 64-71 and 82)
Regarding Claim 7, Kado teaches (Figures 1-8)wherein in a case where the voltage decrease detection circuit detects no decrease in the terminal voltage of the synchronous rectifier element (with 23 and 24), the voltage adjustment circuit adjusts the turn-off threshold voltage such that the turn-off timing is moved up (Fig. 7b, par. 65). (For example: Par. 57-62, 64-71 and 82)
Regarding Claim 12, Kado teaches (Figures 1-8) wherein in a case where the voltage decrease detection circuit detects a decrease in the terminal voltage of the synchronous rectifier element (with 23 and 24), the voltage adjustment circuit adjusts the turn-off threshold voltage such that the turn-off timing is delayed (Fig. 7a operation, par. 64). (For example: Par. 57-62, 64-71 and 82)
Allowable Subject Matter
Claims 8-10 and 13 are allowed.
Reasons for Indicating Allowable Subject Matter
The following is an examiner’s statement of reasons for indicating Allowable Subject Matter:
Claim 8; prior art of record fails to disclose either by itself or in combination: “…wherein the synchronous rectifier control circuit further includes: a first detection circuit that detects a state in which the terminal voltage of the synchronous rectifier element is equal to or less than a predetermined potential; and a second detection circuit that detects a decrease in the terminal voltage of the synchronous rectifier element after the discharge circuit starts the discharge, and wherein the voltage adjustment circuit includes: a first latch circuit that takes in an output signal of the second detection circuit in response to a change in an output signal of the first detection circuit; a pulse generation circuit that generates a pulse signal having a predetermined pulse width in response to a change in the output signal of the ON-timing detection circuit; a first logic circuit that obtains a logical product of an output signal of the first latch circuit and the pulse signal generated by the pulse generation circuit; and a second logic circuit that obtains a logical product of an inverted output signal of the first latch circuit and the pulse signal generated by the pulse generation circuit, and wherein the voltage adjustment circuit changes the turn-off threshold voltage to be higher by a first predetermined amount based on an output signal of the first logic circuit, and changes the turn-off threshold voltage to be lower by a second predetermined amount based on an output signal of the second logic circuit, the second predetermined amount being identical with or different from the first predetermined amount”.
These features taken alone or in combination are neither disclosed nor suggested by the prior art of record.
Response to Arguments
Applicant's arguments filed 01/23/2026 have been fully considered but they are not persuasive.
Applicant argued that “Applicant respectfully disagrees. It is respectfully submitted that Kado does not disclose, teach or even suggest "a voltage decrease detection circuit that detects a decrease in the terminal voltage of the synchronous rectifier element, the decrease in the terminal voltage being caused by a decrease in the gate voltage of the synchronous rectifier element by the discharge of the discharge circuit," as recited in amended Claim 1”. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). The combination of Kado and Xiao teaches the claimed limitations, see rejection above.
Applicant argued that “Xiao fails to compensate for the deficiencies of Kado, nor was Xiao cited for such purposes. That is, Xiao further fails to teach or suggest "a voltage decrease detection circuit that detects a decrease in the terminal voltage of the synchronous rectifier element, the decrease in the terminal voltage being caused by a decrease in the gate voltage of the synchronous rectifier element by the discharge of the discharge circuit," as recited in amended Claim 1”.In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Xiao teaches (Figures 1-4) a discharge circuit (21) that performs discharge of releasing a charge of a gate terminal of the synchronous rectifier element (SR) before the turn-off timing of the synchronous rectifier element to reduce a voltage of the gate terminal (see fig. 4); the decrease in the terminal voltage (Vdss) being caused by the gate voltage (Vg) of the synchronous rectifier element (Sr) by the discharge of the discharge circuit (21).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO A ROSARIO-BENITEZ whose telephone number is (571)270-7888. The examiner can normally be reached M-F 9AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MONICA LEWIS can be reached at 5712721838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/GUSTAVO A ROSARIO-BENITEZ/Primary Examiner, Art Unit 2838