DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Species A2 in the reply filed on 07/28/2026 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/17/2024 and 08/23/2024 have been considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 4, 8-9, and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Re claim 2, Claim 2 recites the limitation "the upper section". There is insufficient antecedent basis for this limitation in the claim. Refer to the Examiner’s Mark-up as to what is being interpreted as “the upper section”.
Re claims 4 and 18, The term “about” in claims 4 and 18 is a relative term which renders the claim indefinite. The term “about” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
Re claim 7, It is not clear what the term “dummy length” means, it appears to be the same as “length” and will be interpreted as such.
Re claim 9, It is not clear what the phrase “alternatively provided in plural” is supposed to mean. No such language is used in Applicant’s Specification, and the Examiner is not aware of this being a known term of art. Until further clarification is provided, Baek et al. (US Pub. 2022/0392916) will be considered to meet the claim.
Appropriate corrections are required.
Examiner’s Mark-up
[AltContent: textbox (inner)][AltContent: textbox (Upper
Section)][AltContent: connector][AltContent: connector][AltContent: textbox (2nd)][AltContent: textbox (1st)][AltContent: connector][AltContent: connector][AltContent: connector][AltContent: connector][AltContent: connector]
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159
182
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From Fig. 2A of Baek et al. (US Pub. 2022/0392916)
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-9 and 11-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Baek et al. (US Pub. 2022/0392916).
Regarding independent claim 1, Baek teaches a semiconductor device (Figs. 1-3; para. 0034+) comprising:
a gate stacking structure that comprises a first stacking structure (ST1) and a second stacking structure (ST2) on the first stacking structure, the first stacking structure and the second stacking structure each comprising a plurality of gate electrodes (130);
a channel structure (CH) that extends into the gate stacking structure; and
a plurality of gate contact portions (170, 175) that are respectively connected to the plurality of gate electrodes of a first pad area (PAD1a, PAD1b, PAD1c) of the first stacking structure or a second pad area of the second stacking structure (PAD2a, PAD2b, PAD2c);
wherein the first stacking structure comprises a buffer insulating portion (192) that comprises a boundary portion (125) that is adjacent to the second pad area,
wherein the buffer insulating portion comprises a first section, a second section, and an inner section that is between the first section and the second section in a first direction (Refer to Fig. 2A/Examiner’s Mark-up),
wherein a length of an upper portion of each of the first section and the second section in the first direction is greater than a length of a lower portion of each of the first section and the second section, respectively (Fig. 2A), and
wherein a first length difference between the length of the upper portion of the first section and the length of the lower portion of the first section is less than a second length difference between the length of the upper portion of the second section and the length of the lower portion of the second section (Fig. 2A).
Re claims 2-9, and 11-15, the limitations of these claims are evident from Figs. 2A, 3A and the Examiner’s Mark-up. Refer also to the 112 rejections for further information regarding the interpretation of claims 2, 4, 7, and 9.
Regarding independent claim 16, Baek teaches a semiconductor device (Figs. 1-3; para. 0034+) comprising:
a gate stacking structure that comprises a first stacking structure (ST1) and a second stacking structure (ST2) on the first stacking structure, the first stacking structure and the second stacking structure each comprising a plurality of gate electrodes (130);
a channel structure (CH) that extends into the gate stacking structure; and
a plurality of gate contact portions (170, 175) that are respectively connected to the plurality of gate electrodes of a first pad area (PAD1a, PAD1b, PAD1c) of the first stacking structure or a second pad area of the second stacking structure (PAD2a, PAD2b, PAD2c),
wherein the first stacking structure comprises a buffer insulating portion (192) that comprises a boundary portion (125) that is adjacent to the second pad area,
wherein at least one of the first pad area and the second pad area comprises a pad section that respectively connects the plurality of gate electrodes and the plurality of gate contact portions and an upper section at an upper portion of the pad section (Fig. 3A),
wherein the buffer insulating portion comprises a first section, a second section, and an inner section that is between the first section and the second section in a first direction of the plurality of gate electrodes (Refer to Fig. 2A/Examiner’s Mark-up)
wherein a first distance between a gate electrode of the plurality of gate electrodes and the inner section and a second distance between the gate electrode and the inner section are greater than a third distance, wherein the first distance is in the first section, wherein the second distance is in the second section, and wherein the third distance is between the upper section and the gate electrode or between an inner section of the upper section and the gate electrode (Fig. 2A).
Re claims 17-19, the limitations of these claims are evident from Figs. 2A, 3A and the Examiner’s Mark-up. Refer also to the 112 rejections for further information regarding the interpretation of claim 18.
Regarding independent claim 20, Baek teaches an electronic system (Fig. 13; para. 0181+) comprising:
a main substrate (2001) (para. 0182);
a semiconductor device (2003) on the main substrate (para. 0182); and
a controller (2002) that is connected to the semiconductor device on the main substrate (para. 0182),
wherein the semiconductor device includes (para. 0187; Figs. 1-3; para. 0034+):
a gate stacking structure that comprises a first stacking structure (ST1) and a second stacking structure (ST2) on the first stacking structure, the first stacking structure and the second stacking structure each comprising a plurality of gate electrodes (130);
a channel structure (CH) that extends into the gate stacking structure; and
a plurality of gate contact portions (170, 175) that are respectively connected to the plurality of gate electrodes of a first pad area (PAD1a, PAD1b, PAD1c) of the first stacking structure or a second pad area of the second stacking structure (PAD2a, PAD2b, PAD2c);
wherein the first stacking structure comprises a buffer insulating portion (192) that comprises a boundary portion (125) that is adjacent to the second pad area,
wherein the buffer insulating portion comprises a first section, a second section, and an inner section that is between the first section and the second section in a first direction (Refer to Fig. 2A/Examiner’s Mark-up),
wherein a length of an upper portion of each of the first section and the second section in the first direction is greater than a length of a lower portion of each of the first section and the second section, respectively (Fig. 2A), and
wherein a first length difference between the length of the upper portion of the first section and the length of the lower portion of the first section is less than a second length difference between the length of the upper portion of the second section and the length of the lower portion of the second section (Fig. 2A).
Allowable Subject Matter
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOLLY KAY REIDA whose telephone number is (571)272-4237. The examiner can normally be reached M-F 8:30-5:00PM.
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/MOLLY K REIDA/Examiner, Art Unit 2899
