DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 8 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 8 includes “wherein upper surfaces of the first bonding pads exposed by the first passivation layer and upper surfaces of the first dummy patterns are on a same plane, and upper surfaces of the second bonding pads exposed by the second passivation layer and upper surfaces of the second dummy patterns are on a same plane.” It is unclear if the second bonding pads, second passivation layer, and second dummy patterns are on another same plane, or whether these elements are on “the same plane”. For the purpose of the instant examination, the Examiner interprets this as two distinctly different planes.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4,11-14, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kweon, et al. US 12512429 B2 (hereinafter Kweon) and further in view of Kim, et al. US 12431195 B2 (hereinafter Kim)
Regarding claim 1, Kweon discloses:
a first substrate structure including a first substrate (“a first chip structure” 100 [col. 3, line 67) includes a first substrate structure 100W [col.4, line14) having a first die region (first region R1 [col.6 line 16]) and a first scribe region surrounding the first die region (the edge of the die is defined by a scribe line), a plurality of first bonding pads in the first die region on a surface of the first substrate (“first bonding metal layers” 195 [col. 5, line 10]), a first passivation layer on the surface of the first substrate and exposing the first bonding pads (“first bonding insulating layer” 191 [col.5, line 10])
(FIG. 1 [col.3, line 67]; 195[col. 5, line 10]; 191[col. 5, line10]; claims 1, 4.)
a second substrate structure stacked on the first substrate structure, the second substrate structure including a second substrate (“a second chip structure” 200 [col. 3, line 67] includes a second substrate structure 200W [col. 4, line12]) having a second die region (second region R2 [col. 6, line 16]) and a second scribe region surrounding the second die region (the edge of the die is defined by a scribe line), a plurality of second bonding pads in the second die region on a surface of the second substrate (second bonding metal layers 295 [col. 5, line 25]), a second passivation layer on the surface of the second substrate and exposing the second bonding pads, (second bonding insulating layer 291 [col. 5, line 55]). (FIG. 2; and claims 1, 4.)
Kweon does not disclose:
a plurality of first dummy patterns in the first passivation layer in the first scribe region; and a plurality of second dummy patterns in the second passivation layer in the second scribe region.
Kim discloses a plurality of first dummy patterns in the first passivation layer in the first scribe region; and a plurality of second dummy patterns in the second passivation layer in the second scribe region.
(FIG. 2, DS1, DS2, DS3, DS4, claim 2. Note that Kim’s choice of words differs from Son’s, yet they refer to the same item.)
Son’s “first dummy patterns and second dummy patterns” are Kim’s “first dummy structure and second dummy structure.”
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to substitute Kim’s dummy structure to Kweon’s semiconductor device to improve manufacturing yield, structural integrity, and physical reliability.
Regarding claim 2, Kweon in view of Kim teaches the limitations of claim 1, as discussed above.
Kweon does not disclose:
The semiconductor device of claim 1, wherein the first dummy patterns and the second dummy patterns are directly bonded to each other.
Kim disclosed the semiconductor device of claim 1, wherein the first dummy patterns and the second dummy patterns are directly bonded to each other.
(FIG. 2, DS1, DS2, DS3, DS4, and claim 2)
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to substitute Kim’s dummy structure to Kweon’s semiconductor device to improve manufacturing yield, structural integrity, and physical reliability.
Regarding claim 3, Kweon in view of Kim teaches the limitations of claim 1, as discussed above.
Kweon does not disclose:
The semiconductor device of claim 1, wherein the first dummy patterns and the second dummy patterns include a first dielectric material.
Kim disclosed the semiconductor device of claim 1, wherein the first dummy patterns and the second dummy patterns include a first dielectric material.
(FIG. 2, DS1, DS2, DS3, DS4, 145, and claim 2)
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to substitute Kim’s dummy structure to Kweon’s semiconductor device to improve manufacturing yield, structural integrity, and physical reliability.
Regarding claim 4, Kweon in view of Kim teaches the limitations of claim 1, as discussed above.
Kweon disclosed:
The semiconductor device of claim 3, wherein the first passivation layer and the second passivation layer include a second dielectric material different from the first dielectric material. (Claim 8, claim 10.) Note that Kweon’s “barrier insulating layer” is silicon nitride or a silicon nitride- based material, which is common dielectric material.
Regarding claim 11, Kweon disclosed:
a first substrate structure having a first die region and a first scribe region surrounding the first die region (“a first chips structure” Abstract); and a second substrate structure stacked on the first substrate structure, the second substrate structure having a second die region overlapping the first die region and a second scribe region surrounding the second die region and overlapping the first scribe region (“a second chip structure disposed on an inner region of the upper surface of the first chip structure, and including second bonding metal layers respectively bonded to the first bonding metal layers ”Abstract), wherein the first substrate structure includes, a first circuit layer, in which first circuit patterns are provided, in the first die region, a plurality of first bonding pads in the first die region on the first circuit layer, the first bonding pads electrically connected to the first circuit patterns, a first passivation layer on the first circuit layer and exposing the first bonding pads (“a first chip structure comprising: a substrate, circuit elements disposed on the substrate, a wiring structure disposed on the circuit elements, first bonding metal layers disposed on the wiring structure, and a first bonding insulating layer disposed on the wiring structure and surrounding side surfaces of the first bonding metal layers,” Claim 1)
the second substrate structure includes, a second circuit layer, in which second circuit patterns are provided, in the second die region; a plurality of second bonding pads in the second die region on the second circuit layer, the second bonding pads electrically connected to the second circuit patterns; a second passivation layer on the second circuit layer and exposing the second bonding pads; the first bonding pads and the second bonding pads are directly bonded to each other, (“the second chip structure comprising: second bonding metal layers respectively bonded to the first bonding metal layers, a second bonding insulating layer surrounding side surfaces of the second bonding metal layers and bonded to the first bonding insulating layer, a second wiring structure disposed on the second bonding metal layers and the second bonding insulating layer, and a second device layer disposed on the second wiring structure and having second circuit elements; a protective insulating layer disposed on an upper surface of the second chip structure and having an extended portion extending to the edge region of the first chip structure along a side surface of the second chip structure; and a connection pad disposed in a region of the protective insulating layer located on the upper surface of the second chip structure, the connection pad being electrically connected to the second circuit elements.” Claim 12)
Kweon does not disclose:
a plurality of first dummy patterns in the first passivation layer in the first scribe region, wherein and a plurality of second dummy patterns in the second passivation layer in the second scribe region, and wherein the first dummy patterns and the second dummy patterns are directly bonded to each other.
Kim teaches:
a plurality of first dummy patterns in the first passivation layer in the first scribe region, wherein and a plurality of second dummy patterns in the second passivation layer in the second scribe region, and wherein the first dummy patterns and the second dummy patterns are directly bonded to each other
(FIG. 2, DS1, DS2, DS3, DS4, claim 1 [col.26, line 61-67], and claims 2, [col. 27, 10-16])
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to substitute Kim’s dummy structure to Kweon’s semiconductor device to improve manufacturing yield, structural integrity, and physical reliability.
Regarding claim 12, Kweon in view of Kim teaches the limitations of claim 11, as discussed above.
Kweon discloses:
the first passivation layer and the second passivation layer are directly bonded to each other. (The passivation layer has an extended portion extending to the edge region of the first chip structure along the side surface of the second chip structure. Claim 5)
Regarding claim 13, Kweon in view of Kim teaches the limitations of claim 11, as discussed above.
Kweon does not disclose:
The semiconductor device of claim 11, wherein the first dummy patterns and the second dummy patterns include a first dielectric material.
Kim disclosed the semiconductor device of claim 11, wherein the first dummy patterns and the second dummy patterns include a first dielectric material.
(FIG. 2, DS1, DS2, DS3, DS4, 145, and claims 2)
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to substitute Kim’s dummy structure to Kweon’s semiconductor device to improve manufacturing yield, structural integrity, and physical reliability.
Regarding claim 14, Kweon in view of Kim teaches the limitations of claim 11, as discussed above.
Kweon disclosed:
The semiconductor device of claim 13, wherein the first passivation layer and the second passivation layer include a second dielectric material different from the first dielectric material. (Claim 8, claim 10.) Note that Kweon’s “barrier insulating layer” is silicon nitride or a silicon nitride- based material, which is common dielectric material.
Regarding claim 20, Kweon discloses:
A semiconductor device, comprising: a first substrate structure including a first substrate having a first die region and a first scribe region surrounding the first die region, a plurality of first bonding pads in the first die region on a surface of the first substrate, a first passivation layer on the surface of the first substrate and exposing the first bonding pads, (“a first substrate structure divided into a plurality of first chip regions, the first substrate structure including a first wafer, a first device layer disposed on the first wafer, a wiring structure disposed on the first device layer, and a first bonding structure disposed on the wiring structure and including first bonding metal layers and a first bonding insulating layer surrounding the first bonding metal layers;” [col.2 line 47-54]);
a second substrate structure stacked on the first substrate structure, the second substrate structure including a second substrate having a second die region overlapping the first die region and a second scribe region surrounding the second die region and overlapping the first scribe region, a plurality of second bonding pads in the second die region on a surface of the second substrate, (a second chip structure disposed on the inner region of the upper surface of the first chip structure, the second chip structure comprising: second bonding metal layers respectively bonded to the first bonding metal layers, Claim 1)
a second passivation layer on the surface of the second substrate and exposing the second bonding pads, (FIG 2, 315, [col. 9, line33-36])
the first bonding pads and the second bonding pads are directly bonded to each other, (FIG 2, 295, 195 [col.45, line 46-48]
the first passivation layer and the second passivation layer are directly bonded to each other, (The passivation layer has an extended portion extending to the edge region of the first chip structure along the side surface of the second chip structure. Claim 5)
and the first passivation layer and the second passivation layer include a second dielectric material. (Claims 4, 8, 10.) Note that Kweon’s “barrier insulating layer” is silicon nitride or a silicon nitride- based material, which is common dielectric material.
Kweon does not disclose:
a plurality of first dummy patterns on the first passivation layer in the first scribe region; a plurality of second dummy patterns on the second passivation layer in the second scribe region, the first dummy patterns and the second dummy patterns are directly bonded to each other. the first dummy patterns and the second dummy patterns include a first dielectric material, the first dummy patterns and the second dummy patterns include a first dielectric material,
Kim teaches:
a plurality of first dummy patterns on the first passivation layer in the first scribe region; a plurality of second dummy patterns on the second passivation layer in the second scribe region, the first dummy patterns and the second dummy patterns are directly bonded to each other, the first dummy patterns and the second dummy patterns include a first dielectric material, and wherein the first dummy patterns and the second dummy patterns include a first dielectric material.
(FIG. 2, DS1, DS2, DS3, DS4, 145, and claims 2, 11)
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to substitute Kim’s dummy structure to Kweon’s semiconductor device to improve manufacturing yield, structural integrity, and physical reliability.
Claims 5 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Kweon in view of Kim further in view of Dunton, et al. US 6319836 B1 (hereinafter Dunton)
Regarding claim 5, Kweon in view of Kim teaches the limitations of claim 1, as discussed above.
Kweon does not disclose:
the first dielectric material has a first polishing rate by chemical mechanical polishing, the second dielectric material has a second polishing rate by chemical mechanical polishing, and the first polishing rate is greater than the second polishing rate.
Dunton disclosed:
the first dielectric material has a first polishing rate by chemical mechanical polishing, the second dielectric material has a second polishing rate by chemical mechanical polishing, and the first polishing rate is greater than the second polishing rate. (claim 1, [col.8, line 43-47])
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to substitute Dunton’s chemical mechanical polishing to Kweon to manage extreme thin-film tolerances, and allow manufacturers to scale down device sizes—a necessity for advanced node logic and 3D chips.
Regarding claim 15, Kweon in view of Kim teaches the limitations of claim 11, as discussed above.
Kweon does not disclose:
the first dielectric material has a first polishing rate by chemical mechanical polishing, the second dielectric material has a second polishing rate by chemical mechanical polishing, and the first polishing rate is greater than the second polishing rate.
Dunton disclosed:
the first dielectric material has a first polishing rate by chemical mechanical polishing, the second dielectric material has a second polishing rate by chemical mechanical polishing, and the first polishing rate is greater than the second polishing rate. (claim 1, [col.8, line 43-47])
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to substitute Dunton’s chemical mechanical polishing to Kweon to manage extreme thin-film tolerances, and allow manufacturers to scale down device sizes—a necessity for advanced node logic and 3D chips.
Claims 6 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Kweon in view of Kim further in view of Yang, et al. US 20220208727 A1 (hereinafter Yang)
Regarding claim 6, Kweon in view of Kim teaches the limitations of claim 1, as discussed above.
Kweon does not disclose:
first dielectric material comprises silicon oxide and the second dielectric material comprises silicon carbonitride.
Yang disclosed:
first dielectric material comprises silicon oxide and the second dielectric material comprises silicon carbonitride. (paragraph [0007], line 5, 6)
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to substitute Yang’s dielectric material to Kweon to provide superior hardness and high thermal stability, protecting underlying circuitry from thermal stress and mechanical damage during subsequent fabrication steps.
Regarding claim 16, Kweon in view of Kim teaches the limitations of claim 11, as discussed above.
Kweon does not disclose:
first dielectric material comprises silicon oxide and the second dielectric material comprises silicon carbonitride.
Yang disclosed:
first dielectric material comprises silicon oxide and the second dielectric material comprises silicon carbonitride. (paragraph [0007], line 5, 6)
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to substitute Yang’s dielectric material to Kweon to provide superior hardness and high thermal stability, protecting underlying circuitry from thermal stress and mechanical damage during subsequent fabrication steps.
Claims 7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kweon in view of Kim further in view of Watanuki et al. US 20170068051 A1 (hereinafter Watanuki)
Regarding claim 7, Kweon in view of Kim teaches the limitations of claim 1, as discussed above.
Kweon does not disclose:
each of the first dummy patterns and the second dummy patterns has a width within a range of 0.1 μm to 1 μm.
Watanuki disclosed:
each of the first dummy patterns and the second dummy patterns has a width within a range of 0.1 μm to 1 μm. (paragraph [0102], line 17,18)
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to substitute Watanuki’s dummy patterns to Kweon’s semiconductor device to improve manufacturing yield, structural integrity, and physical reliability.
Regarding claim 17, Kweon in view of Kim teaches the limitations of claim 11, as discussed above. And further in review with Watanuki et al. US 20170068051 A1 (hereinafter Watanuki) teaches the limitation of claim 17.
Kweon does not disclose:
each of the first dummy patterns and the second dummy patterns has a width within a range of 0.1 μm to 1 μm.
Watanuki disclosed:
each of the first dummy patterns and the second dummy patterns has a width within a range of 0.1 μm to 1 μm. (paragraph [0102], line 17,18)
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to substitute Watanuki’s dummy patterns to Kweon’s semiconductor device to improve manufacturing yield, structural integrity, and physical reliability.
Claims 8 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kweon in view of Kim further in view of Lin et al. US 20210202418 A1 (hereinafter Lin)
Regarding claim 8, Kweon in view of Kim teaches the limitations of claim 1, as discussed above.
Kweon does not teach:
upper surfaces of the first bonding pads exposed by the first passivation layer and upper surfaces of the first dummy patterns are on a same plane, and upper surfaces of the second bonding pads exposed by the second passivation layer and upper surfaces of the second dummy patterns are on a same plane.
Lin teaches:
upper surfaces of the first bonding pads exposed by the first passivation layer and upper surfaces of the first dummy patterns are on a same plane, and upper surfaces of the second bonding pads exposed by the second passivation layer and upper surfaces of the second dummy patterns are on a same plane.
(FIG 1C, FIG 2, paragraph [0010], claim 1,4)
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to substitute Lin’s dummy structure to Kweon’s semiconductor device to improve manufacturing yield, structural integrity, and physical reliability.
Regarding claim 18, Kweon in view of Kim teaches the limitations of claim 11, as discussed above. And further in review with Lin et al. US 20210202418 A1 (hereinafter Lin) teaches the limitation of claim 18
Kweon does not teach:
upper surfaces of the first bonding pads exposed by the first passivation layer and upper surfaces of the first dummy patterns are on a same plane, and upper surfaces of the second bonding pads exposed by the second passivation layer and upper surfaces of the second dummy patterns are on a same plane.
Lin teaches:
upper surfaces of the first bonding pads exposed by the first passivation layer and upper surfaces of the first dummy patterns are on a same plane, and upper surfaces of the second bonding pads exposed by the second passivation layer and upper surfaces of the second dummy patterns are on a same plane.
(FIG 1C, FIG 2, paragraph [0010], claims 1,4.)
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to substitute Lin’s dummy structure to Kweon’s semiconductor device to improve manufacturing yield, structural integrity, and physical reliability.
Claims 9 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kweon in view of Kim further in view of Takada US 20140246780 A1 (hereinafter Takada)
Regarding claim 9, Kweon in view of Kim teaches the limitations of claim 1, as discussed above.
Kweon does not teach:
the first substrate structure further comprises a plurality of third dummy patterns in the first passivation layer in the first die region, and the second substrate structure further includes a plurality of fourth dummy patterns in the second passivation layer in the second die region.
Takada teaches:
the first substrate structure further comprises a plurality of third dummy patterns in the first passivation layer in the first die region, and the second substrate structure further includes a plurality of fourth dummy patterns in the second passivation layer in the second die region. (Claim 1, line 13)
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to substitute Takada’s dummy structure to Kweon’s semiconductor device to improve manufacturing yield, structural integrity, and physical reliability.
Regarding claim 19, Kweon in view of Kim teaches the limitations of claim 11, as discussed above.
Kweon does not teach:
the first substrate structure further comprises a plurality of third dummy patterns in the first passivation layer in the first die region, and the second substrate structure further includes a plurality of fourth dummy patterns in the second passivation layer in the second die region.
Takada teaches:
the first substrate structure further comprises a plurality of third dummy patterns in the first passivation layer in the first die region, and the second substrate structure further includes a plurality of fourth dummy patterns in the second passivation layer in the second die region. (Claim 1, line 13.)
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to substitute Takada’s dummy structure to Kweon’s semiconductor device to improve manufacturing yield, structural integrity, and physical reliability.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kweon in view of Kim further in view of Takada US 20140246780 A1 (hereinafter Takada)
Regarding claim 10, Kweon in view of Kim teaches the limitations of claim 1, as discussed above.
Kweon does not teach:
the first substrate includes a core region in which sense amplifiers and sub-word line drivers are provided, and the second substrate includes a memory cell array region in which memory cells are provided.
Ku teaches:
the first substrate includes a core region in which sense amplifiers and sub-word line drivers are provided, and the second substrate includes a memory cell array region in which memory cells are provided. (paragraph [0008], line 3-17)
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to substitute Ku’s sense amplifiers, sub-word line drivers, and memory cells to complete needed functions.
Citation of Pertinent Art
Kweon, et al. US 12512429 B2
Kim, et al. US 12431195 B2
Dunton, et al. US 6319836 B1
Yang, et al. US 20220208727 A1
Watanuki et al. US 20170068051 A1
Lin et al. US 20210202418 A1
Takada US 20140246780 A1
Ku et al. US 20230380173 A1
Conclusion
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/WEI LI/ Examiner, Art Unit 2899 /Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
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