Office Action Predictor
Last updated: April 16, 2026
Application No. 18/414,804

ELECTRONIC DEVICE

Final Rejection §102
Filed
Jan 17, 2024
Examiner
KARACSONY, ROBERT
Art Unit
2845
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Innolux Corporation
OA Round
2 (Final)
77%
Grant Probability
Favorable
3-4
OA Rounds
2y 10m
To Grant
93%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allow Rate
698 granted / 908 resolved
+8.9% vs TC avg
Strong +16% interview lift
Without
With
+16.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
24 currently pending
Career history
932
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
38.7%
-1.3% vs TC avg
§102
37.0%
-3.0% vs TC avg
§112
17.3%
-22.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 908 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KIM et al. (U.S. Publication No. 2019/0019758). KIM, in figure 2, discloses: Claim 1: An electronic device, comprising: a chip (30); a first insulating layer (20), surrounding to the chip and comprising a first portion (portion between 59 and 30) and a hole (hole of 59); a metal layer (52), overlapped the first insulating layer; a first conductive structure (59), disposed in the hole; a second insulating layer (18), surrounding to the chip (18p1), comprising a second portion, and surrounded by the first insulating layer (fig. 2); wherein the chip is electrically connected to the metal layer through the first conductive structure (fig. 2), wherein in a cross-sectional view: the first portion is disposed between the second portion and the first conductive structure (fig. 2); the second portion is interposed between the first portion and the chip (fig. 2); and the first portion has a first width, the second portion has a second width, and the first width is greater than the second width (fig. 2). Claim 2: wherein the metal layer is higher than the chip along a thickness direction of the first insulating layer (fig. 2). Claim 3: wherein the second insulating layer is disposed between the first insulating layer and the metal layer (fig. 2). Claim 4: wherein a thickness of the second insulating layer is different from a thickness of the first insulating layer (fig. 2). Claim 5: further comprising: a line (14a), electrically connected between the chip and the first conductive structure. Claim 6: further comprising: a second conductive structure (53), disposed under the chip. Claim 7: wherein the first conductive structure is higher than the second conductive structure along a thickness direction of the first insulating layer (fig. 2). Response to Arguments Applicant’s arguments with respect to claim(s) 1-7 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERT KARACSONY whose telephone number is (571)270-1268. The examiner can normally be reached 9:00 am - 5:00 pm, Monday - Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dimary Lopez can be reached at (571) 270-7893. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Robert Karacsony/ Primary Examiner, Art Unit 2845
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Prosecution Timeline

Jan 17, 2024
Application Filed
Jun 14, 2025
Non-Final Rejection — §102
Aug 27, 2025
Response Filed
Feb 07, 2026
Final Rejection — §102
Mar 29, 2026
Request for Continued Examination
Mar 31, 2026
Response after Non-Final Action

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
77%
Grant Probability
93%
With Interview (+16.3%)
2y 10m
Median Time to Grant
Moderate
PTA Risk
Based on 908 resolved cases by this examiner. Grant probability derived from career allow rate.

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