DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/20/2026 has been entered.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
In re to claim 7, method claim 7 are rejected based on the following case law, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device inherently performs the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed Cir. 1986). Therefore the previous rejections based on the apparatus will not be repeated.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 and 7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated Gurlahosur US 10511226 .
Regarding Claims 1 and 7, Gurlahosur teaches (Figures 1-7) a switch converter (Fig. 1), comprising: a master switching stage (102) comprising a master primary switch (502), a master secondary switch (504), a master power inductor (118a), a master controller (112a-114a and 154) wherein the master switching stage is operable to receive a Direct Current (DC) input voltage (Vin) and wherein the master controller is configured to: open and close the master primary switch and the master secondary switch to generate a master ripple current (on and off times of the switches produce IL) from the DC input voltage through the master power inductor (118a); a slave switching stage (104) comprising a slave primary switch (506), a slave secondary switch (508), a slave power inductor (118b), a slave controller (112b-114b) wherein the slave switching stage is operable to receive the DC input voltage (Vin) and wherein the slave controller is configured to: open and close the slave primary switch and the slave secondary switch (controlling 506-508) to generate a slave ripple current (IL of 104) from the DC input voltage through the slave power inductor (118b); and a multiphase controller (110 and 124) configured to : generate a ramp voltage (VRAMP) based on the opening and closing of the master primary switch and the master secondary switch (with PWM at 110a) and operate with the slave switch controller (112b and 114b) such that a phase between the master ripple current (144a) and the slave ripple current (144b) is set in response to a reference voltage level (Vshare) being set relative to the ramp voltage (with Isteer which changes the value of the Vramp see fig. 2). (For Example: Col. 5 lines 50-67, Col. 8 lines 38-67 and Col. 9)
Regarding Claim 2 , Gurlahosur teaches (Figures 1-7) wherein: the master power inductor (118a) and the slave power inductor (118b) are coupled to inject the master ripple current and the slave ripple current (Isense) into an output node (at the output), wherein a DC output voltage (Vout) is generated at the output node . (For Example: Col. 4 lines 21-36)
Regarding Claim 3, Gurlahosur teaches (Figures 1-7)wherein a power capacitor (120) is coupled in shunt to the output node.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gurlahosur US 10511226 in view of Xu US 2019/0190279.
Regarding Claim 4, Gurlahosur teaches (Figures 1-7) a switch converter (at fig. 10), comprising: a master switching stage (1st phase) comprising a master primary switch (502), a master secondary switch (504), and a master power inductor (118a), wherein the master switching stage is operable to receive a Direct Current (DC) input voltage (Vin) and wherein a master controller (112a-114a and 154) is configured to: open and close the master primary switch and the master secondary switch (502-504) to generate a master ripple current (IL) from the DC input voltage through the master power inductor (118a); a slave switching stages (104), for each slave switching stage of the slave switching stages (For Example: Col. 4 lines 21-36), the slave switching stage is configured to: generate a different slave ripple current (IL for each phase) for the slave switching stage (104) from the DC input voltage (Vin). (For Example: Col. 5 lines 50-67, Col. 8 lines 38-67 and Col. 9)
Gurlahosur does not teach a multiphase controller configured to: generate a ramp voltage based on the opening and closing of the master primary switch and the master secondary switch; and operate with each of the slave switching stages such that a different phase between the master ripple current and the slave ripple current is set for each of the slave switching stages, wherein the phase of the slave switching stage of each of the slave switching stages is in response to a different reference voltage level for each of the slave switching stages being set relative to the ramp voltage.
Xu teaches (Figures 10-11) a multiphase controller (507) configured to: generate a ramp voltage (VR) based on the opening and closing of the master primary switch and the master secondary switch (with PWM1); and operate with each of the slave switching stages (bottom 3 phases) such that a different phase between the master ripple current and the slave ripple current is set for each of slave switching stages (see fig. 11 with PWM2-4), wherein the phase of the slave switching stage of each of the slave switching stages is in response to a different reference voltage level (with 581-583) for each of the slave switching stages being set relative to the ramp voltage(VR) . (For Example: Par. 62-69)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Gurlahosur to a multiphase controller configured to: generate a ramp voltage based on the opening and closing of the master primary switch and the master secondary switch; and operate with each of the slave switching stages such that a different phase between the master ripple current and the slave ripple current is set for each of the slave switching stages, wherein the phase of the slave switching stage of each of the slave switching stages is in response to a different reference voltage level for each of the slave switching stages being set relative to the ramp voltage, as taught by Xu to provide a stable output signal to the load.
Regarding Claim 5, Gurlahosur teaches (Figures 1-7) wherein: the master power inductor (118a) and the slave power inductor (118b) are coupled to inject the master ripple current and the slave ripple current (Isense) into an output node (at the output), wherein a DC output voltage (Vout) is generated at the output node . (For Example: Col. 4 lines 21-36)
Regarding Claim 6, Gurlahosur teaches (Figures 1-7)wherein a power capacitor (120) is coupled in shunt to the output node.
Response to Arguments
Applicant’s arguments with respect to the claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO A ROSARIO-BENITEZ whose telephone number is (571)270-7888. The examiner can normally be reached M-F 9AM-5PM.
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/GUSTAVO A ROSARIO-BENITEZ/Primary Examiner, Art Unit 2838
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