DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Remark(s)
Applicant's amendment filed June 15th, 2026 have been fully entered and considered. Regarding the arguments to the previous 101 rejection, the examiner finds the 101 argument to be persuasive, regarding the prior art 102 and 103 rejections, the examiner respectfully finds the arguments to be non-persuasive, see response to remarks section below for more details. Accordingly, this action is made final.
Status of Claims
Claims 1-20 are pending and claims 1-20 remains rejected.
Response to Argument(s)
Regarding the Applicants’ argument to the 101 rejection:
In pages 6-8 of the Applicants made remarks about arguments for the 101 rejection, with the Applicants’ statement regarding the improvement reflected in the claimed invention, the examiner finds them to be persuasive and that the 101 rejection has been withdrawn, that independent claims 1, 7 and 14 are directed to semiconductor-manufacturing process-control technology that operates on measured physical water-feature and uses the resulting prediction to control, disposition, indicate rework for, or rework wafers in a semiconductor manufacturing process.
Regarding the Applicants’ argument to the 102 prior art rejections:
In pages 8-10 of the Applicants’ remarks, the Applicants argue that the proposed Vajaria (previously used as a prior art in the 102 rejections) does not teach or suggest the features of the claims:
“corresponding physical characteristics of a plurality of semiconductor features on a plurality of wafers” in the dependent claims.
And likewise, Vajaria does not teach or suggest that the corresponding physical characteristics include “corresponding dimensions and corresponding positions”.
In support of the above argument, the Applicants state that the Office Action’s mapping of Vajaria’s received wafer images, die inspection results, and image-derived metrics to the claimed physical-characteristic measurement is not supported in the reference, since Vajaria’s inspection results may identify pass/fail conditions and reasons for failure such as alignment, focus, critical dimension, or overlay, thus Vajaria’s inspection results are input labels used to train or select image-statistic combinations, and calculated metrics are statistics of masked image data, such as intensity, symmetry, frequency, gradient means, and gradient standard deviations hence, Vajaria does not disclose semiconductor features across a plurality of wafers, nor does it disclose estimating the claimed mean and variance from those physical feature measurements. And that Vajaria’s disclosure of segment masks, masked die images, and image-intensity or gradient statistics is technically different from that claimed physical metrology of corresponding semiconductor-feature dimensions and positions.
Examiner’s reply:
The examiner respectfully disagrees with the Applicants’ arguments; the Applicants are reminded that the claims are construed based on BRI (broadest reasonable interpretation) in light of the specification. As in Applicants’ own remarks to affirm that Vajaria’s inspection result include an indication of pass/fail and reason for such pass/fail such as critical dimension indicating but a physical characteristic? and other characteristics such as focus, alignment, or overlay which are for each wafer image of a plurality of wafer images obtained during a manufacturing process and Vajaria teaches the discussed limitation of “corresponding dimensions and corresponding positions” as taught in Par. [0023] discloses compliance inspection for a plurality of wafers for semiconductor production based on receiving wafer images based on die alignment, fidelity, focus, reticle tilt, dimensions, etc., and Par. [0024] discloses the physical characteristics, as discussed above, to include dimension of the dies of the wafers, and alignment, overlay, tilt (characteristics that indicates positioning/positions). Furthermore, the examiner finds the limitation “corresponding physical characteristics of a plurality of semiconductor features on a plurality of wafers” to fall within the scope of Vajaria, particularly, the inspection results are obtained through monitoring and/or sampling according to Vajaria’s Par. [0004] of “manufacturing process control is typically performed based on low wafer sampling using a slow, but sensitive, inspection tool” indicating a sampling/measuring step to obtain the inspection results. The claimed invention does not exclude that inspection results cannot be an indication or label, therefore, the examiner finds the Applicants’ argument to be incommensurate with the scope of the claim, even Vajaria’s inspection results are indication of pass/fail condition and reasons for pass/fail indicating some conditions of the physical characteristics, they still are information/data including physical characteristics of the wafers. Therefore, Vajaria teaches the discussed limitation of “corresponding physical characteristics of a plurality of semiconductor features on a plurality of wafers” for the independent claims 1, 7 and 14.
Furthermore, Vajaria teaches the following limitations of “estimating a mean and a variance using the corresponding physical characteristics” wherein Vajaria’s Par. [0027] discloses “an intensity-based mask may be determined by first identifying a die having a mean intensity—the mean die. Next an intensity histogram of the mean die is determined and used to derive …other dynamic schemes can adapt naturally to the density and response of the structure” being the metric used in the processing, wherein Par. [0043] disclose “one or more statistically significant combinations of metric, segment mask, and wafer image based on the die inspection results” indicating the metric including the mean intensity is based on the use of information/data regarding the inspection results. Furthermore, these metrics also indicate variance across the wafer image according to Par. [0050] of “the first significant combination (SD-based mask and intensity-based metric) shows a variance across the wafer image”; and the limitation of “predicting manufacturing variation of the semiconductor manufacturing process using the mean and the variance” wherein, Vajaria’s Par. [0044] discloses “a result wafer image for each combination of wafer image, segment mask, and metric. Each generated result wafer image comprises a set of result die images based on the corresponding combination…certain result wafer images may depict variations in the wafer that are different than the variations depicted other result images” indicating predicting the variation based on the significant combination of metrics/the inspection results. Therefore, Vajaria teaches the discussed limitation of “predicting manufacturing variation of the semiconductor manufacturing process using the mean and the variance” for the independent claims 1, 7 and 14.
Therefore, the 102 rejections remain.
Regarding the Applicants’ argument to the 103 prior art rejections:
In pages 10-11 of the Applicants’ remarks, the Applicants argue that the proposed prior arts, since Vajaria does not teach the limitation as mentioned in the argument above for the 102 rejection, therefore, the 103 rejections of the corresponding dependent claims should be withdrawn.
With the examiner’ reply and explanation of disagreement to the Applicants’ argument, the examiner respectfully find the proposed prior arts to still teach the claimed limitations, therefore, the 103 rejections also remain. See 103 rejections section below for more details
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 7-12, 14 and 17-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Himanshu Vajaria et. al. (“US 2016/0371826 A1” hereinafter as “Vajaria”).
Regarding claim 1, Vajaria discloses a method, comprising: measuring corresponding physical characteristics of a plurality of semiconductor features on a plurality of wafers produced using a semiconductor manufacturing process ([0023] discloses compliance inspection for a plurality of wafers for semiconductor production based on receiving wafer images based on die alignment, fidelity, focus, reticle tilt, dimensions, etc. according to [0024] these are analogous to physical characteristics); estimating a mean and a variance using the corresponding physical characteristics ([0027] discloses a mean intensity is estimated based on the physical characteristic of the die, together with the determination of the variance according to [0029]); predicting manufacturing variation of the semiconductor manufacturing process using the mean and the variance ([0044] discloses basing on the mean and the variance metrics to predict variations of the wafers/semiconductor during its manufacturing process); and controlling or dispositioning the semiconductor manufacturing process using the predicted manufacturing variation (“or” indicates a selection, only one of these options is the instant scope of the limitation, the examiner selects “controlling” which is disclosed in [0055] wherein basing on the variation predicted to determine rework or scrap of the wafers, capable of routing wafers).
Regarding claim 2, Vajaria discloses the method of claim 1, wherein controlling the semiconductor manufacturing process includes adjusting a lithography tool used in the semiconductor manufacturing process ([0007] discloses control monitoring of the monitoring process for lithography, therefore, in [0055] where it discloses the controlling step, it can be understood to adjust the lithography tool used during the monitoring process for the control monitoring which is further disclosed in [0024]).
Regarding claim 3, Vajaria discloses the method of claim 1, wherein the corresponding physical characteristics includes corresponding dimensions of the plurality of semiconductor features and corresponding positions of the plurality of semiconductor features ([0024] discloses the physical characteristics, as discussed above, to include dimension of the dies of the wafers, and alignment, overlay, tilt [characteristics that indicates positioning/positions]).
Regarding claim 4, Vajaria discloses the method of claim 1, wherein predicting manufacturing variation of the semiconductor manufacturing process using the mean and the variance (as discussed above in claim 1) includes combining the mean and the variance (as discussed above in claim 1, the predicting of the variation of the semiconductor includes the use of the determined mean and the variance, in other words, they are being used in combination, further disclosed in [0050], wherein the prediction is based on the combination of PCA-based mask and gradient-based metric as being the mean according to [0034] and the variance in the PCA-based mask).
Regarding claim 7, Vajaria discloses an apparatus, comprising: a measurement device configured to measure corresponding physical characteristics of a plurality of semiconductor features on a plurality of wafers produced using a semiconductor manufacturing process to generate measurement data ([0023] discloses compliance inspection for a plurality of wafers for semiconductor production based on receiving wafer images based on die alignment, fidelity, focus, reticle tilt, dimensions, etc. according to [0024] these are analogous to physical characteristics [further analogous to the measurement data as recited, which is obtained using camera or imaging sensor according to 0048 which is analogous to the recited measurement device]); and an information system configured to: estimate a mean and a variance using the measurement data ([0027] discloses a mean intensity is estimated based on the physical characteristic of the die, together with the determination of the variance according to [0029] using a computer according to [0048] which is analogous to the recited information system); predict manufacturing variation of the semiconductor manufacturing process using the mean and the variance ([0044] discloses basing on the mean and the variance metrics to predict variations of the wafers/semiconductor during its manufacturing process); and generate, using predicted manufacturing variation, an indication to rework at least one wafer of the plurality of wafers ([0055] wherein basing on the variation predicted to determine rework or scrap of the wafers, capable of routing wafers including rework [according to 0055]).
Regarding claim 8, Vajaria discloses the apparatus of claim 7, wherein the information system is further configured to generate control signals for the least one tool used in the semiconductor manufacturing process in response to a generation of the indication to rework the at least one wafer of the plurality of wafers ([0055] discloses the transport state to control the routing wafers for rework which indicates a transporting of the signals for controlling and monitoring of the production process such as recited in [0004], in other words, when the wafer is up for rework, the system transport for reworking with the computer sending signals for the programmed processor to execute such instructions to the machine).
Regarding claim 9, Vajaria discloses the apparatus of claim 8, wherein the at least one tool includes a lithography tool ([0024] discloses the system includes a lithography module/tool).
Regarding claim 10, Vajaria discloses the apparatus of claim 8, wherein the at least one tool includes an etch tool ([0002] discloses the system includes an etch tool).
Regarding claim 11, Vajaria discloses the method of claim 7, wherein the corresponding physical characteristics includes corresponding dimensions of the plurality of semiconductor features and corresponding positions of the plurality of semiconductor features ([0024] discloses the physical characteristics, as discussed above, to include dimension of the dies of the wafers, and alignment, overlay, tilt [characteristics that indicates positioning/positions]).
Regarding claim 12, Vajaria discloses the apparatus of claim 7, wherein to predict the manufacturing variation of the semiconductor manufacturing process, the information system is further configured to combine the mean and the variance (as discussed above in claim 7, the predicting of the variation of the semiconductor includes the use of the determined mean and the variance, in other words, they are being used in combination, further disclosed in [0050], wherein the prediction is based on the combination of PCA-based mask and gradient-based metric as being the mean according to [0034] and the variance in the PCA-based mask).
Regarding claim 14, Vajaria discloses a tangible non-transitory computer-readable storage medium having program instructions stored therein that, in response to execution by a computer system, causes the computer system to perform operations comprising ([0048] discloses the processing includes the use of a computer which indicates the use of a non-transitory computer-readable storage medium such as a RAM or ROM): a method, comprising: measuring corresponding physical characteristics of a plurality of semiconductor features on a plurality of wafers produced using a semiconductor manufacturing process ([0023] discloses compliance inspection for a plurality of wafers for semiconductor production based on receiving wafer images based on die alignment, fidelity, focus, reticle tilt, dimensions, etc. according to [0024] these are analogous to physical characteristics); estimating a mean and a variance using the corresponding physical characteristics ([0027] discloses a mean intensity is estimated based on the physical characteristic of the die, together with the determination of the variance according to [0029]); predicting manufacturing variation of the semiconductor manufacturing process using the mean and the variance ([0044] discloses basing on the mean and the variance metrics to predict variations of the wafers/semiconductor during its manufacturing process); and reworking at least one wafer of the plurality of wafers based on the manufacturing variation ([0055] wherein basing on the variation predicted to determine rework or scrap of the wafers, capable of routing wafers including rework [according to 0055]).
Regarding claim 17, Vajaria discloses the tangible non-transitory computer-readable storage medium of claim 14, wherein the corresponding physical characteristics includes corresponding dimensions of the plurality of semiconductor features and corresponding positions of the plurality of semiconductor features ([0024] discloses the physical characteristics, as discussed above, to include dimension of the dies of the wafers, and alignment, overlay, tilt [characteristics that indicates positioning/positions]).
Regarding claim 18, Vajaria discloses the tangible non-transitory computer-readable storage medium of claim 14, wherein predicting manufacturing variation of the semiconductor manufacturing process using the mean and the variance includes combining the mean and the variance (as discussed above in claim 1, the predicting of the variation of the semiconductor includes the use of the determined mean and the variance, in other words, they are being used in combination, further disclosed in [0050], wherein the prediction is based on the combination of PCA-based mask and gradient-based metric as being the mean according to [0034] and the variance in the PCA-based mask).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 5, 13 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Himanshu Vajaria et. al. (“US 2016/0371826 A1” hereinafter as “Vajaria”)in view of Robert R. Sokal et. al. (“Significance Tests for Coefficients of Variation and Variability Profiles, March 1980, Systematic Biology, Vol. 29, Issue 1, pp. 50-66” hereinafter as “Sokal”).
Regarding claim 5, Vajaria discloses the method of claim 4, wherein combining the mean and the variance (as discussed above in claim 1).
However, Vajaria does not explicitly disclose includes generating a quotient of the mean and the variance, and wherein predicting the manufacturing variation includes generating a prediction using a mathematical function and the quotient of the mean and the variance.
In the same field of variability determination (title, Sokal) Sokal discloses includes generating a quotient of the mean and the variance (page 63, “Appendix A” discloses the formula for coefficient of variation which includes a quotient of the mean and the variance which is used for determination of variability including using of standard deviation; which can be used in Vajaria as the standard deviation divided by the mean and the variance), and wherein predicting the manufacturing variation includes generating a prediction using a mathematical function and the quotient of the mean and the variance (as discussed previously, the formula of
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which is a mathematical formula and the quotient of the mean and the variance).
Thus, it would have been obvious for a person of ordinary skill in the art before the effective filing date to modify Vajaria to perform combining the mean and the variance includes generating a quotient of the mean and the variance, and wherein predicting the manufacturing variation includes generating a prediction using a mathematical function and the quotient of the mean and the variance as taught by Sokal to arrive at the claimed invention discussed above. Such a modification is the result of combing prior art elements according to known methods to yield predictable results. The motivation for the proposed modification would have been to detect variability more efficiently (abstract, Sokal).
Regarding claim 13, Vajaria discloses the apparatus of claim 7, wherein to combine the mean and the variance, the information system (as discussed above in claim 7).
However, Vajaria does not explicitly disclose is further configured to generate a quotient of the mean and the variance, and wherein the information system is further configured to generate a prediction using a mathematical function and the quotient of the mean and the variance.
In the same field of variability determination (title, Sokal) Sokal discloses further configured to generate a quotient of the mean and the variance (page 63, “Appendix A” discloses the formula for coefficient of variation which includes a quotient of the mean and the variance which is used for determination of variability including using of standard deviation; which can be used in Vajaria as the standard deviation divided by the mean and the variance), and wherein the information system is further configured to generate a prediction using a mathematical function and the quotient of the mean and the variance (as discussed previously, the formula of
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which is a mathematical formula and the quotient of the mean and the variance).
Thus, it would have been obvious for a person of ordinary skill in the art before the effective filing date to modify Vajaria to perform combining the mean and the variance includes generating a quotient of the mean and the variance, and wherein predicting the manufacturing variation includes generating a prediction using a mathematical function and the quotient of the mean and the variance as taught by Sokal to arrive at the claimed invention discussed above. Such a modification is the result of combing prior art elements according to known methods to yield predictable results. The motivation for the proposed modification would have been to detect variability more efficiently (abstract, Sokal).
Regarding claim 19, Vajaria discloses the tangible non-transitory computer-readable storage medium of claim 18, wherein combining the mean and the variance (as discussed above in claim 18).
However, Vajaria does not explicitly disclose includes generating a quotient of the mean and the variance, and wherein predicting the manufacturing variation includes generating a prediction using a mathematical function and the quotient of the mean and the variance.
In the same field of variability determination (title, Sokal) Sokal discloses includes generating a quotient of the mean and the variance (page 63, “Appendix A” discloses the formula for coefficient of variation which includes a quotient of the mean and the variance which is used for determination of variability including using of standard deviation; which can be used in Vajaria as the standard deviation divided by the mean and the variance), and wherein predicting the manufacturing variation includes generating a prediction using a mathematical function and the quotient of the mean and the variance (as discussed previously, the formula of
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168
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which is a mathematical formula and the quotient of the mean and the variance).
Thus, it would have been obvious for a person of ordinary skill in the art before the effective filing date to modify Vajaria to perform combining the mean and the variance includes generating a quotient of the mean and the variance, and wherein predicting the manufacturing variation includes generating a prediction using a mathematical function and the quotient of the mean and the variance as taught by Sokal to arrive at the claimed invention discussed above. Such a modification is the result of combing prior art elements according to known methods to yield predictable results. The motivation for the proposed modification would have been to detect variability more efficiently (abstract, Sokal).
Claims 6 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Himanshu Vajaria et. al. (“US 2016/0371826 A1” hereinafter as “Vajaria”)in view of H. T. Kim et. al. (“A Precise Inspection Technique for Wafer Pre-sawing Lines using Affine Transformation, Dec. 2008, 15th International Conference on Mechatronics and Machine Vision in Practice” hereinafter as “Kim”).
Regarding claim 6, Vajaria discloses the method of claim 1 (as discussed above in claim 1).
However, Vajaria does not explicitly disclose wherein the corresponding physical characteristics includes at least a vertical dimension of a cut feature included on a particular wafer of the plurality of wafers, and a vertical width of a horizontal line associated with the cut feature.
In the same field of wafer inspection (title and abstract, Kim), Kim discloses wherein the corresponding physical characteristics includes at least a vertical dimension of a cut feature included on a particular wafer of the plurality of wafers, and a vertical width of a horizontal line associated with the cut feature (section II.A, 1st par., discloses the edges includes features in vertical and horizon directions, the edges can be understood to be cut feature as claimed, by BRI, of the region of the rectangle oriented hence indicates width and lines).
Thus, it would have been obvious for a person of ordinary skill in the art before the effective filing date to modify Vajaria to perform determining of physical characteristics wherein the corresponding physical characteristics includes at least a vertical dimension of a cut feature included on a particular wafer of the plurality of wafers, and a vertical width of a horizontal line associated with the cut feature as taught by Kim to arrive at the claimed invention discussed above. Such a modification is the result of combing prior art elements according to known methods to yield predictable results. The motivation for the proposed modification would have been to determine variability in wafer production effectively (abstract and section II.A, 1st par., Kim).
Regarding claim 20, Vajaria discloses the tangible non-transitory computer-readable storage medium of claim 14 (as discussed above in claim 20).
However, Vajaria does not explicitly disclose wherein the corresponding physical characteristics includes at least a vertical dimension of a cut feature included on a particular wafer of the plurality of wafers, and a vertical width of a horizontal line associated with the cut feature.
In the same field of wafer inspection (title and abstract, Kim), Kim discloses wherein the corresponding physical characteristics includes at least a vertical dimension of a cut feature included on a particular wafer of the plurality of wafers, and a vertical width of a horizontal line associated with the cut feature (section II.A, 1st par., discloses the edges includes features in vertical and horizon directions, the edges can be understood to be cut feature as claimed, by BRI, of the region of the rectangle oriented hence indicates width and lines).
Thus, it would have been obvious for a person of ordinary skill in the art before the effective filing date to modify Vajaria to perform determining of physical characteristics wherein the corresponding physical characteristics includes at least a vertical dimension of a cut feature included on a particular wafer of the plurality of wafers, and a vertical width of a horizontal line associated with the cut feature as taught by Kim to arrive at the claimed invention discussed above. Such a modification is the result of combing prior art elements according to known methods to yield predictable results. The motivation for the proposed modification would have been to determine variability in wafer production effectively (abstract and section II.A, 1st par., Kim).
Claims 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Himanshu Vajaria et. al. (“US 2016/0371826 A1” hereinafter as “Vajaria”)in view of Garry Tuohy (“Excursion Wafer Loss Prediction by Local Density Segmentation, October 2016, IEEE Transactions on Semiconductor Manufacturing, Vol. 29, Issue 4” hereinafter as “Tuohy”).
Regarding claim 15, Vajaria discloses the tangible non-transitory computer-readable storage medium of claim 14, wherein predicting the manufacturing variation (as discussed above in claim 14).
However, Vajaria does not explicitly disclose includes determining a proportion of manufacturing excursions.
In the same field of wafer inspection (title and abstract, Touhy), Touhy discloses includes determining a proportion of manufacturing excursions (section VI. 2nd par., discloses the variation/defect detection includes determining a proportion of manufacturing excursions of the wafer production process).
Thus, it would have been obvious for a person of ordinary skill in the art before the effective filing date to modify Vajaria to perform predicting the manufacturing variation includes determining a proportion of manufacturing excursions as taught by Touhy to arrive at the claimed invention discussed above. Such a modification is the result of combing prior art elements according to known methods to yield predictable results. The motivation for the proposed modification would have been to detect variation in wafer for manufacturing more effectively (abstract, section VI. 2nd par., Touhy).
Regarding claim 16, Vajaria discloses the tangible non-transitory computer-readable storage medium of claim 14, wherein reworking the at least one wafer of the plurality of wafers (as discussed above in claim 14).
However, Vajaria does not explicitly disclose includes comparing the proportion of manufacturing excursions to a threshold value.
In the same field of wafer inspection (title and abstract, Touhy), Touhy discloses includes comparing the proportion of manufacturing excursions to a threshold value (section VI. 2nd par., discloses the variation detection includes determining a proportion of manufacturing excursions of the wafer production process; which is further discloses in section II, 1st par., wherein the proportion of manufacturing excursions is being compared to a threshold to determine the variation/defects).
Thus, it would have been obvious for a person of ordinary skill in the art before the effective filing date to modify Vajaria to perform predicting the manufacturing variation includes comparing the proportion of manufacturing excursions to a threshold value as taught by Touhy to arrive at the claimed invention discussed above. Such a modification is the result of combing prior art elements according to known methods to yield predictable results. The motivation for the proposed modification would have been to detect variation in wafer for manufacturing more effectively (abstract, section VI. 2nd par., Touhy).
Pertinent Prior Art(s)
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Ikeda, Takahiro, “US 20020097913 A1”, discloses a pattern evaluation method includes: scanning an object to be measured on which a pattern has been formed with an energy beam and obtaining an image data of the object by detecting a scattered particle which is produced from the object; recognizing at least one edge of the pattern on the basis of the image data and calculating the coordinate positions of each edge point of a sequence of edge points constituting the shape of the edge of the pattern; deriving a straight line so that the sum of lengths of perpendiculars drawn from the edge points to the straight line is minimum; and statistically processing the lengths of perpendiculars when the straight line is derived and outputting evaluation information for quantitatively expressing roughness of the edge of the pattern.
Strang, Eric J., “US 20050071037 A1”, discloses A method, system and computer readable medium for analyzing a process performed by a semiconductor processing tool. The method includes inputting data relating to a process performed by the semiconductor processing tool, and inputting a first principles physical model relating to the semiconductor processing tool. First principles simulation is performed using the input data and the physical model to provide a first principles simulation result; and the first principles simulation result is used to determine a fault in the process performed by the semiconductor processing tool.
Zafar; Khurram, “US 20070288219 A1”, discloses various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium.
SU; Jing, “US 20200050099 A1”, discloses a method including: obtaining a portion of a design layout; determining characteristics of assist features based on the portion or characteristics of the portion; and training a machine learning model using training data including a sample whose feature vector includes the characteristics of the portion and whose label includes the characteristics of the assist features. The machine learning model may be used to determine characteristics of assist features of any portion of a design layout, even if that portion is not part of the training data.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHUONG HAU CAI whose telephone number is (571)272-9424. The examiner can normally be reached M-F 8:30 am - 5:00pm.
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/PHUONG HAU CAI/Examiner, Art Unit 2673
/CHINEYERE WILLS-BURNS/Supervisory Patent Examiner, Art Unit 2673
