DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6-10, 14-23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (US 2023/0253351 A1 hereinafter referred to as "Wang").
With respect to claim 1, Wang discloses, in Figs.1-15B, a three-dimensional integrated circuit configuration comprising: a first die (20A); a second die (50, 20B) configured with second die back side metallization (120B) (see Par.[0055]-[0056] wherein the second integrated circuit package 200 is formed by bonding a second integrated circuit device 50 to the first integrated circuit device 20, for example, provided in FIG. 2; the second integrated circuit package 200 is formed by attaching a second integrated circuit device 50 (e.g., a die or a chiplet) to the first integrated circuit device 20; the second integrated circuit device 50 may be a logic device (e.g., central processing unit (CPU), graphics processing unit (GPU), microcontroller, etc.), a memory device (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), a power management device (e.g., power management integrated circuit (PMIC) die), a radio frequency (RF) device, a sensor device, a micro-electro- mechanical-system (MEMS) device, a signal processing device (e.g., digital signal processing (DSP) die), a front-end device (e.g., analog front-end (AFE) dies), the like, or combinations thereof (e.g., a system- on-a-chip (SoC) die); see Par.[0065]-[0069] wherein a plurality of the first integrated circuit device 20A and 20B may be stacked before attaching the second integrated circuit device 50 or the carrier wafer 60; the front-side memory arrays (e.g., the front-side memory elements 36A/B and corresponding devices in the device layers 26A/B) and the back-side memory array (e.g., the back-side memory elements 126A/B and corresponding devices in the device layers 26A/B) are non-volatile memories; as illustrated, all of the devices in the plurality of the first integrated circuit devices 20A and 20B may include both of the front- side memory arrays (e.g., the front-side memory elements 36A and 36B) and the back-side memory arrays (e.g., the back-side memory elements 126A and 126B); any of the front-side interconnect structures 30A and 30B and/or the back-side interconnect structures 120A and 120B may be formed without the corresponding memory elements 36A/B and/or 126A/B); and the second die (50, 20B) configured to provide power from the second die back side metallization (120B) to the first die (20A) by way of second die (26B, 36B) back side pass-through vias formed in dummy cells (47) interspersed among second die (50, 20B) active logic cells (see Par.[0031]-[0035] wherein the second bonding layer 46 and the third conductive features 47 may be formed using either same or different methods and/or materials as forming the first bonding layer 44 and the second conductive features 45; see Par.[0040] wherein the back-side interconnect structure 120 includes a back-side power delivery network to provide the means of delivering power and other external connectivity to the integrated circuit; the back-side memory elements 126 may include some of the fourth conductive features 124 as well as one or more other types of devices (e.g., capacitors, resistors, diodes, inductors, power lines, and/or the like); see Par.[0051] wherein the fourth conductive features 124 of the back-side interconnect structure 120 form the power delivery network (PDN) (e.g., including power rails, which provide high throughput current) for power and ground routing through the integrated circuit. The TSVs 90 formed through the substrate 22 may include TSVs 90A formed by, for example, a via-first process as well as TSVs 90B formed by, for example, a via-last process; the TSVs 90A may also be referred to as buried rails and may be configured to delivery power or ground voltages to the device layer 26 and/or the front-side interconnect structure 30; see Par.[0016] wherein the devices formed over and in the device layer 26 as well as the subsequent processing, each completed first integrated circuit package 100 may be a logic device (e.g., central processing unit (CPU), graphics processing unit (GPU), microcontroller, etc.), a memory device (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), a power management device (e.g., power management integrated circuit (PMIC) die), a radio frequency (RF) device, a sensor device, a micro-electro-mechanical-system (MEMS) device, a signal processing device (e.g., digital signal processing (DSP) die), a front-end device (e.g., analog front-end (AFE) dies), the like, or combinations thereof (e.g., a system-on-a-chip (SoC) die)).
With respect to claim 2, Wang discloses, in Figs.1-15B, the three-dimensional integrated circuit configuration, wherein the first die (20A) is configured face down (see Par.[0011] wherein after attaching the carrier substrate or the second integrated circuit device, the structure may be flipped (i.e.; face down) over to fabricate a back-side portion of the first integrated circuit device, which may include a back-side power delivery network (PDN); see Par.[0036]-[0037], [0058] wherein the intermediate structure is flipped over to expose the TSVs 90 and for other subsequent processing; see Par.[0058] wherein after attaching the second integrated circuit device 50, the intermediate structure may be flipped over for subsequent processing, similarly as described above in connection with FIGS. 4-6; for example, the TSVs 90 may be formed over the back-side of the device layer 26 and the back-side interconnect structure 120 may be formed over the TSVs 90).
With respect to claim 3, Wang discloses, in Figs.1-15B, the three-dimensional integrated circuit configuration, wherein the first die (20A) is configured with first die back side metallization (120A) (see Par.[0069] wherein any of the front-side interconnect structures 30A and 30B and/or the back-side interconnect structures 120A and 120B may be formed without the corresponding memory elements 36A/B and/or 126A/B).
With respect to claim 4, Wang discloses, in Figs.1-15B, the three-dimensional integrated circuit configuration, further comprising a capacitor die configured face down on the first die (see Par.[0040] wherein the back-side memory elements 126 may include some of the fourth conductive features 124 as well as one or more other types of devices (e.g., capacitors, resistors, diodes, inductors, power lines, and/or the like); see Par.[0046] wherein the front-side memory elements 36 and the back-side memory elements 126 provide greater capacity for the memory arrays (e.g., a total number of memory devices of non-volatile memory) in the first integrated circuit package 100).
With respect to claim 6, Wang discloses, in Figs.1-15B, the three-dimensional integrated circuit configuration, wherein the first die (20A) is configured face up (see Par.[0065]-[0066] wherein in FIG. 12, a third integrated circuit package 300 may be formed by attaching the second integrated circuit device 50 or the carrier wafer 60 over a stack of multiple dies; the third integrated circuit package 300 may be formed by first forming the front-side interconnect structure 30 of the first integrated circuit device 20A, and then attaching the first integrated circuit device 20B using the methods described above (e.g., hybrid bonding) in connection with attaching the carrier wafer 60 and/or the second integrated circuit device 50).
With respect to claim 7, Wang discloses, in Figs.1-15B, the three-dimensional integrated circuit configuration, wherein the first die (20A) is configured with first die back side metallization (120A) (see Par.[0069] wherein any of the front-side interconnect structures 30A and 30B and/or the back-side interconnect structures 120A and 120B may be formed without the corresponding memory elements 36A/B and/or 126A/B).
With respect to claim 8, Wang discloses, in Figs.1-15B, the three-dimensional integrated circuit configuration, the second die (50, 20B) comprising multiple layers of interconnected front side fill metals (see Par.[0055]-[0056] wherein the second integrated circuit package 200 is formed by bonding a second integrated circuit device 50 to the first integrated circuit device 20, for example, provided in FIG. 2; the second integrated circuit package 200 is formed by attaching a second integrated circuit device 50 (e.g., a die or a chiplet) to the first integrated circuit device 20; the second integrated circuit device 50 may be a logic device (e.g., central processing unit (CPU), graphics processing unit (GPU), microcontroller, etc.), a memory device (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), a power management device (e.g., power management integrated circuit (PMIC) die), a radio frequency (RF) device, a sensor device, a micro-electro-mechanical-system (MEMS) device, a signal processing device (e.g., digital signal processing (DSP) die), a front-end device (e.g., analog front- end (AFE) dies), the like, or combinations thereof (e.g., a system-on-a-chip (SoC) die); see Par.[0065]- [0069] wherein a plurality of the first integrated circuit device 20A and 20B may be stacked before attaching the second integrated circuit device 50 or the carrier wafer 60; the front-side memory arrays (e.g., the front-side memory elements 36A/B and corresponding devices in the device layers 26A/B) and the back-side memory array (e.g., the back-side memory elements 126A/B and corresponding devices in the device layers 26A/B) are non-volatile memories; as illustrated, all of the devices in the plurality of the first integrated circuit devices 20A and 20B may include both of the front-side memory arrays (e.g., the front-side memory elements 36A and 36B) and the back-side memory arrays (e.g., the back-side memory elements 126A and 126B).
With respect to claim 9, Wang discloses, in Figs.1-15B, the three-dimensional integrated circuit configuration, the second die configured with power gating cells interposed between the second die back side pass-through vias and second die front side metallization (see Par.[0031]-[0035] wherein the second bonding layer 46 and the third conductive features 47 may be formed using either same or different methods and/or materials as forming the first bonding layer 44 and the second conductive features 45; see Par.[0040] wherein the back-side interconnect structure 120 includes a back-side power delivery network to provide the means of delivering power and other external connectivity to the integrated circuit; the back-side memory elements 126 may include some of the fourth conductive features 124 as well as one or more other types of devices (e.g., capacitors, resistors, diodes, inductors, power lines, and/or the like); see Par.[0051] wherein the fourth conductive features 124 of the back-side interconnect structure 120 form the power delivery network (PDN) (e.g., including power rails, which provide high throughput current) for power and ground routing through the integrated circuit. The TSVs 90 formed through the substrate 22 may include TSVs 90A formed by, for example, a via-first process as well as TSVs 90B formed by, for example, a via-last process; the TSVs 90A may also be referred to as buried rails and may be configured to delivery power or ground voltages to the device layer 26 and/or the front-side interconnect structure 30; see Par.[0016] wherein the devices formed over and in the device layer 26 as well as the subsequent processing, each completed first integrated circuit package 100 may be a logic device (e.g., central processing unit (CPU), graphics processing unit (GPU), microcontroller, etc.), a memory device (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), a power management device (e.g., power management integrated circuit (PMIC) die), a radio frequency (RF) device, a sensor device, a micro-electro-mechanical-system (MEMS) device, a signal processing device (e.g., digital signal processing (DSP) die), a front-end device (e.g., analog front- end (AFE) dies), the like, or combinations thereof (e.g., a system-on-a-chip (SoC) die)).
With respect to claim 10, Wang discloses, in Figs.1-15B, the three-dimensional integrated circuit configuration, the second die configured with power conditioning cells interposed between the second die back side pass-through vias and second die front side metallization (see Par.[0031]-[0035] wherein the second bonding layer 46 and the third conductive features 47 may be formed using either same or different methods and/or materials as forming the first bonding layer 44 and the second conductive features 45; see Par.[0040] wherein the back-side interconnect structure 120 includes a back- side power delivery network to provide the means of delivering power and other external connectivity to the integrated circuit; the back-side memory elements 126 may include some of the fourth conductive features 124 as well as one or more other types of devices (e.g., capacitors, resistors, diodes, inductors, power lines, and/or the like); see Par.[0051] wherein the fourth conductive features 124 of the back-side interconnect structure 120 form the power delivery network (PDN) (e.g., including power rails, which provide high throughput current) for power and ground routing through the integrated circuit. The TSVs 90 formed through the substrate 22 may include TSVs 90A formed by, for example, a via-first process as well as TSVs 90B formed by, for example, a via-last process; the TSVs 90A may also be referred to as buried rails and may be configured to delivery power or ground voltages to the device layer 26 and/or the front-side interconnect structure 30; see Par.[0016] wherein the devices formed over and in the device layer 26 as well as the subsequent processing, each completed first integrated circuit package 100 may be a logic device (e.g., central processing unit (CPU), graphics processing unit (GPU), microcontroller, etc.), a memory device (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), a power management device (e.g., power management integrated circuit (PMIC) die), a radio frequency (RF) device, a sensor device, a micro-electro-mechanical-system (MEMS) device, a signal processing device (e.g., digital signal processing (DSP) die), a front-end device (e.g., analog front-end (AFE) dies), the like, or combinations thereof (e.g., a system-on-a-chip (SoC) die)).
With respect to claim 14, Wang discloses, in Figs.1-15B, a three-dimensional integrated circuit configuration comprising: a bottom die (20A) configured with bottom die back side metallization (120A) and bottom die front side metallization (30A); a top die (20B, 50) configured with metal layers (120B, 30B) adjacent to the bottom die front side metallization (30A) (see Par.[0055]-[0056] wherein the second integrated circuit package 200 is formed by bonding a second integrated circuit device 50 to the first integrated circuit device 20, for example, provided in FIG. 2; the second integrated circuit package 200 is formed by attaching a second integrated circuit device 50 (e.g., a die or a chiplet) to the first integrated circuit device 20; the second integrated circuit device 50 may be a logic device (e.g., central processing unit (CPU), graphics processing unit (GPU), microcontroller, etc.), a memory device (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), a power management device (e.g., power management integrated circuit (PMIC) die), a radio frequency (RF) device, a sensor device, a micro-electro-mechanical-system (MEMS) device, a signal processing device (e.g., digital signal processing (DSP) die), a front-end device (e.g., analog front-end (AFE) dies), the like, or combinations thereof (e.g., a system-on-a-chip (SoC) die); see Par.[0065]-[0069] wherein a plurality of the first integrated circuit device 20A and 20B may be stacked before attaching the second integrated circuit device 50 or the carrier wafer 60; the front-side memory arrays (e.g., the front-side memory elements 36A/B and corresponding devices in the device layers 26A/B) and the back-side memory array (e.g., the back-side memory elements 126A/B and corresponding devices in the device layers 26A/B) are non-volatile memories; as illustrated, all of the devices in the plurality of the first integrated circuit devices 20A and 20B may include both of the front-side memory arrays (e.g., the front-side memory elements 36A and 36B) and the back-side memory arrays (e.g., the back-side memory elements 126A and 126B); any of the front-side interconnect structures 30A and 30B and/or the back-side interconnect structures 120A and 120B may be formed without the corresponding memory elements 36A/B and/or 126A/B); and the bottom die (20A) configured to pass power from the bottom die back side metallization (120A) to the metal layers of the top die by way of back side pass-through vias formed in dummy cells (26A) interspersed among active logic cells of the bottom die (see Par.[0031]-[0035] wherein the second bonding layer 46 and the third conductive features 47 may be formed using either same or different methods and/or materials as forming the first bonding layer 44 and the second conductive features 45; see Par.[0040] wherein the back-side interconnect structure 120 includes a back-side power delivery network to provide the means of delivering power and other external connectivity to the integrated circuit; the back-side memory elements 126 may include some of the fourth conductive features 124 as well as one or more other types of devices (e.g., capacitors, resistors, diodes, inductors, power lines, and/or the like); see Par.[0051] wherein the fourth conductive features 124 of the back-side interconnect structure 120 form the power delivery network (PDN) (e.g., including power rails, which provide high throughput current) for power and ground routing through the integrated circuit. The TSVs 90 formed through the substrate 22 may include TSVs 90A formed by, for example, a via-first process as well as TSVs 90B formed by, for example, a via-last process; the TSVs 90A may also be referred to as buried rails and may be configured to delivery power or ground voltages to the device layer 26 and/or the front-side interconnect structure 30; see Par.[0016] wherein the devices formed over and in the device layer 26 as well as the subsequent processing, each completed first integrated circuit package 100 may be a logic device (e.g., central processing unit (CPU), graphics processing unit (GPU), microcontroller, etc.), a memory device (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), a power management device (e.g., power management integrated circuit (PMIC) die), a radio frequency (RF) device, a sensor device, a micro-electro-mechanical-system (MEMS) device, a signal processing device (e.g., digital signal processing (DSP) die), a front-end device (e.g., analog front- end (AFE) dies), the like, or combinations thereof (e.g., a system-on-a-chip (SoC) die)).
With respect to claim 15, Wang discloses, in Figs.1-15B, the three-dimensional integrated circuit configuration, wherein the bottom die (20A) front side metallization is configured adjacent to top die front side metallization (see Par.[0055]-[0056] wherein the second integrated circuit package 200 is formed by bonding a second integrated circuit device 50 to the first integrated circuit device 20, for example, provided in FIG. 2; the second integrated circuit package 200 is formed by attaching a second integrated circuit device 50 (e.g., a die or a chiplet) to the first integrated circuit device 20; the second integrated circuit device 50 may be a logic device (e.g., central processing unit (CPU), graphics processing unit (GPU), microcontroller, etc.), a memory device (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), a power management device (e.g., power management integrated circuit (PMIC) die), a radio frequency (RF) device, a sensor device, a micro- electro-mechanical-system (MEMS) device, a signal processing device (e.g., digital signal processing (DSP) die), a front-end device (e.g., analog front-end (AFE) dies), the like, or combinations thereof (e.g., a system-on-a-chip (SoC) die); see Par.[0065]-[0069] wherein a plurality of the first integrated circuit device 20A and 20B may be stacked before attaching the second integrated circuit device 50 or the carrier wafer 60; the front-side memory arrays (e.g., the front-side memory elements 36A/B and corresponding devices in the device layers 26A/B) and the back-side memory array (e.g., the back-side memory elements 126A/B and corresponding devices in the device layers 26A/B) are non-volatile memories; as illustrated, all of the devices in the plurality of the first integrated circuit devices 20A and 20B may include both of the front-side memory arrays (e.g., the front-side memory elements 36A and 36B) and the back-side memory arrays (e.g., the back-side memory elements 126A and 126B); any of the front-side interconnect structures 30A and 30B and/or the back-side interconnect structures 120A and 120B may be formed without the corresponding memory elements 36A/B and/or 126A/B).
With respect to claim 16, Wang discloses, in Figs.1-15B, the three-dimensional integrated circuit configuration, wherein the top die (50, 20B) is not configured with back side metallization (120B) (see Par.[0055]-[0056] wherein the second integrated circuit package 200 is formed by bonding a second integrated circuit device 50 to the first integrated circuit device 20, for example, provided in FIG. 2; the second integrated circuit package 200 is formed by attaching a second integrated circuit device 50 (e.g., a die or a chiplet) to the first integrated circuit device 20; the second integrated circuit device 50 may be a logic device (e.g., central processing unit (CPU), graphics processing unit (GPU), microcontroller, etc.), a memory device (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), a power management device (e.g., power management integrated circuit (PMIC) die), a radio frequency (RF) device, a sensor device, a micro-electro-mechanical-system (MEMS) device, a signal processing device (e.g., digital signal processing (DSP) die), a front-end device (e.g., analog front- end (AFE) dies), the like, or combinations thereof (e.g., a system-on-a-chip (SoC) die); see Par.[0065]- [0069] wherein a plurality of the first integrated circuit device 20A and 20B may be stacked before attaching the second integrated circuit device 50 or the carrier wafer 60; the front-side memory arrays (e.g., the front-side memory elements 36A/B and corresponding devices in the device layers 26A/B) and the back-side memory array (e.g., the back-side memory elements 126A/B and corresponding devices in the device layers 26A/B) are non-volatile memories; as illustrated, all of the devices in the plurality of the first integrated circuit devices 20A and 20B may include both of the front-side memory arrays (e.g., the front-side memory elements 36A and 36B) and the back-side memory arrays (e.g., the back-side memory elements 126A and 126B); any of the front-side interconnect structures 30A and 30B and/or the back-side interconnect structures 120A and 120B may be formed without the corresponding memory elements 36A/B and/or 126A/B).
With respect to claim 17, Wang discloses, in Figs.1-15B, the three-dimensional integrated circuit configuration, wherein the bottom die front side metallization is configured adjacent to top die back side metallization (see Par.[0055]-[0056] wherein the second integrated circuit package 200 is formed by bonding a second integrated circuit device 50 to the first integrated circuit device 20, for example, provided in FIG. 2; the second integrated circuit package 200 is formed by attaching a second integrated circuit device 50 (e.g., a die or a chiplet) to the first integrated circuit device 20; the second integrated circuit device 50 may be a logic device (e.g., central processing unit (CPU), graphics processing unit (GPU), microcontroller, etc.), a memory device (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), a power management device (e.g., power management integrated circuit (PMIC) die), a radio frequency (RF) device, a sensor device, a micro-electro-mechanical-system (MEMS) device, a signal processing device (e.g., digital signal processing (DSP) die), a front-end device (e.g., analog front-end (AFE) dies), the like, or combinations thereof (e.g., a system- on-a-chip (SoC) die); see Par.[0065]-[0069] wherein a plurality of the first integrated circuit device 20A and 20B may be stacked before attaching the second integrated circuit device 50 or the carrier wafer 60; the front-side memory arrays (e.g., the front-side memory elements 36A/B and corresponding devices in the device layers 26A/B) and the back-side memory array (e.g., the back-side memory elements 126A/B and corresponding devices in the device layers 26A/B) are non-volatile memories; as illustrated, all of the devices in the plurality of the first integrated circuit devices 20A and 20B may include both of the front- side memory arrays (e.g., the front-side memory elements 36A and 36B) and the back-side memory arrays (e.g., the back-side memory elements 126A and 126B); any of the front-side interconnect structures 30A and 30B and/or the back-side interconnect structures 120A and 120B may be formed without the corresponding memory elements 36A/B and/or 126A/B).
With respect to claim 18, Wang discloses, in Figs.1-15B, a three-dimensional integrated circuit configuration comprising: a bottom die (20A) configured with bottom die back side metallization (120A) and bottom die (20A) front side metallization (30A); a middle die (20B) configured with metal layers (120B) adjacent to the bottom die front side metallization (30A); a top die (50) configured with metal layers (26) adjacent to metal layers of the middle die (20B) (see Par.[0055]-[0056] wherein the second integrated circuit package 200 is formed by bonding a second integrated circuit device 50 to the first integrated circuit device 20, for example, provided in FIG. 2; the second integrated circuit package 200 is formed by attaching a second integrated circuit device 50 (e.g., a die or a chiplet) to the first integrated circuit device 20; the second integrated circuit device 50 may be a logic device (e.g., central processing unit (CPU), graphics processing unit (GPU), microcontroller, etc.), a memory device (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), a power management device (e.g., power management integrated circuit (PMIC) die), a radio frequency (RF) device, a sensor device, a micro-electro-mechanical-system (MEMS) device, a signal processing device (e.g., digital signal processing (DSP) die), a front-end device (e.g., analog front-end (AFE) dies), the like, or combinations thereof (e.g., a system-on-a-chip (SoC) die); see ar.[0065]-[0069] wherein a plurality of the first integrated circuit device 20A and 20B may be stacked before attaching the second integrated circuit device 50 or the carrier wafer 60; the front-side memory arrays (e.g., the front-side memory elements 36A/B and corresponding devices in the device layers 26A/B) and the back-side memory array (e.g., the back-side memory elements 126A/B and corresponding devices in the device layers 26A/B) are non-volatile memories; as illustrated, all of the devices in the plurality of the first integrated circuit devices 20A and 20B may include both of the front-side memory arrays (e.g., the front-side memory elements 36A and 36B) and the back-side memory arrays (e.g., the back-side memory elements 126A and 126B); any of the front-side interconnect structures 30A and 30B and/or the back-side interconnect structures 120A and 120B may be formed without the corresponding memory elements 36A/B and/or 126A/B); and the bottom die (20A) configured to pass power from the bottom die back side metallization to the metal layers of the middle die (20B) by way of back side pass-through vias formed in dummy cells (26A) interspersed among active logic cells of the bottom die (see Par.[0031]-[0035] wherein the second bonding layer 46 and the third conductive features 47 may be formed using either same or different methods and/or materials as forming the first bonding layer 44 and the second conductive features 45; see Par.[0040] wherein the back-side interconnect structure 120 includes a back-side power delivery network to provide the means of delivering power and other external connectivity to the integrated circuit; the back-side memory elements 126 may include some of the fourth conductive features 124 as well as one or more other types of devices (e.g., capacitors, resistors, diodes, inductors, power lines, and/or the like); see :[0051] wherein the fourth conductive features 124 of the back-side interconnect structure 120 form the power delivery network (PDN) (e.g., including power rails, which provide high throughput current) for power and ground routing through the integrated circuit. The TSVs 90 formed through the substrate 22 may include TSVs 90A formed by, for example, a via-first process as well as TSVs 90B formed by, for example, a via-last process; the TSVs 90A may also be referred to as buried rails and may be configured to delivery power or ground voltages to the device layer 26 and/or the front-side interconnect structure 30; see Par.[0016] wherein the devices formed over and in the device layer 26 as well as the subsequent processing, each completed first integrated circuit package 100 may be a logic device (e.g., central processing unit (CPU), graphics processing unit (GPU), microcontroller, etc.), a memory device (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), a power management device (e.g., power management integrated circuit (PMIC) die), a radio frequency (RF) device, a sensor device, a micro-electro-mechanical-system (MEMS) device, a signal processing device (e.g., digital signal processing (DSP) die), a front-end device (e.g., analog front-end (AFE) dies), the like, or combinations thereof (e.g., a system-on-a-chip (SoC) die)).
With respect to claim 19, Wang discloses, in Figs.1-15B, the three-dimensional integrated circuit configuration, wherein the bottom die (20A) front side metallization (30A) is configured adjacent to middle die (20B) front side metallization (120B) (see Fig.12).
With respect to claim 20, Wang discloses, in Figs.1-15B, the three-dimensional integrated circuit configuration, wherein the middle die (20B) is a capacitor die (see Par.[0013], [0016] wherein the substrate 22 has an active surface (e.g., the surface facing upward or the front-side surface) and an inactive surface (e.g., the surface facing downward or the back-side surface); devices (also not separately illustrated) in a device layer 26 (e.g.; die 20B comprises device 26B) discussed below are at the active surface of the substrate 22; the devices may be active and passive devices, including transistors, diodes, capacitors, resistors, and the like; the inactive surface may be free of devices; see Par.[0018] wherein the front-side interconnect structure 30 may include front-side memory elements 36 (not individually illustrated) electrically connected to certain devices in the device layer 26 to form a front-side memory array; the front-side memory elements 36 may include some of the first conductive features 34 as well as one or more other types of devices (e.g., capacitors, resistors, diodes, inductors, transmission lines, and/or the like); see Par.[0040] wherein the back-side memory elements 126 may include some of the fourth conductive features 124 as well as one or more other types of devices (e.g., capacitors, resistors, diodes, inductors, power lines, and/or the like)).
With respect to claim 21, Wang discloses, in Figs.1-15B, the three-dimensional integrated circuit configuration, wherein the capacitor die is configured to pass the power to top die front side metallization by way of through-silicon vias (see Par.[0013], [0016] wherein the substrate 22 has an active surface (e.g., the surface facing upward or the front-side surface) and an inactive surface (e.g., the surface facing downward or the back-side surface); devices (also not separately illustrated) in a device layer 26 (e.g.; die 20B comprises device 26B) discussed below are at the active surface of the substrate 22; the devices may be active and passive devices, including transistors, diodes, capacitors, resistors, and the like; the inactive surface may be free of devices; see Par.[0018] wherein the front-side interconnect structure 30 may include front-side memory elements 36 (not individually illustrated) electrically connected to certain devices in the device layer 26 to form a front-side memory array; the front-side memory elements 36 may include some of the first conductive features 34 as well as one or more other types of devices (e.g., capacitors, resistors, diodes, inductors, transmission lines, and/or the like); see Par.[0040] wherein the back-side memory elements 126 may include some of the fourth conductive features 124 as well as one or more other types of devices (e.g., capacitors, resistors, diodes, inductors, power lines, and/or the like); see Par.[0031]-[0035] wherein the second bonding layer 46 and the third conductive features 47 may be formed using either same or different methods and/or materials as forming the first bonding layer 44 and the second conductive features 45; see Par.[0040] wherein the back-side interconnect structure 120 includes a back-side power delivery network to provide the means of delivering power and other external connectivity to the integrated circuit; the back-side memory elements 126 may include some of the fourth conductive features 124 as well as one or more other types of devices (e.g., capacitors, resistors, diodes, inductors, power lines, and/or the like); see [0051] wherein the fourth conductive features 124 of the back-side interconnect structure 120 form the power delivery network (PDN) (e.g., including power rails, which provide high throughput current) for power and ground routing through the integrated circuit. The TSVs 90 formed through the substrate 22 may include TSVs 90A formed by, for example, a via-first process as well as TSVs 90B formed by, for example, a via- last process; the TSVs 90A may also be referred to as buried rails and may be configured to delivery power or ground voltages to the device layer 26 and/or the front-side interconnect structure 30; see Par.[0016] wherein the devices formed over and in the device layer 26 as well as the subsequent processing, each completed first integrated circuit package 100 may be a logic device (e.g., central processing unit (CPU), graphics processing unit (GPU), microcontroller, etc.), a memory device (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), a power management device (e.g., power management integrated circuit (PMIC) die), a radio frequency (RF) device, a sensor device, a micro-electro-mechanical-system (MEMS) device, a signal processing device (e.g., digital signal processing (DSP) die), a front-end device (e.g., analog front-end (AFE) dies), the like, or combinations thereof (e.g., a system-on-a-chip (SoC) die)).
With respect to claim 22, Wang discloses, in Figs. 1-15B, the three-dimensional integrated circuit configuration, wherein the capacitor die is configured to pass the power to top die back side metallization by way of through-silicon vias (see Par.[0013], [0016] wherein the substrate 22 has an active surface (e.g., the surface facing upward or the front-side surface) and an inactive surface (e.g., the surface facing downward or the back-side surface); devices (also not separately illustrated) in a device layer 26 (e.g.; die 20B comprises device 26B) discussed below are at the active surface of the substrate 22; the devices may be active and passive devices, including transistors, diodes, capacitors, resistors, and the like; the inactive surface may be free of devices; see Par.[0018] wherein the front-side interconnect structure 30 may include front-side memory elements 36 (not individually illustrated) electrically connected to certain devices in the device layer 26 to form a front-side memory array; the front-side memory elements 36 may include some of the first conductive features 34 as well as one or more other types of devices (e.g., capacitors, resistors, diodes, inductors, transmission lines, and/or the like); see Par.[0040] wherein the back-side memory elements 126 may include some of the fourth conductive features 124 as well as one or more other types of devices (e.g., capacitors, resistors, diodes, inductors, power lines, and/or the like); see Par.[0031]-[0035] wherein the second bonding layer 46 and the third conductive features 47 may be formed using either same or different methods and/or materials as forming the first bonding layer 44 and the second conductive features 45; see Par.[0040] wherein the back-side interconnect structure 120 includes a back-side power delivery network to provide the means of delivering power and other external connectivity to the integrated circuit; the back-side memory elements 126 may include some of the fourth conductive features 124 as well as one or more other types of devices (e.g., capacitors, resistors, diodes, inductors, power lines, and/or the like); see Par.[0051] wherein the fourth conductive features 124 of the back-side interconnect structure 120 form the power delivery network (PDN) (e.g., including power rails, which provide high throughput current) for power and ground routing through the integrated circuit; the TSVs 90 formed through the substrate 22 may include TSVs 90A formed by, for example, a via-first process as well as TSVs 90B formed by, for example, a via- last process; the TSVs 90A may also be referred to as buried rails and may be configured to delivery power or ground voltages to the device layer 26 and/or the front-side interconnect structure 30; see Par.[0016] wherein the devices formed over and in the device layer 26 as well as the subsequent processing, each completed first integrated circuit package 100 may be a logic device (e.g., central processing unit (CPU), graphics processing unit (GPU), microcontroller, etc.), a memory device (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), a power management device (e.g., power management integrated circuit (PMIC) die), a radio frequency (RF) device, a sensor device, a micro-electro-mechanical-system (MEMS) device, a signal processing device (e.g., digital signal processing (DSP) die), a front-end device (e.g., analog front-end (AFE) dies), the like, or combinations thereof (e.g., a system-on-a-chip (SoC) die)).
With respect to claim 23, Wang discloses, in Figs.1-15B, the three-dimensional integrated circuit configuration, wherein the bottom die (20A) front side metallization (30A) is configured adjacent to middle die back side metallization (120B) (see Fig. 12).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11-13, 24-26 are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Agarwal et al. (US 2012/0317529 A1 hereinafter referred to as "Agarwal").
With respect to claim 11, Wang discloses all the claimed limitations of claim 10. However, Wang does not explicitly disclose all the limitations of claim 11.
Agarwal discloses, in Figs. 1-8, the three-dimensional integrated circuit configuration, wherein one or both of the first die and the second die are configured with metallization forming a thermal grid (see Par.[0023] wherein FIG. 1 depicts an example chip package in which an integrated circuit may experience self-heating of wires due to resistive power dissipation; package 102 provides connectivity to input/output pins for an integrated circuit; interconnect layers 104 connect to package 102 by balls of solder. Interconnect layers 104 provide metal wires for connecting various components in substrate 106; see Par.[0024]-[0026], [0029], [0031] wherein wires in interconnect layers 104 experience self heating, also referred to as Joule heating; the wires experience self-heating because of poor heat transfer due to low thermal conductivity of inter-layer dielectric within interconnect layers 104; the self-heating depends on the root mean square (RMS) current density; thermal grid generator 220 generates a resistive network based on thermal conductivities of wires and dielectric in lateral and vertical directions; thermal grid generator 220 generates the thermal resistance network based on an analogy between electrical RC network and thermal resistance network).
Wang and Agarwal are analogous art because they are all directed to a semiconductor package device, and one of ordinary skill in the art would have had a reasonable expectation of success by modifying Wang to include Agarwal because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the package interconnect layers in Wang by including interconnect with thermal grid component as taught by Agarwal in order to utilize several advantages offered by the thermal grid in semiconductor package interconnects, particularly in managing thermal performance and ensuring reliability under thermal cycling conditions, therefore enhancing the overall performance of the device.
With respect to claim 12, Agarwal discloses, in Figs. 1-8, the three-dimensional integrated circuit configuration, wherein the thermal grid comprises interconnected fill metal layers (see Par.[0023] wherein FIG. 1 depicts an example chip package in which an integrated circuit may experience self-heating of wires due to resistive power dissipation; package 102 provides connectivity to input/output pins for an integrated circuit; interconnect layers 104 connect to package 102 by balls of solder. Interconnect layers 104 provide metal wires for connecting various components in substrate 106; see Par.[0024]-[0026], [0029], [0031] wherein wires in interconnect layers 104 experience self heating, also referred to as Joule heating; the wires experience self heating because of poor heat transfer due to low thermal conductivity of inter-layer dielectric within interconnect layers 104; the self heating depends on the root mean square (RMS) current density; thermal grid generator 220 generates a resistive network based on thermal conductivities of wires and dielectric in lateral and vertical directions; thermal grid generator 220 generates the thermal resistance network based on an analogy between electrical RC network and thermal resistance network).
With respect to claim 13, Agarwal discloses, in Figs. 1-8, the three-dimensional integrated circuit configuration, wherein the thermal grid is aligned with hot spots on one or both of the first die and the second die (see ar.[0023] wherein FIG. 1 depicts an example chip package in which an integrated circuit may experience self-heating of wires due to resistive power dissipation; package 102 provides connectivity to input/output pins for an integrated circuit; interconnect layers 104 connect to package 102 by balls of solder. Interconnect layers 104 provide metal wires for connecting various components in substrate 106; see Par.[0024]-[0026], [0029], [0031] wherein wires in interconnect layers 104 experience self heating, also referred to as Joule heating; the wires experience self heating because of poor heat transfer due to low thermal conductivity of inter-layer dielectric within interconnect layers 104; the self heating depends on the root mean square (RMS) current density; thermal grid generator 220 generates a resistive network based on thermal conductivities of wires and dielectric in lateral and vertical directions; thermal grid generator 220 generates the thermal resistance network based on an analogy between electrical RC network and thermal resistance network).
With respect to claim 24, Wang discloses all the claimed limitations of claim 10. However, Wang does not explicitly disclose all the limitations of claim 11.
Agarwal discloses, in Figs.1-8, the three-dimensional integrated circuit configuration, wherein one or both of the first die and the second die are configured with metallization forming a thermal grid (see Par.[0023] wherein FIG. 1 depicts an example chip package in which an integrated circuit may experience self-heating of wires due to resistive power dissipation; package 102 provides connectivity to input/output pins for an integrated circuit; interconnect layers 104 connect to package 102 by balls of solder. Interconnect layers 104 provide metal wires for connecting various components in substrate 106; see Par.[0024]-[0026], [0029], [0031] wherein wires in interconnect layers 104 experience self heating, also referred to as Joule heating; the wires experience self-heating because of poor heat transfer due to low thermal conductivity of inter-layer dielectric within interconnect layers 104; the self-heating depends on the root mean square (RMS) current density; thermal grid generator 220 generates a resistive network based on thermal conductivities of wires and dielectric in lateral and vertical directions; thermal grid generator 220 generates the thermal resistance network based on an analogy between electrical RC network and thermal resistance network).
Wang and Agarwal are analogous art because they are all directed to a semiconductor packge device, and one of ordinary skill in the art would have had a reasonable expectation of success by modifying Wang to include Agarwal because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the package interconnect layers in Wang by including interconnect with thermal grid component as taught by Agarwal in order to utilize several advantages offered by the thermal grid in semiconductor package interconnects, particularly in managing thermal performance and ensuring reliability under thermal cycling conditions, therefore enhancing the overall performance of the device.
With respect to claim 25, Agarwal discloses, in Figs. 1-8, the three-dimensional integrated circuit configuration, wherein the thermal grid comprises interconnected fill metal layers (see Par.[0023] wherein FIG. 1 depicts an example chip package in which an integrated circuit may experience self-heating of wires due to resistive power dissipation; package 102 provides connectivity to input/output pins for an integrated circuit; interconnect layers 104 connect to package 102 by balls of solder. Interconnect layers 104 provide metal wires for connecting various components in substrate 106; see Par.[0024]-[0026], [0029], [0031] wherein wires in interconnect layers 104 experience self heating, also referred to as Joule heating; the wires experience self heating because of poor heat transfer due to low thermal conductivity of inter-layer dielectric within interconnect layers 104; the self heating depends on the root mean square (RMS) current density; thermal grid generator 220 generates a resistive network based on thermal conductivities of wires and dielectric in lateral and vertical directions; thermal grid generator 220 generates the thermal resistance network based on an analogy between electrical RC network and thermal resistance network).
With respect to claim 26, Agarwal discloses, in Figs. 1-8, the three-dimensional integrated circuit configuration, wherein the thermal grid is aligned with hot spots on one or both of the first die and the second die (see Par.[0023] wherein FIG. 1 depicts an example chip package in which an integrated circuit may experience self-heating of wires due to resistive power dissipation; package 102 provides connectivity to input/output pins for an integrated circuit; interconnect layers 104 connect to package 102 by balls of solder. Interconnect layers 104 provide metal wires for connecting various components in substrate 106; see Par.[0024]-[0026], [0029], [0031] wherein wires in interconnect layers 104 experience self heating, also referred to as Joule heating; the wires experience self heating because of poor heat transfer due to low thermal conductivity of inter-layer dielectric within interconnect layers 104; the self heating depends on the root mean square (RMS) current density; thermal grid generator 220 generates a resistive network based on thermal conductivities of wires and dielectric in lateral and vertical directions; thermal grid generator 220 generates the thermal resistance network based on an analogy between electrical RC network and thermal resistance network).
Response to Arguments
Applicant's arguments filed 08/10/2026 have been fully considered but they are not persuasive.
Applicant alleges that the identification of devices 26 do not include vias and dummy cells (see remarks, pages 8 of 12). Examiner disagrees. As previously presented in the Non-Final Rejection mailed on 08/10/2026, Wang teaches device element that include dummy structures 45, 47 within which conductive features pass-through layer 44 (e.g., Figs. 9-12, see Par.[0031]-[0032] wherein a second bonding layer 46 and third conductive features 47 may be formed over the carrier wafer 60 using the methods and materials described above in connection with the first bonding layer 44 and the second conductive features 45). Applicant also suggests that the present of bonding material within identified dummy cells implies that 45, 47, 44, 46 together can not constitute a dummy cell of present invention. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., dummy cells void of bonding material) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Applicant also alleges that Agarwal thermal grid is not that of claimed thermal grid because the “thermal grid” in the claims is a particular configuration of actual physical metallization (see remarks, page 10/12). In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., particular of actual physical metallization) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Examiner’s Telephone/Fax Contacts
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOULOUCOULAYE INOUSSA whose telephone number is (571)272-0596. The examiner can normally be reached Monday-Friday (10-18).
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/Mouloucoulaye Inoussa/ Primary Examiner, Art Unit 2818
