DETAILED ACTION
This action is in regards to the arguments and amendments filed on 12/12/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 14, 21, and 34 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 14, 21, 34, and 40-41 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li et al. (US 2014/0145650) and Elbanhawy (US 2008/0007236). Regarding claims 1 and 21, Li et al. discloses (see fig. 1, 2 and 5) a method for controlling an input current limit of boost converter circuitry (operation of 34 controlling input current limit of 12), the method comprising: receiving a power dissipation value for the boost converter circuitry (output from 32 to 34); and controlling an input current limit of the boost converter circuitry based on the power dissipation value (operation of 34 controlling input current limit of 12). Li et al. does not disclose that the power dissipation value is representative of power dissipated by the boost converter circuitry in operation of the boost converter circuitry. Elbanhawy discloses that a power dissipation value is representative of power dissipated by the boost converter circuitry in operation of the boost converter circuitry (see paragraph 0014). Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the method of Li et al. to include the features of Elbanhawy because it provides for a transient control means to prevent unwanted fluctuations in operation, thus increasing operational efficiencies. Regarding claims 14 and 34, Li et al. discloses (see fig. 1, 2 and 5) a method for controlling an input current limit of boost converter circuitry (operation of 34 controlling input current limit of 12), the method comprising: receiving a power dissipation value of the boost converter circuitry (output from 32 to 34); determining a duration for which the boost converter circuitry is permitted to dissipate power at the power dissipation value (operation of 34 determining that the operation period of the converter is not normal); and controlling the input current limit of the boost converter circuitry based on the determined duration (operation of 34 limiting input current during the non-normal operational period). Li et al. does not disclose that the power dissipation value is representative of power dissipated by the boost converter circuitry in operation of the boost converter circuitry. Elbanhawy discloses that a power dissipation value is representative of power dissipated by the boost converter circuitry in operation of the boost converter circuitry (see paragraph 0014). Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the method of Li et al. to include the features of Elbanhawy because it provides for a transient control means to prevent unwanted fluctuations in operation, thus increasing operational efficiencies. Regarding claim 40, Li et al. discloses (see fig. 1, 2, and 5) an integrated circuit comprising a system according to claim 21 (see fig. 1, 2, and 5). Regarding claim 41, Li et al. discloses (see fig. 1, 2, and 5) a host device comprising the system of claim 21 (see fig. 1, 2, and 5). Li et al. discloses the claimed invention except for a host device comprising a laptop, notebook, netbook or tablet computer, a gaming device, a games console, a controller for a games console, a virtual reality (VR) or augmented reality (AR) device, a mobile telephone, a portable audio player, a portable device, an accessory device for use with a laptop, notebook, netbook or tablet computer, a gaming device, a games console a VR or AR device, a mobile telephone, a portable audio player or other portable device. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to have a host device comprise a laptop, notebook, netbook or tablet computer, a gaming device, a games console, a controller for a games console, a virtual reality (VR) or augmented reality (AR) device, a mobile telephone, a portable audio player, a portable device, an accessory device for use with a laptop, notebook, netbook or tablet computer, a gaming device, a games console a VR or AR device, a mobile telephone, a portable audio player or other portable device, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the method of Li et al. to include the features of having a host device comprise a laptop, notebook, netbook or tablet computer, a gaming device, a games console, a controller for a games console, a virtual reality (VR) or augmented reality (AR) device, a mobile telephone, a portable audio player, a portable device, an accessory device for use with a laptop, notebook, netbook or tablet computer, a gaming device, a games console a VR or AR device, a mobile telephone, a portable audio player or other portable device, because it allows for a specific design choice, which can provide a reduction in component variance, thus increasing operational efficiencies.
Claim(s) 2-4, 10, 15-16, 22-23, and 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US 2014/0145650) in view of Elbanhawy (US 2008/0007236), Shimada et al. (US Patent 10063058) and Iisaka et al. (US Patent 10630194). Regarding claim 2, 15, 22, Li et al. does not disclose determining the power dissipation value based on an input power value of the boost converter circuitry and an efficiency value for the boost converter circuitry at the determined input power value. Shimada et al. discloses (see fig. 2) that power dissipation value is based on an input power value of a converter circuitry ( operation of 301-303 based on input voltage and input current of 200). Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the method of Li et al. to include the features of Shimada et al. because it provides for a transient control means to prevent unwanted fluctuations in operation, thus increasing operational efficiencies. Iisaka et al. discloses (see fig. 1) that a power dissipation value (output from controller 10) based on an efficiency value for a converter circuitry (see equation 2, column 9 line 25) at a determined input power value (See column 9 lines 18-40). Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the method of Li et al. to include the features of Iisaka et al. because it provides for a transient control means to prevent unwanted fluctuations in operation, thus increasing operational efficiencies. Regarding claims 3, Li et al. does not disclose that determining the input power value of the boost converter circuitry comprises: receiving an input current value and an input voltage value and determining the input power value based on the input current value and the input voltage value. Shimada et al. discloses (see fig. 2) that determining an input power value of a converter circuitry comprises: receiving an input current value (output from current sensor 21) and an input voltage value (output from voltage sensor 31) and determining the input power value based on the input current value and the input voltage value (operation of 301). Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the method of Li et al. to include the features of Shimada et al. because it provides for a transient control means to prevent unwanted fluctuations in operation, thus increasing operational efficiencies. Regarding claim 4, Li et al. does not disclose that the input current value is based on a signal received from input current monitor circuitry and the input voltage value is based on a signal received from input voltage monitor circuitry. Shimada et al. discloses (see fig. 2) that the input current value is based on a signal received from input current monitor circuitry (output from 21) and the input voltage value is based on a signal received from input voltage monitor circuitry (output from 31). Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the method of Li et al. to include the features of Shimada et al. because it provides for a transient control means to prevent unwanted fluctuations in operation, thus increasing operational efficiencies. Regarding claim 10, 16, 30, Li et al. does not disclose that the efficiency value is dynamically calculated or dynamically measured during operation of the boost converter circuitry. Iisaka et al. discloses (see fig. 1) that the efficiency value is dynamically calculated or dynamically measured during operation of a converter circuitry (see equation 2, column 9 line 25). Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the method of Li et al. to include the features of Iisaka et al. because it provides for a transient control means to prevent unwanted fluctuations in operation, thus increasing operational efficiencies. Regarding claim 23, Li et al. does not disclose that determining the input power value of the boost converter circuitry comprises: receiving an input current value and an input voltage value and determining the input power value based on the input current value and the input voltage value; wherein the system further comprises current monitor circuitry configured to output a signal indicative of the input current and voltage monitor circuitry configured to output a signal indicative of the input voltage. Shimada et al. discloses (see fig. 2) that determining an input power value of a converter circuitry comprises: receiving an input current value (output from current sensor 21) and an input voltage value (output from voltage sensor 31) and determining the input power value based on the input current value and the input voltage value (operation of 301), wherein a system further comprises a current monitor circuitry (21) configured to output a signal indicative of the input current (output from 21) and a voltage monitor circuitry (31) configured to output a signal indicative of the input voltage (output from 31). Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the method of Li et al. to include the features of Shimada et al. because it provides for a transient control means to prevent unwanted fluctuations in operation, thus increasing operational efficiencies.
Claim(s) 13 and 33 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US 2014/0145650) in view of Elbanhawy (US 2008/0007236) and Sherman (US Patent 6507172). Regarding claims 13 and 33, Li et al. does not disclose that the input current limit of the boost converter circuitry is controlled to limit a die temperature increase or a rate of die temperature increase of a semiconductor die on which the boost converter circuitry is implemented. Sherman discloses (see fig. 2-3) that an input current limit of a converter circuitry (32) is controlled to limit a die temperature increase or a rate of die temperature increase of a semiconductor die on which the boost converter circuitry is implemented (operation of 40/44/46/48). Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the method of Li et al. to include the features of Sherman because it provides for a transient control means to prevent unwanted fluctuations in operation, thus increasing operational efficiencies.
Claim(s) 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li et al. (US 2014/0145650) and Elbanhawy (US 2008/0007236) and Boncato (US Patent 10917003). Regarding claim 20, Li et al. does not disclose a non-transitory computer-readable medium storing instructions which, when executed by processing circuitry, cause the processing circuitry to perform the method of claim 1. Boncato discloses a non-transitory computer-readable medium storing instructions which, when executed by processing circuitry, cause the processing circuitry to perform a method (see column 7 line 58 – column 8 line 6). Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the method of Li et al. to include the features of Boncato because it provides for a reduction in footprint and area required for control management elements and thus allowing for favorable integration of function and reduction of cost.
Allowable Subject Matter
Claims 5, 9, 11, 17, 25, 29, and 31 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEFFREY A GBLENDE whose telephone number is (571)270-5472. The examiner can normally be reached M-F 9am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at 571-272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JEFFREY A GBLENDE/Primary Examiner, Art Unit 2838