DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/15/2024 and 11/14/2025 were considered by the examiner.
Drawings
The drawings received on 3/29/2024 were accepted by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 6-18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Pezeshki et al. [US 2023/0280557].
Claim 1, Pezeshki et al. discloses a system including a memory optical interconnect [par. 0002 and 0094; bus connections], comprising: a processor chip including logic for interfacing with memory [par. 0094, bus connections as described disclosing a bus master node 1311 comprising a transmitter Tx and a receiver Rx wherein the master node is identified as a processor]; a first array of microLEDs on the processor chip [par. 0016 and 0040 wherein a first array of optical transceivers electrically coupled to a first integrated circuit chip include at least one microLED as a light source and a first plurality of optical transmitters each include a microLED]; a first array of photodetectors on the processor chip [par. 0016 and 0040 wherein the first array of optical transceivers includes a first plurality of optical receivers each including a photodetector and receiver circuitry]; a plurality of memory chips [par. 0094]; and a fiber bundle including a plurality of sub-bundles of fibers [par. 0008 and 0084; the propagation medium is a multicore fiber; in some further embodiments the multicore fiber is a coherent fiber bundle (CFB) and the fiber can comprise a bundle of more than 1000 cores], with the fibers of some of the sub-bundles optically coupled to the first array of microLEDs and fibers of others of the sub-bundles optically coupled to the first array of photodetectors, and with fibers of different ones of the sub-bundles optically coupling different ones of the memory chips and the processor chip [par. 0040, 0094, 0095; Fig 13].
Claim 2, Pezeshki et al. discloses the system of claim 1, wherein the memory chips comprise static random-access memory (SRAM) chips [par. 0003 high performance computing clusters; par. 0036 consolidating functionality onto a single system on a chip. SRAM is the inherent standard for SoC cache/memory].
Claim 6, Pezeshki discloses the system of claim 1, wherein fibers of two different sub-bundles optically couple each memory chip and the processor chip [par. 0013; inter-chip optical communication system, first array of optical transceivers, second array of optical transceivers. Par. 0076, duplex optical waveguide links exploit light propagating in both directions].
Claim 7, Pezeshki discloses the system of claim 2, wherein a first of the two different sub-bundles provides for communication in a first transmit/receive direction and a second of the two different sub-bundles provides for communication in a second transmit/receive direction [par. 0042,optical interconnect channel comprising an optical transmitter in one transceiver array that is optically connected to an optical receiver in the other… defines dedicated directional paths].
Claim 8, Pezeshki discloses the system of claim 1, wherein the processor chip and the memory chips are on different substrates [par. 0053; PMI connects between two different modules which may be connected by many thousands of optical interconnects, par. 0055].
Claim 9, Pezeshki discloses a system including a processor optically connected to memory [par. 0003 and 0094; relates to microLED based inter and intra chip optical communication interconnections specifically describing a configuration useful for communication between a processor at the master node and multiple memories at the slave nodes], comprising: a processor chip including a plurality of processor cores, cache memory for each processor core, shared cache memory for the processor cores, and a first microLED interface [par. 0003 and 0040; discloses consolidating functionality onto a single system on a chip SoC. An SoC inherently includes a processor core and shared cache memory. Discloses a first optical transceiver array containing microLEDs]; at least one first memory electrically coupled to the processor chip; at least one second memory electrically coupled to a second microLED interface [par. 0040]; the first microLED interface and the second microLED interface each comprising microLEDs, drive circuitry for the microLEDs, photodetectors, and read-out circuitry for the photodetectors [par. 0016, 0044, 0046; the first array of optical transceivers including transmitters each including transmitter circuitry and microLED and optical receivers each including a photodetector and receiver circuitry. The second array contains the same elements]; and at least one optical fiber bundle, the at least one optical fiber bundle coupling the microLEDs of the first microLED interface with photodetectors of the second microLED interface and coupling the microLEDs of the second microLED interface with photodetectors of the first microLED interface [par. 0008, 0040, 0076; discloses coherent fiber bundle CFB optically connecting between the first optically connecting between the first optical transceiver array. Explicitly describes bidirectional communication and duplex links].
Claim 10, Pezeshki discloses the system of claim 9, wherein the second memory is directly mapped to a subset of address space of the processor core [par. 0051; interconnects serve as express lanes greatly reducing latency compared to an on chip electronic interconnect. Direct mapping is a standard method for reducing latency in high speed I/O].
Claim 11, Pezeshki discloses the system of claim 9, wherein the first memory comprises dynamic random-access memory (DRAM) and the second memory chip comprises static random-access memory (SRAM) [par. 0003; high performance computing clusters… standardly utilize DRAM for main memory and SRAM for local chip buffers/cache].
Claim 12, Pezeshki discloses the system of claim 9, wherein the first microLED interface of the processor chip is coupled to the processor cores such that processor core access to the second memory bypasses a hierarchy defined by the cache memory and shared cache memory of the processor chip [par. 0051; describes optical links as express lanes to bypass the tens of electrical regenerators such as flip flops found in standard IC hierarchies].
Claim 13, Pezeshki discloses the system of claim 9, wherein the first microLED interface of the processor chip is coupled to the processor cores by way of the cache memory and the shared cache memory of the processor chip [par. 0003 refers to the consolidation onto a single system on a chip, wherein these designs integrate I/O interfaces directly through the internal cache hierarchy].
Claim 14, Pezeshki discloses the system of claim 13, wherein the first microLED interface of the processor chip is coupled to the shared cache memory of the processor chip [par. 0003; consolidation into an SoC. The shared cache is the conventional point of synchronization for high speed I/O in multi-core SoCs].
Claim 15, Pezeshki discloses the system of claim 14, wherein the at least one optical fiber bundle includes a plurality of sub-bundles, each sub-bundle including fibers interfaced with an independent region of the second memory [par. 0013].
Claim 16, Pezeshki discloses a neural network accelerator memory interconnect [par. 0003, 0091], comprising: a plurality of first microLED interfaces on a neural network (NN) accelerator chip [par. 0007, 0040], the accelerator chip comprising a host interface for communication with a central processing unit (CPU) and blocks for performing matrix multiplication and arithmetic logic unit [par. 0003 and 0094; consolidating functionality onto a single SoC. The master slave bus architecture describes communication between a processor (CPU/host) and multiple nodes. Matrix multiplication and ALU blocks are inherent/standard components for the cited artificial neaural network application]; at least one second microLED interface coupled to memory external to the NN accelerator chip [par. 0040, 0094; discloses a second optical transceiver array coupled to a second integrated circuit chip or slave node, which is explicitly identified as memory]; with the plurality of first microLED interfaces and the at least one second microLED interface each comprising microLEDs, drive circuitry for the microLEDs, photodetectors, and read-out circuitry for the photodetectors [par. 0016, 0044, Fig. 2b, par. 0046, Fig. 2c; the first array of optical transceivers including transmitters each including transmitter circuitry and microLED and optical recievers each including a photodetector and receiver circuitry. The second array contains the same elements]; and at least one optical fiber bundle, the at least one optical fiber bundle coupling the microLEDs of the plurality of first microLED interfaces with photodetectors of the at least one second microLED interface and coupling the microLEDs of the at least one second microLED interface with photodetectors of the plurality of first microLED interfaces [par. 0008, 0040, 0076, Fig 1; discloses a coherent fiber bundle CFB, optically connecting between the first optical transceiver array and the second optical transceiver array. Explicitly describes bidirectional communication and duplex links].
Claim 17, Pezeshki discloses the neural network accelerator memory interconnect of claim 16, wherein a first of the plurality of first microLED interfaces is associated with computation weights, a second of the plurality of first microLED interfaces is associated with results of matrix multiplication by the NN accelerator chip, and a third of the plurality of first microLED interfaces is associated with intermediate results determined by the NN accelerator chip [par. 0003; prominent applications include artificial neural networks].
Claim 18, Pezeshki discloses a many-to-one high bandwidth memory interconnect [par. 0094], comprising: a plurality of first microLED interfaces coupled to a plurality of CPUs, with at least one of the plurality of first microLED interfaces packaged on or with each CPU die [par. 0003 and 0016; discloses consolidating functionality onto a single system on a chip. The first array of optical transceivers is electrically coupled to a first integrated circuit chip and can be in the same package]; at least one second microLED interface coupled to high bandwidth memory external to the CPU die [par. 0094]; with the plurality of first microLED interfaces and the at least one second microLED interface each comprising microLEDs, drive circuitry for the microLEDs, photodetectors, and read-out circuitry for the photodetectors [par. 0044, 0046; Figure 2b and 2c]; and at least one optical fiber bundle, the at least one optical fiber bundle coupling the microLEDs of the plurality of first microLED interfaces with photodetectors of the at least one second microLED interface and coupling the microLEDs of the at least one second microLED interface with photodetectors of the plurality of first microLED interfaces [par. 0008, 0076, 0094; discloses a coherent fiber bundel CFB optically connecting a master node and slave nodes. Describes bidirectional link capability and bidirectional communication across the propagation medium].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over Pezeshki et al. [US 2023/0280557] in view of Brusberg et al. [“Optoelectronic Glass Substrates for Co-packaging of Optics and ASICs”].
Claim 3, Pezeshki et al. discloses the system of claim 1, wherein the processor chip is mounted to a substrate [par. 0052]. Pezeshki et al. does not teach but Brusberg et al. discloses the fiber bundle routed through an aperture in the substrate [Brusberg section 4 teaches the creation of TGVs and complex cutouts at the substrate edge for fiber optic connector housings. A TGV is a functional aperture enabling vertical connectivity through the substrate]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the memory optical interconnect system of Pezeshki et al. with the glass packaging substrate of Brusberg et al. since Brusberg provides a physical routing path for fiber bundles to transition vertically from a processor chip through a supporting package substrate while achieving compact, low latency, high density packaging that overcomes bandwidth limitations of traditional electrical lines.
Claim 4, Pezeshki et al. in view of Brusberg et al. discloses the system of claim 3, wherein the first array of microLEDs and the first array of photodetectors are on an active surface of the processor chip [Pezeshki par. 0016; a first array of optical transceivers electrically coupled to a first integrated circuit chip including a first plurality of optical transmitters each including a micro-LED. Monolithic integration [par. 0047] requires the active surface].
Claim 5, Pezeshki et al. in view of Brusberg et al. discloses the system of claim 4, wherein a heatsink and cooling fins are coupled to an inactive surface of the processor chip [Brusberg sections 4, discloses glass packaging substrate and thermal management of a high-power consuming ASICs wherein adding standard heatsinks to the inactive side of a chip is a routine solution for the requirement.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kruger [US 2025/0299726]; Memory Relocation. See Background Par. 006-008.
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/MIDYS ROJAS/Primary Examiner, Art Unit 2133
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