DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Examiner acknowledges the amendment of claims 1, 4, 9, 12, and 17, filed on 8/14/2026.
The Examiner acknowledges the cancellation of claims 3 and 11.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 6, 9, 10, 16 are rejected under 35 U.S.C. 103 as being unpatentable over
Sevenhans et al (US Patent Number 5283535) in view of Danyuk (WO-2017192700-A1).
Regarding claim 1: Sevenhans discloses, in the figure, an amplifier circuit comprising: A differential pair of transistors (M1, M2) configured and arranged to generate a summed current (node VS) from
individual ones of the differential pair of transistors; a transistor (M3) coupled with the differential pair
of transistors (M1, M2, column 4, lines 25-29); and an error correction amplifier (amplifier A, column 4,
lines 43-48), coupled with a control terminal (gate electrode) of the transistor (M3) and configured for: comparing a representation of the summed current (node Vs) to a representation of a reference current (Vref); and adjusting, based on the comparison, a voltage (output voltage of amplifier A applied to the gate electrode of M3) at the control terminal of the transistor (M3,) (column 4, lines 43-48).
However, Sevenhans does not teach a reference current source configured to generate a reference current that is fixed and independent of an input signal applied to the differential pair of transistors.
Danyuk discloses a reference current source configured to generate a reference current that is fixed and independent of an input signal applied to the differential pair of transistors (POWER 2 reference input of current-controlled current source 408; the reference signal is implicitly a fixed reference value independent of INPUT 1 and INPUT2) ¶[0047]-[0048).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify Sevenhans’ amplifier circuit to include Danyuk’s reference-current and feedback arrangement in order to “suitably compensate variation of the differential input stage currents with input signal” (¶[0047], lines 3-4).
Regarding claim 2: Sevenhans does not disclose a first sense resistor coupled with the differential pair of transistors, wherein the first sense resistor is configured to generate the representation of the summed current from the differential pair of transistors.
Danyuk discloses a first sense resistor (series resistor 601; ¶[00500]-[0051]) coupled with the differential pair of transistors (303,304; transistor 602 and resistors 501, 502 couple resistor 601/current-control circuitry to the sources transistors 303, 304), wherein the first sense resistor is configured to generate the representation of the summed current from the differential pair of transistors (the total current of additional current followers 410, 411 corresponding to the currents of input devices 303, 304, produces a voltage drop across series resistor 601; ¶[0050]).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to further modify Sevenhans in view of Danyuk to include Danyuk’s first sense resistor as part of the reference-current and feedback arrangement in order to “suitably compensate variation of the differential input stage currents with input signal” (¶[0047], lines 3-4).
Regarding claim 6: Sevanhans, in the figure, discloses the amplifier circuit of claim 1, wherein the differential pair of transistors includes field-effect transistors (M1 and M2 NMOS field-effect transistors, column 4, lines 26-28).
Regarding claim 9: (Sevenhans discloses, in the figure, a method for biasing an amplifier circuit, the method comprising: coupling a transistor with a differential pair of transistors; generating a summed current from the differential pair of transistors; comparing, with an error correction amplifier (amplifier A, column 4,lines 43-48) coupled to a control terminal (gate electrode) of the transistor (M3), a representation of the summed current to a representation of [[a]] the reference current (amplifier A; node VS and Vref) and adjusting, based on the comparison and with the error correction amplifier, a voltage at the control terminal of the transistor (output voltage of amplifier A applied to the gate electrode of M3; (column 4, lines 43-48).
However, Sevenhans does not teach generating, via a reference current source, a reference current that is fixed and independent of an input signal applied to the differential pair of transistors.
Danyuk discloses generating, via a reference current source, a reference current that is fixed and independent of an input signal applied to the differential pair of transistors; (POWER 2 reference input of current-controlled current source 408; the reference signal is implicitly a fixed reference value independent of INPUT 1 and INPUT2) ¶[0047]-[0048).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify Sevenhans’ method of biasing an amplifier circuit to include Danyuk’s reference-current and feedback arrangement in order to “suitably compensate variation of the differential input stage currents with input signal” (¶[0047], lines 3-4).
Regarding claim 10: Sevenhans does not disclose coupling a first sense resistor with the differential pair of transistors to generate the representation of the summed current from the differential pair of transistors.
Danyuk discloses coupling a first sense resistor (series resistor 601; ¶[00500]-[0051]) with the differential pair of transistors (303,304; transistor 602 and resistors 501, 502 couple resistor 601/current-control circuitry to the sources transistors 303, 304), to generate the representation of the summed current from the differential pair of transistors(the total current of additional current followers 410, 411 corresponding to the currents of input devices 303, 304, produces a voltage drop across series resistor 601; ¶[0050]).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to further modify Sevenhans in view of Danyuk to couple Danyuk’s first sense resistor as part of the reference-current and feedback arrangement in order to “suitably compensate variation of the differential input stage currents with input signal” (¶[0047], lines 3-4).
Regarding claim 16. Sevanhans, in the figure, discloses the method of claim 9, wherein coupling the transistor with the differential pair of transistors includes: coupling a field-effect transistor with a differential pair of field-effect transistors (M3 coupled with M1/M2; M3, M1 and M2 are NMOS field-effect transistors, column 4, lines 25-29).
Claims 4 is rejected under 35 U.S.C. 103 as being unpatentable over
Sevenhans et al (US Patent Number 5283535) in view of Danyuk (WO-2017192700-A1).
as applied to claim 1 above, and further in view of Renirie et al. (US-3989959-A).
Regarding claim 4: Sevenhans in combination with Danyuk does not disclose a second sense resistor coupled with the reference current source, wherein the second sense resistor is configured to generate the representation of the reference current.
Renirie, Fig. 4, discloses a second sense resistor (resistor 65) coupled with the reference current source (FET 61 and resistor 62 current source), wherein the second sense resistor is configured to generate the representation of the reference current (the output of the current source is connected to resistor 65, such that current supplied by the current source through resistor 65 produces a voltage corresponding to that current; column 5, lines 1-7; column 7, lines 17-23).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to further modify the amplifier circuit of Sevenhans in view of Danyuk to include Renirie’s second sense resistor coupled with the reference current source in order to provide a desired division of current and establish the desired bias voltage.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over
Sevenhans et al (US Patent Number 5283535) in view of Danyuk (WO-2017192700-A1)
as applied to claim 1 above, and further in view of Jansson (US 2011/0204978 A1).
Regarding claim 5: Sevenhans in view of Danyuk discloses the amplifier circuit of claim 1, except wherein the differential pair of transistors includes bipolar junction transistors.
Jansson, page 12, paragraph [00111], lines 8 – 17, teaches amplifier implementations utilizing bipolar junction transistors in place of MOS transistor implementations.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the
invention was effectively filed to further modify Sevenhans in view of Danyuk to include bipolar
junction transistors as taught by Jansson since all the claimed elements were known in the prior art and
one skilled in the art could have substituted the elements as claimed by known methods with no change
in their respective functions, yielded nothing predictable results. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385).
Claims 7, 8 are rejected under 35 U.S.C. 103 as being unpatentable over
Sevenhans et al (US Patent Number 5283535) in view of Danyuk (WO-2017192700-A1)
as applied to claim 1 above, and further in view of Li et al. (US 2017/0359119 A1).
Regarding claim 7: Sevenhans further discloses, in the figure, the amplifier circuit of claim 1, including, wherein the differential pair of transistors (M1/M2), (column 4, lines 25 – 29) is a first differential pair of transistors, wherein the first differential pair of transistors has a first control terminal to receive a first input signal (VG1) and a second control terminal to receive a second input signal (VG2), and wherein the summed current is a first summed current (VS node), the amplifier circuit further comprising: a second pair of transistors (M8/M9) having a first control terminal (VG1)coupled with the first control terminal of the first differential pair of transistors (M1)and a second control terminal (VG2) coupled with the second control terminal of the first differential pair of transistors (M2), the first control terminal (VG1) of the second pair of transistors (M8) to receive the first input signal and the second control terminal (VG2) of the second pair of transistors (M9) to receive the second input signal, wherein the second pair of transistors (M8, M9) is configured and arranged to generate a second summed current from individual ones of the second pair of transistors. Sevenhans discloses transistors M8 and M9 generating node voltages VX and VY through operation of the second pair of transistors. (column 4, lines 35 – 44) and wherein the error correction amplifier (amplifier A) configured to compare the representation of the summed current to the representation of the reference current (column 4, lines 43-48).
However, Sevenhans in combination with Danyuk does not disclose compare a representation of the first summed current to a sum of the representation of the reference current and the second summed current.
Li, figure 7, teaches using outputs from both slicers (130,150) together within a comparative
logic/control process to determine regulation behavior (Li, paragraphs [0041]-[0044],[0054]-[0058])
which corresponds to the claimed comparison using both the reference current representation and the
second summed current representation.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify Sevenhans in view of Danyuk with Li’s comparative multi-signal control teachings in order to detect and reduce errors in signal processing and improve regulation behavior (Li, paragraphs [0036]-[0037], [0041]-[0044]).
Regarding claim 8: Sevenhans in view of Danyuk discloses all of the claim limitations have been discussed with respect to claim 7 above, except for wherein individual ones of the second pair of transistors are replicas of the individual ones of the first differential pair of transistors.
Li, figure 7, discloses corresponding parallel slicer structures (130,150) receiving corresponding
signals from the same amplifier output ([0033]-[0038]), which corresponds to replicated parallel
structures operating together as claimed.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to configure replicated parallel transistor structures in Sevenhans in view of Danyuk with Li’s coordinated parallel signal-processing paths in order to provide predictable comparative operation
between multiple amplifier paths.
Claims 12 is rejected under 35 U.S.C. 103 as being unpatentable over
Sevenhans et al (US Patent Number 5283535) in view of Danyuk (WO-2017192700-A1).
as applied to claim 9 above, and further in view of Renirie et al. (US-3989959-A).
Regarding claim 12: Sevenhans in combination with Danyuk does not disclose coupling a second sense resistor with the reference current source to generate the representation of the reference current.
Renirie, Fig. 4, discloses coupling a second sense resistor( resistor 65) with the reference current source (FET 61 and resistor 62 current source) to generate the representation of the reference current(the output of the current source is connected to resistor 65, such that current supplied by the current source through resistor 65 produces a voltage corresponding to that current; column 5, lines 1-7; column 7, lines 17-23).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to further modify the method of Sevenhans in view of Danyuk to include coupling Renirie’s second sense resistor with the reference current source in order to provide a desired division of current and establish the desired bias voltage.
Claims 13, 14 are rejected under 35 U.S.C. 103 as being unpatentable over
Sevenhans et al (US Patent Number 5283535) in view of Danyuk (WO-2017192700-A1)
as applied to claim 9 above, and further in view of Li et al. (US 2017/0359119 A1).
Regarding claim 13: Sevenhans in view of Danyuk discloses the method of claim 9 as discussed above. Sevenhans further discloses, in the figure, wherein the differential pair of transistors (M1/M2), (column 4, lines 25 – 29) is a first differential pair of transistors, wherein the first differential pair of transistors has a first control terminal to receive a first input signal (VG1) and a second control terminal to receive a second input signal (VG2), and wherein the summed current is a first summed current (VS node), the method further comprising: coupling a second pair of transistors (M8/M9) having a first control terminal (VG1) with the first control terminal of the first differential pair of transistors (M1); coupling a second control terminal (VG2) with the second control terminal of the first differential pair of transistors (M2); the first control terminal (VG1) of the second pair of transistors (M8) to receive the first input signal and the second control terminal (VG2) of the second pair of transistors (M9) to receive the second input signal; wherein the second pair of transistors (M8, M9) is configured and arranged to generate a second summed current from individual ones of the second pair of transistors. Sevenhans further discloses second transistor pair M8 and M9 generating node voltages VX and VY, wherein VX and VY represent signal output generated responsive to operation of the second transistor pair, through operation of the second pair of transistors. (column 4, lines 35 – 44) and wherein the error correction amplifier (amplifier A) configured to compare the representation of the summed current to the representation of the reference current (column 4, lines 43-48).
However, Sevenhans in combination with Danyuk does not disclose comparing a representation of the first summed current to a sum of the representation of the reference current and the second summed current.
Li, figure 7, teaches comparative regulation behavior using outputs from multiple participating
signal paths together within a control process (Li, paragraphs [0041]-[0044],[0054]-[0058]), which
corresponds to the claimed comparison involving both the reference current representation and the
second summed current representation.
It would have been obvious to one having ordinary skill in the art at the time the invention was
effectively filed to apply Li’s comparative multi-signal regulation teachings to the amplifier circuit taught
by Sevenhans in view of Danyuk, in order to improve comparative regulation accuracy using multiple participating signal paths (paragraphs [0041]-[0044], [0057]-[0062]).
Regarding claim 14: Sevenhans in view of Danyuk does not disclose wherein individual ones of the second pair of transistors are replicas of the individual ones of the first differential pair of transistors.
Li, figure 7, teaches individual ones of the second pair of transistors are replicas of the individual
ones of the first differential pair of transistors, which relates to Li’s corresponding parallel signal-
processing paths that receive and process related signals comparatively (paragraphs, [0033]-[0038]).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the
invention was effectively filed to configure replicated corresponding transistor structures within
Sevenhans in view of Danyuk using Li’s corresponding parallel signal-processing paths in order to provide predictable comparative operation between corresponding signal-processing paths.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over
Sevenhans et al (US Patent Number 5283535) in view of Danyuk (WO-2017192700-A1).
as applied to claim 9 above, and further in view of Jansson (US 2011/0204978 A1)
Regarding claim 15: Sevenhans in view of Danyuk discloses the method of claim 9, except wherein coupling the transistor with the differential pair of transistors includes: coupling a bipolar junction transistor with a differential pair of bipolar junction transistors.
Jansson, page 12, paragraph [00111], lines 8 – 17, teaches wherein coupling the transistor with the differential pair of transistors includes: coupling a bipolar junction transistor with a differential pair of bipolar junction transistors.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the
invention was effectively filed to further modify Sevenhans in view of Danyuk to include bipolar
junction transistors as taught by Jansson since all the claimed elements were known in the prior art and
one skilled in the art could have substituted the elements as claimed by known methods with no change
in their respective functions, yielded nothing predictable results. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385).
Claims 17 is rejected under 35 U.S.C. 103 as being unpatentable over
Sevenhans et al (US Patent Number 5283535) and Danyuk (WO-2017192700-A1) in view of
Renirie et al. (US-3989959-A).
Regarding to claim 17: Sevenhans discloses, in the figure, an amplifier circuit comprising: A differential
pair of transistors (M1, M2) configured and arranged to generate a summed current (node VS) from
individual ones of the differential pair of transistors, the differential pair of transistors having a first
control terminal to receive a first input signal (VG1) and a second control terminal to receive a second
input signal (VG2), (Sevenhans, figure, column4, lines 25-34), wherein the differential pair of transistors
is configured and arranged to generate a summed current; a transistor (M3) coupled with the
differential pair of transistors, the transistor having a third control terminal (gate electrode of M3),
(Sevanhans, figure and column 4, lines 25 – 29, and 43-48); an error correction amplifier (amplifier A) having: a non-inverting input (Amplifier A) coupled with the first sense resistor and configured to receive the first voltage generated by the first sense resistor (VS) (column 4, lines 43-48); and an inverting input coupled with the second sense resistor and configured to receive the second voltage generated by the second sense resistor (Vref) (column 4, lines 43-48).
However, Sevenhans does not disclose a first sense resistor coupled with the differential pair of transistors, wherein the first sense resistor is configured to generate a first voltage in response to the summed current from the differential pair of transistors; a reference current source coupled with the transistor and configured to generate a reference current that is fixed and independent of the first input signal and the second input signal; a second sense resistor coupled with the reference current source, wherein the second sense resistor is configured to generate a second voltage in response to the reference current.
Danyuk does disclose a first sense resistor (series resistor 601; ¶[00500]-[0051]) coupled with the differential pair of transistors (input device 303, 304; transistor 602 and resistors 501, 502 couple the current-control circuitry to the sources of transistors 303, 304; ¶[0049]-[0050]), wherein the first sense resistor is configured to generate a first voltage in response to the summed current from the differential pair of transistors (the total current of additional current followers 410, 411 corresponding to the currents of input devices 303, 304, produces a voltage drop across series resistor 601; ¶[0048]-[0051]); Danyuk further discloses a reference current source coupled with the transistor and configured to generate a reference current that is fixed and independent of the first input signal and the second input signal (POWER 2 reference input of current-controlled current source 408; the reference signal is implicitly a fixed reference value independent of INPUT 1 and INPUT2) ¶[0047]-[0048).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the
invention was effectively filed to modify Sevenhans’ amplifier circuit to incorporate Danyuk’s first sense resistor and reference-current arrangement, including coupling the reference-current arrangement with Sevenhans’ transistor M3, in order to “suitably compensate variation of the differential input stage currents with input signal” (¶[0047], lines 3-4).
However, Sevenhans in combination with Danyuk does not disclose a second sense resistor coupled with the reference current source, wherein the second sense resistor is configured to generate a second voltage in response to the reference current.
Renirie discloses second sense resistor (resistor 65) coupled with the reference current source (FET 61 and resistor 62 current source), wherein the second sense resistor is configured to generate a second voltage in response to the reference current (the output of the current source is connected to resistor 65, such that current supplied by the current source through resistor 65 produces a voltage corresponding to that current; column 5, lines 1-7; column 7, lines 17-23).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the
invention was effectively filed to modify Sevenhans’ amplifier circuit to incorporate Danyuk’s first sense resistor and reference-current arrangement and to further incorporate Renirie’s second sense resistor coupled with the reference current source, in order to “suitably compensate variation of the differential input stage currents with input signal” (Danyuk ¶[0047], lines 3-4), while providing a desired division of current and establishing the desired bias voltage (Renirie, column 7, lines 17-23). In the resulting combination, the first voltage generated by Danyuk’s first sense resistor would be received the non-inverting input of Sevenhan’s amplifier A, and the second voltage generated by Renirie’s second sense resistor would be received at the inverting input of Sevenhans’ amplifier A, consistent with Sevenhans’ comparison of (VS) at the non-inverting input and (Vref) at the inverting input (column 4, lines 43-48).
Claims 18, 19 are rejected under 35 U.S.C. 103 as being unpatentable over
Sevenhans et al (US Patent Number 5283535) and Danyuk (WO-2017192700-A1) in view of
Renirie et al. (US-3989959-A) as applied to claim 17 above, and further in view of
Li et al. (US 2017/0359119 A1).
Regarding claim 18: Sevenhans in view of Danyuk and Renirie discloses the amplifier circuit of claim 17 as discussed above. Sevenhans further discloses the differential pair of transistors (M1/M2), (column 4, lines 25 – 29) is a first differential pair of transistors, wherein the first differential pair of transistors has a first control terminal to receive a first input signal (VG1) and a second control terminal to receive a second input signal (VG2), and wherein the summed current is a first summed current (VS node), the amplifier circuit further comprising: a second pair of transistors (M8/M9) having a first control terminal (VG1) with the first control terminal coupled the first differential pair of transistors (M1) and a second control terminal (VG2) coupled with the second control terminal of the first differential pair of transistors (M2), the first control terminal (VG1) of the second pair of transistors (M8) to receive the first input signal and the second control terminal (VG2) of the second pair of transistors (M9) to receive the second input signal, wherein the second pair of transistors (M8, M9) is configured and arranged to generate a second summed current from individual ones of the second pair of transistors (the second transistor pair M8 and M9 generating node voltages VX and VY responsive to operation of the second pair of transistors, wherein VX and VY represent signal outputs corresponding to operation of the second transistor pair), and where in the error correction amplifier (amplifier A) is configured to compare the representation of the summed current to the representation of the reference current (column 4, lines 43-48).
However, Sevenhans in combination with Danyuk and Renirie does not disclose comparing a representation of the first summed current to a sum of the representation of the reference current and the second summed current.
Regarding claim 19: Sevenhans in view of Danyuk and Renirie disclose the amplifier circuit of claim 18 as discussed above, except for wherein individual ones of the second pair of transistors are replicas of the individual ones of the first differential pair of transistors.
Li, figure 7, discloses corresponding parallel slicer structures (130, 150) receiving corresponding
signals from the same amplifier output (¶[0033]-[0038]), which corresponds to replicated parallel structures operating together as claimed.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to configure the individual ones of Sevenhans’ second pair of transistors as replicas of the individual ones of the first differential pair of transistors, in view of Li’s coordinated parallel signal-processing paths, in order to provide predictable comparative operation between multiple amplifier paths.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over
Sevenhans et al (US Patent Number 5283535) in view of Danyuk (WO-2017192700-A1) further in view of Renirie et al. (US-3989959-A) as applied to claim 17 above, and further in view of
Jansson (US 2011/0204978 A1)
Regarding claim 20: Sevenhans in view of Danyuk and Renirie discloses the amplifier circuit of claim 17 as discussed above, except wherein the differential pair of transistors includes bipolar junction transistors.
Jansson, page 12, paragraph [00111], lines 8 – 17, discloses wherein the differential pair of transistors includes bipolar junction transistors.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the
invention was effectively filed to further modify the amplifier circuit of Sevenhans as modified by Danyuk and Renirie to include bipolar junction transistors as taught by Jansson, since bipolar transistor
differential pairs were known alternatives to MOS differential pairs and could be substituted using known methods, yielding predictable results.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to /NATASHA Y MARANO/ whose telephone number is (571)272-9512. The examiner can normally be reached Mon - Fri 7:30am - 3:30pm.
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/NATASHA Y MARANO/Examiner, Art Unit 2843
/Jessica Han/Supervisory Patent Examiner, Art Unit 2843
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