DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see pages 5-6, filed 4/22/26, with respect to the rejection(s) of claim(s) 1 and 9 under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Dong et al. (US 2022/0155526 A1).
Applicant’s arguments, see 6-7, filed 4/22/26, with respect to the rejection(s) of claim(s) 16 under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Dong et al. (US 2022/0155526 A1) and Amano et al. (US 11,611,004 B2).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 5-13, and 15 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Dong et al. (US 2022/0155526 A1).
Re. Claims 1 and 9, Dong et al. discloses an apparatus comprising:
a substrate or interposer 10 (Figs. 1A-1B; [0021]);
an optical module 20 coupled to the substrate 10, the optical module comprising a photonic integrated circuit (PIC) 40 and electronic integrated circuit (EIC) 30, the EIC 30 being coupled to the PIC 40 via the substrate 10 (Figs. 2A-2B; [0026]); and
a fiber optic coupler 50 coupled to the substrate 10 and/or the optical module 20, wherein the PIC 40 is configured to transmit or receive an optical signal via the fiber optic coupler 50 (Figs. 2A-2B; [0031]);
wherein the PIC 40 and the EIC 30 are coupled to a top side of the substrate 10, the PIC 40 and the EIC 30 being not stacked and separated on the top side of the substrate 10 (Fig. 2B).
Re. Claim 5, Dong et al. discloses an arrangement wherein the PIC 40 is at least partially embedded within the substrate 10 (Fig. 5A; [0040]).
Re. Claim 6, Dong et al. discloses the EIC 30 is coupled to the PIC 40 via a solder bump 34 (Fig. 2B; [0027]).
Re. Claim 7, Dong et al. discloses the EIC 30 comprises at least one of a control circuitry, a power circuitry, an electronic amplifier, a filter, and a converter ([0024]).
Re. Claim 8, Dong et al. discloses the substrate 10 comprises a glass core ([0023]), and the PIC 40 is embedded in the glass core (Fig. 5A; [0040]).
Re. Claim 10, Dong et al. discloses the interposer 10 is configured to provide an electrical interconnect between the PIC 40 and the EIC 30 (Fig. 2B; [0024]).
Re. Claim 11, Dong et al. discloses the PIC 40 and the EIC 30 are located on opposite sides of the interposer 10 (e.g., left side versus right side; Figs. 2A-2B).
Re. Claim 12, Dong et al. discloses the PIC 40 and the EIC 30 are located on a same side of the interposer 10 (e.g., both locat3ed on the top side; Figs. 2A-2B).
Re. Claim 13, Dong et al. discloses the PIC 40 is at least partially embedded within the interposer 10 (Fig. 5A; [0040]).
Re. Claim 15, Dong et al. discloses the EIC 30 is coupled to the PIC 40 via a solder bump 34 (Fig. 2B; [0027]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dong et al. (US 2022/0155526 A1).
Re. Claim 2, Dong et al. discloses the apparatus as discussed above, including an embodiment where the PIC 40 is partially embedded in the substrate 10 (Fig. 5A). However, Dong et al. does not disclose an arrangement wherein the EIC is at least partially embedded within the substrate.
The claimed arrangement would have been obvious to one of ordinary skill in the art before the effective filing date of the current invention for the purpose of providing desired alignment of the EIC on the substrate, as Dong et al. discloses embedding a component in the substrate through the use of a trench provides alignment to the component positioned in the trench (Dong et al.: [0040]).
Re. Claim 14, Dong et al. discloses the apparatus as discussed above. Dong et al. also discloses an application specific integrated circuit (ASIC) 104 coupled to the interposer 10 (Fig. 6; [0044]). However, Dong et al. does not disclose the ASIC being a high-bandwidth memory (HBM).
High-bandwidth memory chips are known in the prior art, and one of ordinary skill would have found the claimed arrangement obvious before the effective filing date of the current invention for the purpose of providing high-performance computing and graphics applications. All the claimed elements were known in the prior art, and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc., 550 USPQ2d 1385 (2007).
Claim(s) 3-4 and 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dong et al. (US 2022/0155526 A1) and Amano et al. (US 11,611,004 B2).
Re. Claims 3 and 16, Dong et al. discloses an apparatus comprising:
a substrate 10 comprising a first side and a second side (Figs. 1A-1B; [0021]);
an optical module 20 coupled to the substrate 10, the optical module comprising a photonic integrated circuit (PIC) 40 and electronic integrated circuit (EIC) 30, the EIC 30 being coupled to the PIC 40 via the substrate 10 (Figs. 2A-2B; [0026]); and
a fiber optic coupler 50 coupled to the substrate 10, wherein the PIC 40 is configured to transmit or receive an optical signal via the fiber optic coupler 50 (Figs. 2A-2B; [0031]);
wherein the PIC 40 is coupled to the EIC 30 through copper traces 11 of a router layer, the router layer being positioned in the substrate 10 (Fig. 2B; [0021]).
However, Dong et al. does not disclose through-hole vias in the routing layer and coupled to the PIC.
Amano discloses an apparatus 10 comprising a substrate 100/300, PIC 200, and EIC 400, wherein the PIC 200 is coupled to the EIC 400 through copper traces 310 in the substrate 100/300, and a fiber optic coupler 500 coupled to the substrate 100/300 such that the PIC 200 communicates optical signals to/from the coupler 500 (Fig. 2; col. 2 lines 21-25; col. 5 lines 57-59; col. 6 lines 12-15, 32-33, 42-43). Amano also discloses the substrate 100/300 also comprises through vias 320 coupled to the PIC 200 (Fig. 2B; col. 6 lines 32-41).
The claimed arrangement would have been obvious to one of ordinary skill in the art before the effective filing date of the current invention, as Amano discloses the through hole vias provide enhanced alignment between the PIC and the fiber coupler having improved accuracy (Amano: col. 1 lines 50-59).
Re. Claim 4, Dong et al. and Amano renders obvious the apparatus as discussed above. In addition, Amano discloses the substrate 100/300 further comprises a waveguide positioned within the through-hole via 320, and the waveguide is in optical communication with the PIC 200 (Fig. 2B; col. 6 lines 32-41). The claimed arrangement would have been obvious to one of ordinary skill in the art before the effective filing date of the current invention, as Amano discloses the through hole vias provide enhanced alignment between the PIC and the fiber coupler having improved accuracy (Amano: col. 1 lines 50-59).
Re. Claim 17, Dong et al. and Amano renders obvious the apparatus as discussed above. In addition, Amano discloses the PIC 200 is coupled to the first side of the substrate 100/300, specifically portion 300, the EIC 400 is coupled to the second side of the substrate 100/300, specifically portion 300, and the second side is opposite of the first side (e.g., top side versus bottom side of portion 300; Fig. 2B). The claimed arrangement would have been obvious to one of ordinary skill in the art before the effective filing date of the current invention, as Amano discloses the through hole vias provide enhanced alignment between the PIC and the fiber coupler having improved accuracy (Amano: col. 1 lines 50-59).
Re. Claim 18, Dong et al. and Amano renders obvious the apparatus as discussed above. However, Dong et al. does not disclose an arrangement wherein the EIC is at least partially embedded within the substrate.
The claimed arrangement would have been obvious to one of ordinary skill in the art before the effective filing date of the current invention for the purpose of providing desired alignment of the EIC on the substrate, as Dong et al. discloses embedding a component in the substrate through the use of a trench provides alignment to the component positioned in the trench (Dong et al.: [0040]).
Re. Claim 19, Dong et al. and Amano renders obvious the apparatus as discussed above. In addition, Amano discloses the PIC 200 is at least partially embedded within the substrate 100/300, specifically portion 100 (Fig. 2). The claimed arrangement would have been obvious to one of ordinary skill in the art before the effective filing date of the current invention, as Amano discloses the arrangement provides enhanced alignment between the PIC and the fiber coupler (Amano: col. 1 lines 50-59).
Re. Claim 20, Dong et al. and Amano renders obvious the apparatus as discussed above. Dong et al. discloses the EIC 30 comprises at least one of a control circuitry, a power circuitry, an electronic amplifier, a filter, and a converter ([0024]). The claimed arrangement would have been obvious to one of ordinary skill int eh art before the effective filing date of the current invention for the reasons discussed above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See the attached PTO-892.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to R. PEACE whose telephone number is (571)272-8580. The examiner can normally be reached 9-5 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached at (571) 272-2397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RHONDA S PEACE/Primary Examiner, Art Unit 2874 5/27/26
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