DETAILED ACTION
Response to Amendment
Applicant’s amendment, filed 04/27/26, for application number 18/415,595 has been received and entered into record. Claims 1 and 6 have been amended, Claims 3 and 8 were previously cancelled, and Claims 2 and 7 have been newly cancelled. Therefore, Claims 1, 4-6, 9, and 10 are presented for examination.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 5, 6, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Poss, US 2019/0302831 A1, in view of Shikata et al., US 2002/0159326 A1, and further in view of Applicant’s Admitted Prior Art (AAPA).
Regarding Claim 1, Poss discloses a method for performing clock compensation in a communication device [preamp circuitry 20, Fig. 2B], comprising:
determining a frequency difference between a source operating clock of a first circuit and a target operating clock of second circuit within the communication device [the frequency of the preamp clock 26 may be measured relative to the frequency of the system clock 30, par 14];
obtaining a compensated time by counting cycles of the adjusted operating clock, wherein a number of cycles of the adjusted operating clock accumulated over a time period corresponds to a number of cycles of the target operating clock over the time period, such that the compensated time corresponds to time calculated based on the target operating clock [the system circuitry is further configured to generate the frequency adjustment command based on a difference between a target count value and the counted number of cycles of the system clock; that is, the frequency is adjusted (i.e. clock synchronization) towards a target frequency (compensated time) based on system clock cycles (which would necessarily occur over a period of time), par 14; claim 6].
However, Poss does not explicitly teach the communication device including a physical layer circuit, a medium access control layer circuit, and a precision time protocol (PTP) processing circuit coupled between the physical layer circuit and the medium access control layer circuit; based on the frequency difference, masking selected rising edges of the source operating clock to generate an adjusted operating clock; and performing a clock synchronization process based on PTP according to the compensated time.
In the analogous art of clock generation, Shikata teaches based on the frequency difference, masking selected rising edges of the source operating clock to generate an adjusted operating clock [the clock enable signal DCKE is set in ON state or OFF state depending on a result of comparison of the frequency of an internal clock CK_A, and the frequency of an internal clock CK_C. When the clock enable signal DCKE is set in OFF state (when the logic level of the DCKE is set to the low level), the clock signal DCLK, received from the processor 100, is masked so as to produce a modified clock frequency, and the masked clock signal DCLK is supplied to the internal circuits of the SDRAM 200; The internal clock CK_C is a clock signal that is used to generate the clock signal DCLK to be supplied to the SDRAM 200; i.e. based on the frequency difference between internal clocks CK_A and CK_C, internal clock signal DCLK is masked to produce a modified clock frequency, with CK_C used to generate CLK, par 29, 35]
It would have been obvious to one of ordinary skill in the art, having the teachings of Poss and Shikata before him before the effective filing date of the claimed invention, to incorporate the clock masking based on frequency difference as taught by Shikata into the method as disclosed by Poss, to allow for data synchronization if the clock speed of a controlling module is slower than the clock speed of the controlled module [Shikata, par 11].
However, the combination of references does not explicitly teach the communication device including a physical layer circuit, a medium access control layer circuit, and a precision time protocol (PTP) processing circuit coupled between the physical layer circuit and the medium access control layer circuit; and performing a clock synchronization process based on PTP according to the compensated time.
AAPA teaches the communication device including a physical layer circuit, a medium access control layer circuit, and a precision time protocol (PTP) processing circuit coupled between the physical layer circuit and the medium access control layer circuit [generally, a circuit responsible for processing PTP (e.g., a PTP processing circuit), which is disposed between Medium Access Control (MAC) layer and Physical (PHY) layer, is tasked with adding timestamps into packets (at the transmitting end), or correcting time based on timestamps extracted from received packets (at the receiving end), par 3]; and performing a clock synchronization process based on PTP according to the compensated time [Precision Time Protocol (PTP) is a protocol employed for synchronizing clocks of different nodes in a communication system, thereby to cater to application scenarios requiring high-precision clock synchronization, par 2].
It would have been obvious to one of ordinary skill in the art, having the teachings of Poss, Shikata, and AAPA before him before the effective filing date of the claimed invention, to incorporate the PTP processing circuit as taught by AAPA into the method as disclosed by Poss and Shikata, to allow for use of the high-precision synchronization available through use of PTP in a communication device without modifying the circuit architecture [AAPA, par 2, 3].
Regarding Claim 5, Poss, Shikata, and AAPA disclose the method of Claim 1. AAPA further discloses wherein the step of performing the clock synchronization process based on the precision time protocol according to the compensated time comprises: adding a timestamp based on the compensated time into a packet between a physical layer circuit and a medium access control layer circuit of the communication device for the clock synchronization process [nodes interact with each other through PTP messages containing timestamps, such as Sync, Follow_Up, Delay_Req and Delay_Resp. By exchanging these messages between nodes, a receiving end can calibrate its clock; a circuit responsible for processing PTP (e.g., a PTP processing circuit), which is disposed between Medium Access Control (MAC) layer and Physical (PHY) layer, is tasked with adding timestamps into packets (at the transmitting end), or correcting time based on timestamps extracted from received packets (at the receiving end), par 2, 3].
Regarding Claim 6, Poss discloses a communication device [preamp circuitry 20, Fig. 2B], comprising: a clock compensation circuit [control unit of preamp circuitry 20 which receives instructions from control unit of system circuitry 22 to perform the steps of Fig. 3A].
The remainder of Claim 6 repeats the same limitations as recited in Claim 1, and is rejected accordingly.
Regarding Claim 10, Poss, Shikata, and AAPA disclose the communication device of Claim 6. Claim 10 repeats the same limitations as recited in Claim 5, and is rejected accordingly.
Claims 4 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Poss, Shikata, and AAPA, and further in view of Mangano et al., US 2016/0246324 A1.
Regarding Claim 4, Poss, Shikata, and AAPA disclose the method of Claim 1. AAPA further discloses performing a calibration process based on a local time and an absolute time to obtain the compensated time [nodes interact with each other through PTP messages containing timestamps, such as Sync, Follow_Up, Delay_Req and Delay_Resp. By exchanging these messages between nodes, a receiving end can calibrate its clock, par 2].
However, the combination of references does not explicitly teach based on the frequency difference, determining a time period representing an interval after which the source operation clock and the target operation clock align; and upon expiration of the time period, performing a calibration process.
In the analogous art of calibration, Mangano teaches based on the frequency difference, determining a time period representing an interval after which the source operation clock and the target operation clock align; and upon expiration of the time period, performing a calibration process [aligning the clocks at subsequent calibration times (time period) based on the difference between the frequency of the first clock and second clock, par 8].
It would have been obvious to one of ordinary skill in the art, having the teachings of Poss, Shikata, AAPA, and Mangano before him before the effective filing date of the claimed invention, to incorporate the calibration after alignment as taught by Mangano into the method as disclosed by Poss, Shikata, and AAPA to ensure accurate timekeeping while providing energy efficiency and battery duration [Mangano, par 3].
Regarding Claim 9, Poss, Shikata, and AAPA disclose the communication device of Claim 6. Claim 9 repeats the same limitation as recited in Claim 4, and is rejected accordingly.
Response to Arguments
Applicant’s arguments filed 04/27/26 have been considered but are moot due to the new rejection based on the references cited above, as well as the newly cited portions of the references previously presented.
Applicant's arguments as to Poss and Shikata have been fully considered but they are not persuasive.
Applicant argues Poss does not disclose the limitation of masking selected rising edges and obtaining a compensated time as required by Claim 1.
Specifically, Applicant argues Claim 1 requires masking selected rising edges of the source operating clock to generate an adjusted operating clock, and then obtaining a compensated time by counting cycles of that adjusted operating clock such that the compensated time corresponds to time calculated based on the target operating clock, and that Poss does not disclose such features.
However, Applicant appears to be arguing against the references individually, and one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Examiner notes the rejection, similar to the rejection previously presented, does not rely upon Poss alone for such a disclosure, but instead relies upon Shikata for the teachings of masking selected risking edges, and only relies upon Poss for obtaining a compensated time by counting cycles.
As to Shikata, Applicant argues Claim 1 requires masking selected rising edges of the source operating clock to generate an adjusted operating clock, and then obtaining a compensated time by counting cycles of the adjusted operating clock, and that Shikata also does not disclose using a masked clock to generate a compensated time that corresponds to time calculated based on a different target operating clock.
Similar to Poss, Examiner notes the rejection does not rely upon Shikata alone for the teaching being argued here, but instead relies upon a combination of references, including Poss and AAPA, to address the portions of the limitations not taught by Shikata. Poss is relied upon to disclose a first clock and target clock, the frequency difference between the clocks, as well as a compensated time.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL J YEN whose telephone number is (571)270-5047. The examiner can normally be reached M-F 8-5 PT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J Jung can be reached at (571) 270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Paul Yen/Primary Examiner, Art Unit 2175
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