DETAILED ACTION
Response to Amendment
Applicant’s amendment, filed 11/14/25, for application number 18/415,595 has been received and entered into record. Claims 1 and 6 have been amended, and Claims 3 and 8 have been cancelled. Therefore, Claims 1, 2, 4-7, 9, and 10 are presented for examination.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 6, and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Poss, US 2019/0302831 A1, in view of Shikata et al., US 2002/0159326 A1, and further in view of Matsumoto, US 2022/0345290 A1.
Regarding Claim 1, Poss discloses a method for performing clock compensation in a communication device [preamp circuitry 20, Fig. 2B], comprising:
determining a frequency difference between a source operating clock of a first circuit and a target operating clock of second circuit within the communication device [the frequency of the preamp clock 26 may be measured relative to the frequency of the system clock 30, par 14];
performing clock compensation according to the frequency difference by generating an adjusted operating clock through modification of the source operating clock, thereby obtaining a compensated time, wherein the compensated time is obtained based on a number of cycles of the adjusted operating clock [the frequency of the preamp clock 26 adjusted toward a target frequency; the system circuitry is further configured to generate the frequency adjustment command based on a difference between a target count value and the counted number of cycles of the system clock; that is, the frequency is adjusted (i.e. clock synchronization) towards a target frequency (compensated time) based on system clock cycles, par 14; claim 6].
However, Poss does not explicitly teach based on the frequency difference, masking specific rising edges of the source operating clock to obtain an adjusted operating clock and obtaining the compensated time based on the adjusted operating clock; and performing a clock synchronization process based on a precision time protocol according to the compensated time.
In the analogous art of clock generation, Shikata teaches based on the frequency difference, masking specific rising edges of the source operating clock to obtain an adjusted operating clock and obtaining the compensated time based on the adjusted operating clock [the clock enable signal DCKE is set in ON state or OFF state depending on a result of comparison of the frequency of an internal clock CK_A, which will be described later, and the frequency of an internal clock CK_C, which will be described later. When the clock enable signal DCKE is set in OFF state (when the logic level of the DCKE is set to the low level), the clock signal DCLK, received from the processor 100, is masked so as to produce a modified clock frequency, and the masked clock signal DCLK is supplied to the internal circuits of the SDRAM 200; The internal clock CK_C is a clock signal that is used to generate the clock signal DCLK to be supplied to the SDRAM 200; i.e. based on the frequency difference between internal clocks CK_A and CK_C, internal clock signal DCLK is masked to produce a modified clock frequency, with CK_C used to generate CLK, par 29, 35].
It would have been obvious to one of ordinary skill in the art, having the teachings of Poss and Shikata before him before the effective filing date of the claimed invention, to incorporate the clock masking based on frequency difference as taught by Shikata into the method as disclosed by Poss, to allow for data synchronization if the clock speed of a controlling module is slower than the clock speed of the controlled module [Shikata, par 11].
However, the combination of references does not explicitly teach performing a clock synchronization process based on a precision time protocol according to the compensated time.
In the analogous art of time synchronization, Matsumoto teaches performing a clock synchronization process based on a precision time protocol according to the compensated time [according to PTP, a leader device having an accurate time transmits a PTP packet carrying information of the time. A follower device performs time synchronization by receiving the PTP packet, par 3].
It would have been obvious to one of ordinary skill in the art, having the teachings of Poss, Shikata, and Matsumoto before him before the effective filing date of the claimed invention, to incorporate the synchronization as taught by Bedrosian into the method as disclosed by Poss and Shikata, as the method of PTP synchronization is well-known and allows for accurate time synchronization [Matsumoto, par 3].
Regarding Claim 2, Poss, Shikata, and Matsumoto disclose the method of Claim 1. Poss further discloses a source operating clock and target operating clock [system clock 30 and premp clock 26, Fig. 2B], and Matsumoto further teaches an operating clock of a physical layer circuit of the communication device, and an operating clock of a medium access control layer circuit, respectively [the PHY/MAC interface 26 of camera adapters performs communication control on the physical (PHY) layer and the media access control (MAC) layer (data link layer) in communication; that is, clocks (PTP packets containing time info) are obtained through the PHY/MAC interface, Fig. 2; par 61, 62].
Regarding Claim 6, Poss discloses a communication device [preamp circuitry 20, Fig. 2B], comprising: a clock compensation circuit [control unit of preamp circuitry 20 which receives instructions from control unit of system circuitry 22 to perform the steps of Fig. 3A]. The remainder of Claim 6 repeats the same limitations as recited in Claim 1, and is rejected accordingly.
Matsumoto further teaches a precision time protocol (PTP) processing circuit [camera adapter 2 operates as a PTP leader device, Fig. 1; par 38].
It would have been obvious to one of ordinary skill in the art, having the teachings of Poss, Shikata, and Matsumoto before him before the effective filing date of the claimed invention, to incorporate the PTP processing as taught by Matsumoto into the method as disclosed by Poss and Shikata, to allow for data communication and synchronization [Matsumoto, par 58-65].
Regarding Claim 7, Poss, Shikata, and Matsumoto disclose the communication device of Claim 6. Claim 7 repeats the same limitations as recited in Claim 2, and is rejected accordingly.
Claims 4 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Poss, Shikata, and Matsumoto, and further in view of Mangano et al., US 2016/0246324 A1.
Regarding Claim 4, Poss, Shikata, and Matsumoto disclose the method of Claim 1. Matsumoto further discloses performing a calibration process based on a local time and an absolute time to obtain the compensated time [the camera adapter 2 performs time synchronization using a PTP packet from the GMC device and a PTP packet transferred from another sensor system 3, par 40, 139, 151].
However, the combination of references does not explicitly teach based on the frequency difference, determining a time period representing an interval after which the source operation clock and the target operation clock align; and upon expiration of the time period, performing a calibration process.
In the analogous art of calibration, Mangano teaches based on the frequency difference, determining a time period representing an interval after which the source operation clock and the target operation clock align; and upon expiration of the time period, performing a calibration process [aligning the clocks at subsequent calibration times (time period) based on the difference between the frequency of the first clock and second clock, par 8].
It would have been obvious to one of ordinary skill in the art, having the teachings of Poss, Shikata, Matsumoto, and Mangano before him before the effective filing date of the claimed invention, to incorporate the calibration after alignment as taught by Mangano into the method as disclosed by Poss, Shikata, and Matsumoto to ensure accurate timekeeping while providing energy efficiency and battery duration [Mangano, par 3].
Regarding Claim 9, Poss, Shikata, and Matsumoto disclose the communication device of Claim 6. Claim 9 repeats the same limitation as recited in Claim 4, and is rejected accordingly.
Claims 5 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Poss, Shikata, and Matsumoto, and further in view of Horn et al., US 2020/0351189 A1.
Regarding Claim 5, Poss, Shikata, and Matsumoto disclose the method of Claim 1. Matsumoto further discloses wherein the step of performing the clock synchronization process based on the precision time protocol according to the compensated time comprises: adding a timestamp based on the compensated time into a packet [the PHY/MAC interface 26 further outputs reception timestamps of all received communication packets. The term “timestamp” herein refers to time information about a timing at which the PHY/MAC interface 26 transmits or receives a communication packet. The timestamps are used in calculation for time correction in PTP protocol processing; PTP packets carry time information (time correction is performed on the time information contained within PTP packets), par 62, 29].
However, the combination of references does not explicitly teach adding a timestamp into a packet between a physical layer circuit and a medium access control layer circuit of the communication device for the clock synchronization process.
In the analogous art of synchronization, Horn teaches adding a timestamp into a packet between a physical layer circuit and a medium access control layer circuit of the communication device for the clock synchronization process [timestamp insertion between MAC 108 and PHY 114 at media independent interface (MII) 112, Fig. 1B; par 143, 181].
It would have been obvious to one of ordinary skill in the art, having the teachings of Poss, Shikata, Matsumoto, and Horn before him before the effective filing date of the claimed invention, to incorporate the adding of a timestamp as taught by Horn into the method as disclosed by Poss, Shikata, and Matsumoto to allow for fault tolerant synchronization through the use of timestamps [Horn, par 3].
Regarding Claim 10, Poss, Shikata, and Matsumoto disclose the communication device of Claim 6. Claim 10 repeats the same limitations as recited in Claim 5, and is rejected accordingly.
Response to Arguments
Applicant’s arguments filed 11/14/25 have been considered but are moot due to the new rejection based on the references cited above, as well as the newly cited portions of the references previously presented.
Conclusion
Applicant is reminded that in amending a response to a rejection of claims, the patentable novelty must be clearly shown in view of the state of the art disclosed by the references cited and the objections made. Applicant must also show how the amendments avoid such references and objections. See 37 CFR §1.111(c).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL J YEN whose telephone number is (571)270-5047. The examiner can normally be reached M-F 8-5 PT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J Jung can be reached at (571) 270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Paul Yen/Primary Examiner, Art Unit 2175