DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendments filed on 7/5/2026 have been entered. Claims 1, 3-11, and 13-20 remain pending. Claims 2 and 12 were cancelled.
Response to Arguments
Applicant’s arguments regarding Claim 1 have been fully considered and are persuasive. Therefore, the prior art rejections of Claims 1 and 3-8 have been withdrawn.
Applicant’s arguments regarding Claim 9 have been fully considered but are not persuasive. Regarding Claim 9, Applicant argues that the prior art reference Furuyama et al discloses solder bumps 35b and 36b which are different from the electrode of the chip of the power module package structure in the instant application. The examiner disagrees in that in the broadest reasonable interpretation of the electrode, solder bumps can be considered electrodes. Further, although the vertical conductive connector, the conductive layer, and the electrode may not be perfectly aligned with one another in a direction perpendicular to the surface of the substrate, the vertical conductive connectors may still be considered correspondingly attached to a plurality of electrodes on the first chip. In the embodiment shown in Fig 8, Furuyama et al discloses
wherein the first chip (83 Fig 8 and Fig 17) has at least one electrode (electrically conductive bumps 35b and 36b [0060]).
In the broadest reasonable interpretation, being attached to the vertical conductive connectors (417) Fig 17 Furuyama et al, does not have to be directly aligned with or contacting the vertical conductive connectors (417) Fig 17 Furuyama et al. In other words, 35b and 36b provide connection between first chip (83 Fig 17) and element 33 of the power component which would still meet the requirement of being attached. Therefore, the prior art rejections of claims 9-11 and 13 will be maintained.
In the interest of compact prosecution, the examiner notes that further description of the how the electrodes are attached to the vertical conductive connectors would be helpful in overcoming the prior art of record. The examiner is available for an interview at Applicant’s convenience.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 9-11 and 13 are rejected under 35 U.S.C. 102(a)(1) as being are rejected under 35 U.S.C. 103 as being unpatentable over Furuyama et al (US 2005/0230795).
Regarding Claim 9, Furuyama et al discloses a power module package structure (LSI package [0010]), comprising:
a first substrate (first substrate 1a [0110] Fig 17); and
a power component (header base 33 [0110], thermal vias 417 [0110], interface IC chip 83 [0109], heat conductive resin 38 [0109], optical semiconductor chip 93 [0060] Fig 17) located on the first substrate (1a Fig 17),
wherein the power component (33, 417, 83, 38, 93 Fig 17) comprises:
a first chip (83 Fig 17); and
a spacer (33 and 417 Fig 17) connecting the first chip and the first substrate (1a Fig 17),
wherein the spacer (33 and 417 Fig 17) comprises a plurality of vertical conductive connectors (417 Fig 17) and an insulating heat dissipation layer (33 Fig 17),
the insulating heat dissipation layer (header base 33 may be made of an oxide which is insulative [0066]) is located in a heat dissipation space (area where 33 and 417 are located Fig 17) between the first substrate (1a Fig 17) and the first chip (83 Fig 17) and surrounds the vertical conductive connector (417 Fig 17) to electrically isolate the vertical conductive connectors (417 Fig 17), and
the vertical conductive connectors (417 Fig 17) penetrate the insulating heat dissipation layer (33 Fig 17) to be electrically connected to the first chip (83 Fig 17) and the first substrate (1a Fig 17).
Furuyama et al does not directly disclose
wherein the vertical conductive connectors are correspondingly attached to a plurality of electrodes on the first chip.
However, in the embodiment shown in Fig 8, Furuyama et al discloses
wherein the first chip (83 Fig 8 and Fig 17) has at least one electrode (electrically conductive bumps 35b and 36b [0060]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Furuyama et al to include wherein the first chip has at least one electrode as taught by Furuyama et al in order to provide electrical connection between the chip and other elements of the module. Further, a person of ordinary skill in art would have recognized that having electrical connection between the chips and other elements of the module would be advantageous in optimizing electrical functioning of the device (see MPEP 2143.I(D)).
Furuyama et al now discloses
wherein the vertical conductive connectors (417 Fig 17 Furuyama et al) are correspondingly attached to a plurality of electrodes (35b and 36b Fig 8 and Fig 17 Furuyama et al) on the first chip (83 Fig 17 Furuyama et al).
Regarding Claim 10, Furuyama et al discloses the limitations of claim 9 as explained above. Furuyama et al further discloses
wherein the insulating heat dissipation layer (33 Fig 17) is formed by an insulating organic material (may be made of various organic materials [0066]), and the insulating organic material comprises aluminum nitride (may be aluminum nitride ALN [0066]), copper molybdenum, aluminum silicon carbide, aluminum oxide, and silicon nitride, or a combination thereof.
Regarding Claim 11, Furuyama et al discloses the limitations of claim 10 as explained above. Furuyama et al further discloses
wherein the vertical conductive connectors (417 Fig 17) are a plurality of metal pillars (may be formed by a metal paste [0118]).
Regarding Claim 13, Furuyama et al discloses the limitations of claim 9 as explained above. Furuyama et al further discloses
wherein the power component (33, 417, 83, 38, 93 Fig 17) further comprises a second chip (93 Fig 17),
wherein the spacer (33 and 417 Fig 17) is located between the first chip (83 Fig 17) and the second chip (93 Fig 17), and
the first chip (83 Fig 17) is electrically connected and thermally conducted to the second chip (93 Fig 17) through the spacer (33 and 417 Fig 17).
Allowable Subject Matter
Claims 1 and 3-8 are allowable.
Regarding Claim 1, Furuyama et al (US 2005/0230795) discloses a power module package structure (LSI package [0010]), comprising:
a first substrate (first substrate 1a [0110] Fig 17) comprising a surface (top surface of 1a) and at least one conductive layer (interposer-site thermal vias 411 [0110] Fig 17) located on the surface (top surface of 1a); and
a power component (header base 33 [0110], thermal vias 417 [0110], interface IC chip 83 [0109], heat conductive resin 38 [0109], optical semiconductor chip 93 [0060] Fig 17), comprising a first chip (83 Fig 17) and a first spacer (header base 33 and thermal vias 417 Fig 17),
the first spacer (33 and 417 Fig 17) located in a heat dissipation space (area where 33 and 417 are located) between the first substrate (1a Fig 17) and the first chip (83 Fig 17) comprises:
an insulating heat dissipation layer (header base 33 may be made of an oxide which is insulative [0066]) located in the heat dissipation space (area where 33 and 417 are located Fig 17); and
a plurality of vertical conductive connectors (thermal vias 417 [0110] Fig 17),
wherein each of the vertical conductive connectors (417 Fig 17) penetrates the insulating heat dissipation layer (33 Fig 17),
the insulating heat dissipation layer (33 Fig 17) surrounds the vertical conductive connector (417 Fig 17) and electrically isolates the vertical conductive connector (417 Fig 17),
the vertical conductive connector (417 Fig 17) comprises two opposite ends (top and bottom end),
one end (bottom end) is electrically connected to the conductive layer (411 Fig 17).
However, in the embodiment shown in Fig 8, Furuyama et al discloses
wherein the first chip (83 Fig 8 and Fig 17) has at least one electrode (electrically conductive bumps 35b and 36b [0060]).
Furuyama et al now discloses
the vertical conductive connector (417 Fig 17) comprises two opposite ends (top and bottom end),
one end (bottom end) is electrically connected to the conductive layer (411 Fig 17), and the other end (top end) is electrically connected to the electrode (35b and 36b Fig 8 and Fig 17 Furuyama et al) to form a conductive path and a heat dissipation path between the first chip (83 Fig 17 Furuyama et al) and the first substrate (1a Fig 17 Furuyama et al).
The reason for the indication of allowability of Claim 1 is the inclusion of
wherein the vertical conductive connector, the conductive layer, and the at least one electrode are aligned with one another in a direction perpendicular to the surface of the first substrate.
Specifically, Furuyama et al does not disclose these limitations of the claim. Furuyama et al discloses solder bumps 35b and 36b as connected to the edges of component 83 in Fig 8, which would mean that they would not be directly aligned in the vertical direction, which is perpendicular to the surface of the first substrate, in that they would be beside the vertical conductive connectors 417 and not aligned with them. Further, should another reference be found discloses these limitations, it would not be obvious to a person of ordinary skill in the art to combine the references to make this alteration to Furuyama et al.
It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art.
Claims 14-20 are allowable.
Regarding Claim 14, Furuyama et al (US 2005/0230795) discloses a power module package structure (LSI package [0010]), comprising:
a conductive layer (interposer-site thermal vias 411 [0110] Fig 17);
a first substrate (first substrate 1a [0110] Fig 17) located at a position opposite to the conductive layer (411 Fig 17); and
a power component (header base 33 [0110], thermal vias 417 [0110], interface IC chip 83 [0109], heat conductive resin 38 [0109], optical semiconductor chip 93 [0060] Fig 17) located on the first substrate (1a Fig 17) and comprising:
a chip (93 Fig 17) located in a heat dissipation space (area where 33 and 417 are located);
a first spacing portion (33 and 417 Fig 17) adjacent to the chip (93 Fig 17), and comprising a plurality of vertical conductive connectors (thermal vias 417 [0110] Fig 17) electrically connected and an insulating heat dissipation layer (header base 33 may be made of an oxide which is insulative [0066]) surrounding the vertical conductive connectors (417 Fig 17),
wherein the vertical conductive connectors (417 Fig 17) penetrate the insulating heat dissipation layer (33 Fig 17) to form a conductive path between the chip (93 Fig 17) and the first substrate (1a Fig 17); and
wherein the vertical conductive connectors (417 Fig 17) penetrate the insulating heat dissipation layer (33 Fig 17) to form a heat dissipation path between the conductive layer (411 Fig 17) and the chip (93 Fig 17).
The reason for the indication of allowability of Claim 14 is the inclusion of
a chip located between the conductive layer and the first substrate;
at least one pin electrically connected to the chip;
a first spacing portion comprising a plurality of vertical conductive connectors electrically connected to the pin and an insulating heat dissipation layer surrounding the vertical conductive connectors,
a second spacing portion located on the chip, and comprising a plurality of vertical conductive connectors electrically connected to the chip and the conductive layer and an insulating heat dissipation layer surrounding the vertical conductive connectors.
Specifically, the prior art reference Furuyama et al does not disclose these claim limitations and should another reference be found that teaches the limitations, it would not be obvious to a person of ordinary skill in the art to modify Furuyama et al in this manner.
It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Related Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Pagaila et al (US 2011/0068459) which discloses semiconductor devices that vary in number and density of electrical components [0003], and Aketa (US 2020/0144209) which discloses a MISFET transistor that involves a chip [0051-[0052].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID PAUL SEDOROOK whose telephone number is (571)272-4158. The examiner can normally be reached Monday - Friday 7:30 am -5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge can be reached on (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.P.S./Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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