DETAILED ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by S. -H. Shin, P. -H. Lee, J. -W. Park, Y. -J. Hwang and Y. -C. Jang, "0.5 kHz–32 MHz digital fractional-N frequency synthesizer with burst-frequency switch," 2017 IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, MD, USA, 2017, pp. 1-4, doi: 10.1109/ISCAS.2017.8050286 (Shin).
For claim 1, Shin teaches a clock signal noise reduction device (Fig 2 and 6; and sections II to IV), comprising:
a phase generator configured to generate a multi-phase clock signal based on an input signal (Fig 2, VCO ϕ0- ϕ62 and 3; and section II.A);
a phase selector having an input end connected with an output end of the phase generator (Fig 6, phase selector, CLKpll; and section II.B), the phase selector being configured to select a channel of the multi-phase clock signal based on phase information (Fig. 6, MUX0, MUX1, EX_DIGIT[13:8]; and section II.B) and assign a delay of a preset period to a clock signal of the selected channel, (Fig. 6, phase interpolator, EX_DIGIT[7:5]; and section II.B) wherein the preset period is less than a cycle period of the multi-phase clock signal (see, e.g. section II.B); and
a frequency divider having an input end connected to an output end of the phase selector, the frequency divider being configured to perform fractional frequency division on the multi-phase clock signal that is delayed by the preset period to reduce a signal noise (Fig. 6, C-CLK, AND gate, O_CLK, 2k+1 FREQ. DIVIDER, FS_OUT).
For claim 11, Shin teaches a clock signal noise reduction method, comprising:
obtaining a multi-phase clock signal (Fig 6, phase selector, CLKpll; and section II.B);
selecting a channel of the multi-phase clock signal based on phase information and assigning a delay of a preset period to a clock signal of the selected channel (Fig. 6, MUX0, MUX1, EX_DIGIT[13:8]; and section II.B), wherein the preset period is less than a cycle period of the multi-phase clock signal (see, e.g., section II.B); and
performing fractional frequency division on the multi-phase clock signal that is delayed by the preset period to reduce a signal noise (Fig. 6, C-CLK, AND gate, O_CLK, 2k+1 FREQ. DIVIDER, FS_OUT).
Allowable Subject Matter
Claims 2-10 and 12-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM D HOUSTON whose telephone number is (571)270-3901. The examiner can normally be reached M-F 10-7 CST.
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/ADAM D HOUSTON/Primary Examiner, Art Unit 2842