Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to application No. 18415810 filed on 01/18/2024.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Election/Restrictions
Applicants’ election without traverse of (Species 1) claims 1-11 in the reply filed on 8/12/2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-11 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), secondparagraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding independent claim 1, the claim first recites “a substrate having a first main surface on which a recesses is formed” and later it recites through holes formed “from a first main surface”. The second recital of “a first main surface” lacks proper antecedent basis. Appropriate correction is required.
Claims 2-11 are also rejected under 112(b) as they depend from independent claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 3, 7, 8 & 11 are rejected under 35 U.S.C. 102 (a) (2) as being anticipated by Nakamoto et al. (US 2024/0044828 A1).
Regarding independent claim 1, Nakamoto et al. teach a semiconductor package member (fig. 16, elements 2 & 110C [0102] [0118]) comprising:
a substrate (fig. 16, element 10A [0060]) having a first main surface (fig. 16, top surface of element 10A) on which a recess (fig. 16, element 111A [0059]) is formed, wherein
the substrate includes a plurality of through holes (fig. 16, plurality of element 101A [0060]) formed in such a manner as to, from a first main surface,
reach a second main surface (fig. 16, bottom surface of element 10A) opposite to the first main surface (fig. 16),
and at least some of the plurality of through holes are formed at positions overlapping the recess (fig.16).
Regarding claim 2, Nakamoto et al. teach the semiconductor package member, further comprising:
a water-repellent film formed on the first main surface of the substrate (paragraph [0073] discloses a coating layer is applied having a water-repellent function may be provided on the surface of substrate).
Regarding claim 3, Nakamoto et al. teach the semiconductor package member,
wherein the water-repellent film is in contact with at least a portion of inner peripheral surfaces of the through holes and the recess (paragraph [0073] discloses a coating layer having water-repellent function may also be formed on the inner wall of the first through hole element 101 (fig. 1 element 101 [0051] labeled as 101A in fig.16) and the surface of the element 103 (fig. 1, element 103 [0051] which is bottom surface of recess element 111A in fig. 16)).
Regarding claim 7, Nakamoto et al. teach the semiconductor package member, wherein
the recess includes a first recess and a second recess (fig. 16, plurality of element 111A [0060]), on the first main surface, the first recess is formed to extend linearly (fig. 5, element 111 [0051] labeled as 111A in fig.16),
and on the first main surface, the second recess is formed to extend linearly and intersect with the first recess. (fig. 5, element 111 [0051] labeled as 111A in fig.16).
Regarding claim 8, Nakamoto et al. teach the semiconductor package member, wherein
an inner peripheral width (figs. 1, element D1 [0052]) of each of the through holes
(fig. 1, element 101 is labeled as 101A in fig. 16 [0051]) is 0.05 mm or less [0052].
Regarding claim 11, Nakamoto et al. teach semiconductor device comprising:
a semiconductor element (fig. 16, element 3G [0099]);
and the semiconductor package member, which is connected to the semiconductor element (fig. 16 discloses element 3G connected to the elements 2 & 100C by a connecting member element 5 [0108]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 & 9 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamoto et al. (US 2024/0044828 A1) in view of Tanaka et al. (US 2017/0234754 A1).
Regarding claim 4, Nakamoto et al. all the limitations as discussed above.
Nakamoto et al. teach the semiconductor package member, wherein,
the first main surface and the water-repellent film.
Nakamoto et al. do not explicitly teach a contact angle of water with respect to the first main surface and the water-repellent film is 90° or more.
However, Tanaka et al. is a pertinent art which teaches a water repellent treatment of the surface of a waterproof member that the contact angle of water on the surface is, theoretically, approximately 120° [0058].
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package member of Nakamoto et al. to include the first main surface have a contact angle of water is about 120° which is 90° or more as taught by Tanaka et al. since it is possible to accurately control a contact angle of water on the surface, it becomes easy to determine the diameter of the through hole [0058].
Regarding claim 9, Nakamoto et al. as modified by Tanaka et al. teach the semiconductor package member, wherein,
a material of the substrate is silicon ([0055] of Tanaka et al.).
Claims 5 & 6 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamoto et al. (US 2024/0044828 A1).
Regarding claim 5, Nakamoto et al. teach all the limitations as discussed above.
Nakamoto et al. teach the semiconductor package member, wherein,
when a direction perpendicular to the first main surface is defined as a first direction (figs. 2 & 16) and a direction parallel to the first main surface is defined as a second direction (figs. 2 & 16),
Nakamoto et al. do not explicitly teach a width of the recess in the second direction
is 100 μm or less, and a depth of the recess from the first main surface to a bottom surface of the recess in the first direction is equal to or greater than the width.
However, Nakamoto et al. teaches a width (fig. 2, width of element D2A is 100 μm
or more and 200 μm less [0061]) of the recess in the second direction (figs. 2 & 16) [0061],
and a depth (figs. 1, 2 &16, depth of element T2 is 50 μm or more and 200 μm or less [0052]) of the recess from the first main surface (figs. 1, 2 & 16) to a bottom surface of the recess (figs. 1, 2 & 16) in the first direction (figs. 1, 2 & 16) is equal to or greater than the width. The claimed width and depth overlaps Nakamoto’s width and depth. In case where the claimed ranges overlaps or lie inside ranges disclosed by prior art, a prima-facie case of obviousness exist (MPEP 2144.05). Moreover, Nakamoto et al. teaches the first through holes 101A that are finer and have higher waterproof property can keep water from entering [0019] and the thickness of the second layer (fig. 16, element 11A [0060]) “can have a thickness and the number of layers corresponding to the strength required for the substrate” [0056].
Therefore, the width and depth of the recess result effective variable, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package member to vary the width and depth of the recess, through routine optimization. Furthermore, the applicant has not presented persuasive evidence that the claimed width and depth are for particular purposes that is critical to the overall claimed invention (i.e. that the invention would not work without the specific claimed dimensions).
Regarding claim 6, Nakamoto et al. teach all the limitations as discussed above.
Nakamoto et al. teach the semiconductor package member, wherein,
the recess includes a first recess and a second recess (fig. 16, plurality of element 111A [0060]) and, when a direction perpendicular to the first main surface is defined as a first direction, and a direction parallel to the first main surface is defined as a second direction and a width of the first recess in the second direction.
Nakamoto et al. do not explicitly teach a distance from the first recess to the second recess in the second direction is equal to or less than three times a width of the first recess in the second direction.
However, Nakamoto et al. teaches that the positions and the number of the first through holes and the second through holes may be changed as appropriate in accordance with the sensor element to be mounted [0130] and smaller size of the second through hole improves the strength of the semiconductor package [0177].
Therefore, distance from the first recess to the second recess is result effective variable, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package member to employ the distance from the first recess to the second recess is equal to or less than three times a width of the first recess, through routine optimization. Furthermore, the applicant has not presented persuasive evidence that the claimed distance is for particular purposes that is critical to the overall claimed invention (i.e. that the invention would not work without the specific claimed. Furthermore, the applicant has not presented persuasive evidence that the claimed distance are for particular purposes that is critical to the overall claimed invention (i.e. that the invention would not work without the specific claimed dimensions).
Claims 10 is rejected under 35 U.S.C. 103 as being unpatentable over Nakamoto et al. (US 2024/0044828 A1) in view of Tezuka et al. (US 2020/0086283 A1).
Regarding claim 10, Nakamoto et al. teach all the limitations as discussed above.
Nakamoto et al. do not explicitly teach, wherein
a moisture permeability is 100 g/(m2-h) or more.
However, Tezuka et al. is a pertinent which teaches a waterproof air permeable member, a water vapor permeability as measured according to JIS Z 0208 (water vapor permeability test, cup or dish method) is, for example, 9000 g/ (m.sup.2.Math.day) or more [0067].
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package member of Nakamoto et al. to employ a moisture permeability is 100 g/(m2-h) or more as taught by Tezuka et al. in order to “It is desired that the water vapor residing inside the housing be discharged out of the housing as quickly as possible [0004].
Cited Prior Art
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARIFUR RAHMAN whose telephone number is (571) 895-1534. The examiner can normally be reached on Monday-Friday, 9:00 AM - 5:00 PM (Eastern Time). If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571) 270-0373. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at (866) 217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call (800) 786-9199 (IN USA OR CANADA) or (571) 272-1000.
/ARIFUR RAHMAN/
Examiner, Art Unit 2813
/SHAHED AHMED/Primary Examiner, Art Unit 2813
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