DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending for examination.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim language in the following claims is not clearly understood:
As per claim 1, line 10, it is unclear whether “the parallel thread group queue” is referring to one of the “at least parallel thread group queues” in line 6 (i.e. consistent term should be used with “the” or “said” if they are the same)
As per claim 2, line 1, it is unclear whether “a request” is referring to one of “the requests” in claim 1 (i.e. consistent term should be used with “the” or “said” if they are the same)
As per claim 6, line 4, it is unclear whether “a stalled parallel thread” is one parallel threads of the “parallel thread groups” (i.e. consistent term should be used with “the” or “said” if they are the same)
As per claims 11, 12 and 16, they have the same deficiencies as claims 1, 2 and 16. Appropriate corrections are required.
As per claims 2-10, 12-20, they depend from rejected claims and do not resolve the deficiencies thereof and are therefore rejected for at least the same reasons.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 7, 11, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakazawa US Pub 2021/0019183 (hereafter Nakazawa) in view of Govindarajeswaran et al. US Pub 2014/0373020 (hereafter Govindarajeswaran).
As per claim 1, Nakazawa teaches the invention substantially as claimed including an apparatus for offloading parallel computation tasks, comprising: one or more processors; and memory for storing at least one program executed by the one or more processors, wherein the at least one program: inserts requests to execute multiple parallel thread groups into at least one parallel thread group queues, wherein when a preset order of priority exists the requests to execute is inserted into the at least one parallel thread group queues according to the preset order of priority (para[0029, 0032, 0036, 0088-0091, 0097], divide the received task request into subtasks to be executed by corresponding parallel thread groups, and the subtasks are added to high/normal/low priority queues based on its priority, where parallel thread groups are associated with different priority queues);
executes parallel threads of the parallel thread groups using a parallel thread group execution request entry extracted from the parallel thread group queue according to the order of priority (para[0032, 0038-0039, 0088-0091, 0097], execute the subtasks, obtained from a priority queue, using a plurality of threads in a group associating with the priority queue);
inserts an execution result into an execution result queue when execution of the parallel threads is terminated; checking the execution result reported from the execution result queue (para[0039-0040, 0052, 0098], transmitting the execution result to the queue to be used in the transmission management processing, when the subtask execution thread is done processing, and obtain the execution result of the subtask).
Nakazawa does not explicitly teach checks an execution termination state of the parallel thread groups by checking the execution result, and executes parallel threads of parallel thread groups corresponding to the execution termination state.
However, Govindarajeswaran teaches checks an execution termination state of the parallel thread groups by checking the execution result, and executes parallel threads of parallel thread groups corresponding to the execution termination state (para[0042-0043, 0048-0049], if the executing threads are done executing the task, and there are no more task in the queue, then change the state of threads of a thread group to idle, and the idle thread can be allocated to execute other tasks).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Govindarajeswaran’s teaching to Nakazawa’s invention in order to provide a method for effectively managing threads in a thread group which executes tasks in a task queue, which minimizes the need to the dynamic extension or creation of new threads only when no idle threads are determined to be available in other thread groups, by tracking the status of the idle threads in different thread groups (para[0005-0006, 0009]).
As per claim 7, Nakazawa and Govindarajeswaran teach the apparatus of claim 1, and Nakazawa teaches wherein the at least one program causes a representative parallel thread selected in advance from among parallel threads included in the parallel thread groups to insert the execution result of the parallel thread group into the execution result queue (para[0039-0040, 0052, 0098], request transmission of execution result, indicating a particular thread, then transmitting the execution result to the queue to be used in the transmission management processing, when the subtask execution thread is done processing, and obtain the execution result of the subtask).
As per claim 11, it is a method claim of claim 1 above, thus it is rejected for the same rationale.
As per claim 17, it is a method claim of claim 7 above, thus it is rejected for the same rationale.
Claim(s) 2-3 and 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakazawa in view of Govindarajeswaran as applied to claim 1 above, and further in view of Gottlieb et al US Patent 11,481,237 (hereafter Gottlieb).
As per claim 2, Nakazawa and Govindarajeswaran teach the apparatus of claim 1, but they do not explicitly teach wherein the at least one program discovers a request to execute a parallel thread group that is not scheduled for a preset time period by using a programmable timer in the parallel thread group queues corresponding to the priority.
However, Gottlieb teaches the at least one program discovers a request to execute a parallel thread group that is not scheduled for a preset time period by using a programmable timer in the parallel thread group queues corresponding to the priority (col 8, line 62-67, col 9, line 1-4, col 16, line 27-40, determine an identified amount of time elapses since adding a task to the low priority task queue, which exceeds a time threshold).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Gottlieb’s teaching to Nakazawa and Govindarajeswaran’s invention in order to provide a method of managing the one or more task queues where each is associated with a priority allows controlling the order in which tasks are executed and such method improves usability and reduces latency (col 8, line 62-67, col 9, line 1-17).
As per claim 3, Nakazawa, Govindarajeswaran and Gottlieb teach the apparatus of claim 2, and Gottlieb teaches wherein, when the at least one program discovers the request to execute the parallel thread group that is not scheduled for the preset time period, the at least one program moves the request to execute the parallel thread group that is not scheduled for the preset time period to a last execution request entry of a parallel thread group queue having second-highest priority (col 8, line 62-67, col 9, line 1-4, col 16, line 27-40, determine an identified amount of time elapses since adding a task to the low priority task queue, which exceeds a time threshold, and moves the task from a low priority queue to a higher (medium) priority task queue).
As per claim 12, it is a method claim of claim 2 above, thus it is rejected for the same rationale.
As per claim 13, it is a method claim of claim 3 above, thus it is rejected for the same rationale.
Claim(s) 4-5, 8-10, 14-15, 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakazawa in view of Govindarajeswaran as applied to claim 1 above, and further in view of Gruber et al. US Pub 2018/0232846 (hereafter Gruber).
As per claim 4, Nakazawa and Govindarajeswaran teach the apparatus of claim 1, but they do not explicitly teach wherein the at least one program loads information required for execution of parallel computation kernel code from execution states information into a register of an accelerating core by executing execution startup routine code for each parallel thread of the parallel thread groups and then executes the parallel computation kernel code.
However, Gruber teaches the at least one program loads information required for execution of parallel computation kernel code from execution states information into a register of an accelerating core by executing execution startup routine code for each parallel thread of the parallel thread groups and then executes the parallel computation kernel code (para[0045, 0070-0071, 0077], the internal state register of GPU indicates the state of the warp (threads), and the first warp of the shader executes the shader preamble(kernel code)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Gruber’s teaching to Nakazawa and Govindarajeswaran’s invention in order to provide a method for a GPU to detect and nullify unnecessary instructions in a call, which improves processing speed, efficiency and power consumption (para[0004-0005, 0047]).
As per claim 5, Nakazawa, Govindarajeswaran and Gruber teach the apparatus of claim 4, and Govindarajeswaran teaches wherein the execution states information includes common state information for identifying the parallel thread groups and individual parallel thread state information for identifying parallel threads included in the parallel thread groups (para[0026, 0049], identify idle threads and active threads from the thread groups and state of a thread group can be also maintained or changed, thus the individual thread state and thread group state are identified).
As per claim 8, Nakazawa and Govindarajeswaran teach the apparatus of claim 1, but they do not explicitly teach wherein the at least one program executes a first parallel thread group selected from among the multiple parallel thread groups on any one accelerating core group.
However, Gruber teaches the at least one program executes a first parallel thread group selected from among the multiple parallel thread groups on any one accelerating core group (para[0045-0047, 0057, 0070-0071, 0077], GPU executes the instructions in a first warp (thread group) of the call).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Gruber’s teaching to Nakazawa and Govindarajeswaran’s invention in order to provide a method for a GPU to detect and nullify unnecessary instructions in a call, which improves processing speed, efficiency and power consumption (para[0004-0005, 0047]).
As per claim 9, Nakazawa, Govindarajeswaran and Gruber teach the apparatus of claim 8, and Govindarajeswaran teaches wherein, when in an idle state, the at least one program executes all of parallel threads included in the first parallel thread group (para[0042-0043, 0048-0049], if the executing threads are done executing the task, and there are no more task in the queue, then change the state of threads of a thread group to idle, and the idle thread can be allocated to execute other tasks).
In addition, Gruber teaches the at least program reads a value of an idle status register of the accelerating core group and confirms that the accelerating core group (para[0045, 0070-0071, 0077], the internal state register of GPU indicates the state of the warp (threads) and indicates whether the first warp started to execute).
As per claim 10, Nakazawa, Govindarajeswaran and Gruber teach the apparatus of claim 9, and Govindarajeswaran teaches wherein the at least one program changes the value of the idle status register from IDLE to BUSY when all of the parallel threads included in the first parallel thread group are executed, and changes the value of the idle status register from BUSY to IDLE when execution of all of the parallel threads is terminated (para[0026, 0034-0036, 0049], determined idle threads of the thread group, and maintain or change the state of threads to idle if no task is left in the queue and all the threads’ status is idle).
As per claim 14, it is a method claim of claim 4 above, thus it is rejected for the same rationale.
As per claim 15, it is a method claim of claim 5 above, thus it is rejected for the same rationale.
As per claim 18, it is a method claim of claim 8 above, thus it is rejected for the same rationale.
As per claim 19, it is a method claim of claim 9 above, thus it is rejected for the same rationale.
As per claim 20, it is a method claim of claim 10 above, thus it is rejected for the same rationale.
Claim(s) 6 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakazawa in view of Govindarajeswaran as applied to claim 1 above, and further in view of Bishop et al. Us Pub 2017/075693 (hereafter Bishop).
As per claim 6, Nakazawa and Govindarajeswaran teach the apparatus of claim 1, but they do not explicitly teach wherein, when a total number of parallel threads in one of the parallel thread groups is greater than a number of hardware threads included in an accelerating core group, the at least one program switches to a context block of a stalled parallel thread so as to be loaded into scratchpad memory using thread switching logic.
However, Bishop teaches when a total number of parallel threads in one of the parallel thread groups is greater than a number of hardware threads included in an accelerating core group, the at least one program switches to a context block of a stalled parallel thread so as to be loaded into scratchpad memory using thread switching logic (para[0104-0105, 0110-0111], when a count of available physical threads is less than the number of logically parallel threads, then the stalled batch process is loaded in the input pipeline).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Bishop’s teaching to Nakazawa and Govindarajeswaran’s invention in order to provide a method that use a combination of concurrent and multiplexed processing schemes to adapt to the varying computational requirements and availability in a stream processing system with little performance loss or added complexity, and such method will result in increased revenue, higher user retention, improved user engagement and experience (para[0011-0013]).
As per claim 16, it is a method claim of claim 6 above, thus it is rejected for the same rationale.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zhang et al. US Pub 2025/0321785 teaches a method including obtaining an algorithm directed graph corresponding to a target task, the algorithm directed graph comprising a plurality of algorithm nodes; grouping the plurality of algorithm nodes in the algorithm directed graph to obtain a plurality of node groups; scheduling the plurality of node groups in series, and scheduling a processing algorithm corresponding to at least one algorithm node in the node group in parallel.
Uhrenholt US 2022/0020108 teaches suspending the processing for a group of one or more execution threads currently executing a shader program for an output being generated by a graphics processor, the issuing of shader program instructions for execution by the group of one or more execution threads is stopped, and any outstanding register-content affecting transactions for the group of one or more execution threads are allowed to complete.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAMMY EUNHYE LEE whose telephone number is (571)270-7773. The examiner can normally be reached Mon, Tues, Thur 9PM-4PM.
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/TAMMY E LEE/Primary Examiner, Art Unit 2195
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