Prosecution Insights
Last updated: July 17, 2026
Application No. 18/415,946

ELECTRONIC DEVICE AND OPERATION METHOD OF ELECTRONIC DEVICE FOR PERFORMING CALCULATION USING ARTIFICIAL INTELLIGENCE MODEL

Non-Final OA §103
Filed
Jan 18, 2024
Priority
Aug 23, 2022 — RE 10-2022-0105710 +2 more
Examiner
FEATHERSTONE, MARK D
Art Unit
Tech Center
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
59%
Grant Probability
Moderate
1-2
OA Rounds
1y 8m
Est. Remaining
84%
With Interview

Examiner Intelligence

Grants 59% of resolved cases
59%
Career Allowance Rate
185 granted / 312 resolved
-0.7% vs TC avg
Strong +25% interview lift
Without
With
+24.6%
Interview Lift
resolved cases with interview
Typical timeline
4y 2m
Avg Prosecution
6 currently pending
Career history
318
Total Applications
across all art units

Statute-Specific Performance

§101
0.8%
-39.2% vs TC avg
§103
87.1%
+47.1% vs TC avg
§102
7.0%
-33.0% vs TC avg
§112
2.4%
-37.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 312 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hunter et al (US 2022/0108157), hereinafter Hunter, in view of Simmons et al (US 2023/0125403), hereinafter Simmons. With regard to claim 1, Hunter discloses an electronic device comprising: a processor; and memory storing instructions, wherein the instructions, when executed by the processor, cause the electronic device to([0078], [0103], memory with AI processor) : load and compile an artificial intelligence model stored in the memory ([0055], machine learning models stored in memory);, skip a calculation with respect to a designated value when the designated value exists in a feature map and calculate a value to be calculated subsequent to the designated value ([0094], a sparse tensor may be compressed to a dense tensor so that the computations related to value location that are zero are skipped); and when the first-type activation function is not included in the compiled artificial intelligence model, perform a calculation with respect to input values of the feature map ([0094], sparse tensors generated by a sparse activation function; dense tensors are not compressed so calculations for each of the input values are performed). Hunter applies an activation function, however fails to specifically disclose determine whether the compiled artificial intelligence model includes a first-type activation function; when the first-type activation function is included in the compiled artificial intelligence model. Simmons teaches determining an appropriate activation function based on the types of inputs and outputs and applying the activation function that is present ([0120-0121]). It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the system of Hunter which teaches applying activation functions with the teaching of Simmons of determining an appropriate type of activation function so that the desired activation function can be applied in the system of Hunter based on the desired output (Simmons, [0121]). With regard to claim 2, Hunter in view of Simmons teaches the electronic device of claim 1. Hunter further teaches wherein the first-type activation function is a Rectified Linear Unit (ReLU) function ([0107], ReLU with a threshold). With regard to claim 3, Hunter in view of Simmons teaches the electronic device of claim 2, wherein the instructions, when executed by the processor, further cause the electronic device to: when the first-type activation function is included in the compiled artificial intelligence model, compress a feature map by excluding the designated value when the designated value exists in the feature map; and when the first-type activation function is not included in the compiled artificial intelligence model, deactivate the compress the feature map (See claim 1 rejection and also Hunter [0087], the activation function being ReLU, compression of the sparse tensor). With regard to claim 4, Hunter in view of Simmons teaches the electronic device of claim 2, wherein skipping the calculation with respect to the designated value and calculating the value to be calculated subsequent to the designated value includes performing a zero-skipping function that skips a calculation for “0” if “0” exists in the feature map (see claim 2 rejection and also Hunter [0087], skipping calculations where 0 appears). With regard to claim 5, Hunter in view of Simmons teaches the electronic device of claim 3, wherein compressing the feature map is a function of extracting a value excluding a value of "0" from the feature map and compressing the feature map based on the extracted value (see claim 3 rejection and also Hunter [0087], compression of the sparse tensor and skipping calculations where 0 appears). With regard to claim 6. Hunter in view of Simmons teaches the electronic device of claim 4, wherein the instructions, when executed by the processor, further cause the electronic device to: in response to calculate the value, when a feature map corresponding to a result value of a previous hidden layer of the artificial intelligence model is used as an input value and “0” exists in the feature map, skip a calculation with respect to “0” and perform a calculation with respect to a value other than “0” to be calculated next; and perform calculation with respect to a multiply accumulate calculation (MAC) result (see claim 4 rejection and also Hunter [0087], compression of the sparse tensor and skipping calculations where 0 appears). With regard to claim 7, Hunter in view of Simmons teaches the electronic device of claim 5, wherein the instructions, when executed by the processor, further cause the electronic device to: in response to compressing the feature map, compress a feature map with values other than “0” from the feature map corresponding to an output value of a hidden layer after a calculation of the hidden layer of the artificial intelligence model is completed; and store the compressed feature map in the memory (see claim 5 rejection and [0087] of Hunter, compression as pre-processing before the calculation, performed on input feature maps before the calculation takes place, thus based on whether the input feature map is sparse. Claims 8-14 correspond to claims 1-7, and are analyzed accordingly. Claims 15-20 correspond to claims 1-5 and 7, and are analyzed accordingly. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARK D FEATHERSTONE whose telephone number is (571)270-3750. The examiner can normally be reached Monday-Friday 9:00AM - 5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, John Cottingham can be reached at 571-272-1400. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111
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Prosecution Timeline

Jan 18, 2024
Application Filed
Jun 12, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
59%
Grant Probability
84%
With Interview (+24.6%)
4y 2m (~1y 8m remaining)
Median Time to Grant
Low
PTA Risk
Based on 312 resolved cases by this examiner. Grant probability derived from career allowance rate.

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