DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/18/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restrictions
Applicant’s election without traverse of Invention I and Claims 1-11 and 17-20 in the reply filed on 06/26/2026 is acknowledged. Claims 12 - 16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 06/26/2026.
Specification
The disclosure is objected to because of the following informalities:
[0010] recites “the light emitting element may include a first sensor electrode..”; this should be “the light receiving element may include a first sensor electrode..”
Appropriate correction is required.
Claim Objections
Claim 9 is objected to because of the following informalities:
Claim 9 recites “a first drain electrode connected to a drain area of the first active pattern”; this should be written as “a first drain electrode connected to a drain region of the first active pattern”
Claim 9 recites “a second drain electrode connected to a drain area of the second active pattern”; this should be written as “a second drain electrode connected to a drain region of the second active pattern”
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 17, and 20 are rejected under 35 U.S.C. 102 (a)(2) as being anticipated by Han et al. (US20220075979A1; Han).
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Han: FIG. 17
Regarding Claim 1, Han discloses a display panel (display panel 100, FIG. 17 reproduced above, [0121]) comprising:
a base substrate (substrate 10 or SUBS), FIGS. 1, 17, [0078], [0143];
a thin film transistor layer (circuit layer 12 including pixel circuit CPIX and sensor driving circuit COPD) on the base substrate (SUBS/10), FIGS. 1, 17, [0078], [0123], [0126] and comprising:
a lower metal layer configured to receive a low potential voltage FIG. 15, [0235], [0277];
Han [0235] discloses the pixel circuit CPIX and the sensor driving circuit COPD receive the low-potential power voltage ELVSS through shared power line PL3 and [0277] discloses the VSS line PL3 is formed by one of the lower metal layers. Therefore, the lower metal layer is configured to receive a low potential voltage ELVSS.
a pixel circuit (pixel circuit CPIX) including at least one transistor (driving element DT and the switch elements M1 to M6 implemented with a p-channel TFT) FIG. 15, [0157]; and
a sensor circuit (COPD) electrically connected to the lower metal layer, [0204], [0277].
Han [0204], [0277]) discloses the sensor driving circuit COPD is connected to PL3, and PL3 if formed by one of the lower metal layers. Therefore the sensor circuit is electrically connected to the lower metal layer.
an element layer (light emitting element and sensor layer 14) on the thin film transistor layer (circuit layer 12) having a light emitting element (OLED), FIGS. 1, 17, [0143] comprising:
a first pixel electrode (anode electrode AND of OLED) electrically connected to the pixel circuit (pixel circuit CPIX), FIG. 17, [0183];
a second pixel electrode (cathode electrode CAT of OLED) configured to receive the low potential voltage (cathode electrode of the light emitting element OLED is connected to the VSS line PL3 to which the low-potential power voltage ELVSS is applied), [0164]; and
a light receiving element (organic photodiode OPD) electrically connected to the sensor circuit (anode electrode of OPD may be connected to sensor circuit COPD, [0184]) and configured to receive the low potential voltage from the lower metal layer (cathode electrode of OPD receives ELVSS through VSS line PL3 and PL3 may be formed by a lower metal layer), [0208], [0277].
Regarding Claim 17, Han discloses a display device (display device includes a display panel 100 in which a pixel array is disposed on the screen, a display panel driver, a fingerprint recognition processor 500, an optical sensor driver 600, [0120]) comprising:
a display panel (display panel 100, FIG. 17, [0121]) comprising:
a pixel (display pixels P) including a pixel circuit (CPIX) and a light emitting element (OLED), [0124], [0183]; and
a photo sensor (sensor pixels S) including a sensor circuit (COPD) and a light receiving element (OPD), [0126], [0140]; and
a readout circuit (fingerprint recognition processor 500) configured to sense the photo sensor (sensor pixels S), [0140];
Han [0140] discloses the fingerprint recognition processor 500 is connected to the sensor pixels S and amplifies the output voltage of the sensor pixels S. Therefore the readout circuit is configured to sense the photosensor.
wherein the display panel (display panel 100, FIG. 17, [0121]) comprises:
a base substrate (substrate 10 or SUBS), FIGS. 1, 17, [0078], [0143];
a thin film transistor layer (circuit layer 12 including pixel circuit CPIX and sensor driving circuit COPD) on the base substrate (SUBS/10), FIGS. 1, 17, [0078], [0123], [0126] and comprising:
a lower metal layer configured to receive a low potential voltage FIG. 15, [0235], [0277];
Han [0235] discloses the pixel circuit CPIX and the sensor driving circuit COPD receive the low-potential power voltage ELVSS through shared power line PL3 and [0277] discloses the VSS line PL3 is formed by one of the lower metal layers. Therefore, the lower metal layer is configured to receive a low potential voltage ELVSS.
a pixel circuit (pixel circuit CPIX) including at least one transistor (driving element DT and the switch elements M1 to M6 implemented with a p-channel TFT) FIG. 15, [0157]; and
a sensor circuit (COPD) electrically connected to the lower metal layer, [0204], [0277].
Han [0204], [0277]) discloses the sensor driving circuit COPD is connected to PL3, and PL3 if formed by one of the lower metal layers. Therefore the sensor circuit is electrically connected to the lower metal layer.
an element layer (light emitting element and sensor layer 14) on the thin film transistor layer (circuit layer 12) comprising:
a light emitting element (OLED) having a first pixel electrode (anode electrode AND of OLED) electrically connected to the pixel circuit (pixel circuit CPIX), FIG. 17, [0183]; and
a second pixel electrode (cathode electrode CAT of OLED) configured to receive the low potential voltage (voltage (cathode electrode of the light emitting element OLED is connected to the VSS line PL3 to which the low-potential power voltage ELVSS is applied), [0164]; and
a light receiving element (organic photodiode OPD) electrically connected to the sensor circuit (anode electrode of OPD may be connected to sensor circuit COPD, [0184]) and configured to receive the low potential voltage from the lower metal layer (cathode electrode of OPD receives ELVSS through VSS line PL3 and PL3 may be formed by a lower metal layer), [0208], [0277].
Regarding Claim 20, Han discloses the display device of claim 17, wherein the readout circuit (500) is configured to receive different voltages according to an amount of light received by the photo sensor (sensor pixel S), [0140], [0240].
Han [0140] discloses the fingerprint recognition processor 500 is connected to the sensor pixels S and amplifies the output voltage of the sensor pixels S. Han [0240] discloses when light is irradiated to the active layer ACT-OPD of the organic photodiode OPD during the exposure time te, a photocurrent is generated, the voltage of the capacitor Cst2 changes in proportion to the amount of received light, and the sensor data SRX is stored. Therefore, the read out circuit 500 is configured to receive different voltages according to the light received by the photo sensor.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Han in view of Kubota et al. (US20210066669A1; hereinafter Kubota).
Regarding Claim 2, Han discloses the display panel of claim 1.
Han does not disclose “wherein the element layer further includes a partition wall member surrounding the light receiving element.”
In a similar art, Kubota discloses a display unit 100B, FIG. 19A, [0436].
Kubota [0365] discloses the light-receiving device 110 is provided on the inner side of a frame-shaped light-blocking layer 219a and the four sides of the light-receiving device 110 are completely surrounded by the light-blocking layer 219a. Kubota [0450] discloses the light-blocking layer 219a is positioned over the partition 217 having a function of blocking visible light.
Kubota discloses: wherein the element layer (layer including light-emitting device 190, light receiving device 110) includes a partition wall (partition 217 with light blocking layer 219a) surrounding the light receiving element (light receiving device 110), [0365], [0450].
Kubota discloses that a device as taught including a partition wall inhibits entry of stray light into the light-receiving device [0365]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Han’s device in order to inhibit entry of stray light into the light-receiving device as disclosed by Kubota [0365].
Regarding Claim 18, Han discloses the display device of claim 17.
Han does not disclose “wherein the element layer includes a partition wall surrounding the light receiving element without an opening.”
Kubota discloses: wherein the element layer (layer including light-emitting device 190, light receiving device 110) includes a partition wall (partition 217 with light blocking layer 219a) surrounding the light receiving element (light receiving device 110) without an opening, [0365], [0450].
Kubota [0365] discloses the light-receiving device 110 is provided on the inner side of a frame-shaped light-blocking layer 219a and the four sides of the light-receiving device 110 are completely surrounded by the light-blocking layer 219a. Kubota [0450] discloses the light-blocking layer 219a is positioned over the partition 217 having a function of blocking visible light and the partition 217 does not require the opening which is formed between the light-receiving device 110 and the light-emitting device 190.
Kubota discloses that a device as taught including a partition wall with no opening can absorb the stray light and improve sensing capability of the device [0450]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Han’s device in order to absorb stray light and improve sensing capability as disclosed by Kubota [0450].
Regarding Claim 19, The combination of Han and Kubota discloses the display device of claim 18.
Han does not disclose “wherein the partition wall includes at least one of an acryl resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.”
Kubota discloses: wherein the partition wall (partition 217 with light blocking layer 219a) includes at least one of an acryl resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin [0314], [0381].
Kubota [0314] discloses partition 216 can include an acrylic resin, a polyimide resin, an epoxy resin, a polyamide resin, a phenol resin; and partition 217 may be provided instead of partition 216, indicating 217 may also include these materials. Kubota [0381] discloses the light-blocking layer 219a may be formed using a resin material.
Kubota discloses that a device as taught enables formation of partition walls comprised of known materials having desired electrical insulating properties [0313]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Han’s device in order to form partition walls comprised of known materials having desired electrical insulating properties as disclosed by Kubota [0313].
Claims 3 - 7 are rejected under 35 U.S.C. 103 as being unpatentable over Han in view of Yamazaki et al. (US20020011972A1; hereinafter Yamazaki).
Regarding Claim 3, Han discloses the display panel of claim 1.
Han does not explicitly disclose “wherein the thin film transistor layer includes:
a multi-layered source-drain electrode layer; and a planarization insulating layer exposing at least a portion of the source-drain electrode layer, wherein the lower metal layer is electrically connected to the source-drain electrode layer.”
In a similar art Yamazaki discloses a display device [0014].
Yamazaki discloses: wherein the thin film transistor layer (TFT structure, FIG. 16A, [0366]) includes:
a multi-layered source-drain electrode layer (source wirings 238-242 and drain wirings 243-247 formed as a three layer structure including Ti/Al including Ti/Ti, FIG. 16A, [0366]); and
a planarization insulating layer (second interlayer insulating film 249) exposing at least a portion of the source-drain electrode layer (contact hole is formed in the second interlayer insulating film 249 and the first passivation film 248 so as to reach the drain wiring 245), FIG. 16C, [0369].
Han [0277] discloses the lower metal layer including third power line PL3.
The combination of Han and Yamazaki discloses: wherein the lower metal layer (Han: PL3) is electrically connected to the source-drain electrode layer (Yamazaki: source wirings 238-242 and drain wirings 243-247 formed as a three layer structure including Ti/Al including Ti/Ti).
Yamazaki discloses that a device as taught can provide a TFT structure with excellent leveling properties while maintaining electrical connectivity [0368], [0369]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Han’s device including a TFT structure with excellent leveling properties while maintaining electrical connectivity as disclosed by Yamazaki [0368], [0369].
Regarding Claim 4, The combination of Han and Yamazaki discloses the display panel of claim 3.
Yamazaki discloses: wherein the second pixel electrode includes a conductive layer having light transmission (anode 259 made of a transparent conductive film), FIG. 17B, [0378].
the light receiving element includes:
Yamazaki discloses: a first sensor electrode (250) connected to the source-drain electrode layer (245), FIG. 16C, [0369]; and
a second sensor electrode (252) includes the conductive layer (conductive film), FIG. 16C, [0370]; and
the second sensor electrode (252) is connected to a side surface of the exposed source-drain electrode layer (245), FIG. 16C, [0369], [0370].
Yamazaki FIG. 16C, [0369], [0370] discloses the cathode electrode 250 of a light receiving diode (photoelectric converting element) is formed so as to contact the drain wiring 245, with photoconversion layer 251 and transparent anode electrode 252 are subsequently formed thereon, such that electrode 252 is electrically connected to drain wiring 245 through 251 and 250. This indicates the second sensor electrode may be connected to a side surface of the exposed source-drain electrode layer.
Yamazaki discloses that a device as taught can provide a TFT structure with excellent leveling properties while maintaining electrical connectivity [0368], [0369]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Han’s device including a TFT structure with excellent leveling properties while maintaining electrical connectivity as disclosed by Yamazaki [0368], [0369].
Regarding Claim 5, The combination of Han and Yamazaki discloses the display panel of claim 4.
Yamazaki discloses: wherein the source-drain electrode layer (source wirings 238-242 and drain wirings 243-247) includes first and third layers containing titanium and a second layer containing aluminum layer (source wirings 238-242 and drain wirings 243-247 formed as a three layer structure including Ti/Al including Ti/Ti, FIG. 16A, [0366], and
the second sensor electrode (252) is connected to the second layer of the source-drain electrode layer (wiring 245 of the three layer structure), FIG. 16C, [0369], [0370].
Yamazaki [0366], [0369] discloses a drain wiring 245 in a three layer structure including Ti/Al including Ti/Ti. Yamazaki FIG. 16C, [0369], [0370] discloses the cathode electrode 250 of a light receiving diode (photoelectric converting element) is formed so as to contact the drain wiring 245, with photoconversion layer 251 and transparent anode electrode 252 are subsequently formed thereon, such that electrode 252 is electrically connected to drain wiring 245 through 251 and 250. This indicates the second sensor electrode may be connected to the second layer of the source-drain electrode layer.
Yamazaki discloses that a device as taught can provide a TFT structure with excellent leveling properties while maintaining electrical connectivity [0368], [0369]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Han’s device including a TFT structure with excellent leveling properties while maintaining electrical connectivity as disclosed by Yamazaki [0368], [0369].
Regarding Claim 6, The combination of Han and Yamazaki discloses the display panel of claim 5.
Yamazaki discloses: wherein the second layer (second layer of three layer TFT structure including Ti/Al-Ti/Ti) includes a side wall, and the second sensor electrode (252) is connected to the side wall of the second layer, FIG. 16C, [0366], [0369], [0370].
Yamazaki [0366], [0369] discloses a drain wiring 245 in a three layer structure including Ti/Al including Ti/Ti. Yamazaki FIG. 16C, [0369], [0370] discloses the cathode electrode 250 of a light receiving diode (photoelectric converting element) is formed so as to contact the drain wiring 245, with photoconversion layer 251 and transparent anode electrode 252 are subsequently formed thereon, such that electrode 252 is electrically connected to drain wiring 245 through 251 and 250. This indicates the second layer includes a side wall and the second sensor electrode may be connected to the side wall of the second layer.
Yamazaki discloses the second layer includes a side wall, and the second sensor electrode may be connected to the side wall of the second layer except for the sidewall of the second layer is inclined.
However, a change in size or shape or both is an unpatentable modification when it results in optimum conditions that differ from the prior art in degree but not in kind. In Re Rose, 220 F.2d 459, 105 USPQ 237, In reDailey, 357 F.2d 669, 149 USPQ 47). In the instant case the prior art device would not perform differently if modified to the claimed shape. Therefore the claimed limitations are considered met.
Regarding Claim 7, The combination of Han and Yamazaki discloses the display panel of claim 4.
Yamazaki discloses: wherein the second pixel electrode (259) and the second sensor electrode (252) are disconnected from each other, FIG. 17B, [0378].
Yamazaki discloses that a device as taught can provide a TFT structure with excellent leveling properties while maintaining electrical connectivity [0368], [0369]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Han’s device including a TFT structure with excellent leveling properties while maintaining electrical connectivity as disclosed by Yamazaki [0368], [0369].
Claims 8 – 11 are rejected under 35 U.S.C. 103 as being unpatentable over Han in view of Huang et al. (US20240172490A1; hereinafter Huang).
Regarding Claim 8, Han discloses the display panel of claim 1, wherein the
thin film transistor layer (circuit layer 12 including pixel circuit CPIX and sensor driving circuit COPD) FIG. 17, [0123], [0126] includes:
a buffer layer (a first buffer layer BUF1) on the base substrate (substrate SUBS), FIG. 31, [0268];
the lower metal layer on the buffer layer (first metal layer may be formed on the first buffer layer BUF1), FIG. 31, [0268];
a first interlayer insulating layer (second buffer layer BUF2) covering the lower metal layer (a second buffer layer BUF2 may be formed on the first metal layer), FIG. 31, [0268];
a first active pattern (active layer ACT) on the first interlayer insulating layer (BUF2), (an active layer ACT may be formed of a semiconductor material, for example, a-Si, deposited on the second buffer layer BUF2), FIG. 31, [0269];
a first gate insulating layer (gate insulating film GI) covering the first active pattern (active layer ACT) and overlapping a channel region of the first active pattern (portion of ACT underlying GATE), FIG. 31, [0270].
Han [0270] discloses a gate insulating film GI may be formed on the active layer ACT and a second metal layer include a gate line and a gate electrode GATE may be formed on the gate insulating film GI.
a first gate electrode layer (second metal layer including gate electrode GATE) on the first gate insulating layer (GI), FIG. 31, [0270]
a second interlayer insulating layer (a first interlayer insulating film ILD1) covering the first gate electrode layer (second metal layer including gate electrode GATE), FIG. 31, [0271];
Han does not disclose “a second active pattern on the second interlayer insulating layer; a second gate insulating layer covering the second active pattern;
a second gate electrode layer on the second gate insulating layer and overlapping a channel region of the second active pattern; a third interlayer insulating layer covering the second gate electrode layer; and a first source-drain electrode layer on the third interlayer insulating layer and connected to the lower metal layer, the first active pattern, and the second active pattern.”
In a similar art, Huang discloses a display device [0002].
Huang discloses: a second active pattern (a second active layer 32) on the second interlayer insulating layer (second insulation layer 12), FIG. 5, [0091];
a second gate insulating layer (third insulation layer 13) covering the second active pattern (32), FIG. 5, [0091];
a second gate electrode layer (second top gate electrode 33) on the second gate insulating layer (13) and overlapping a channel region of the second active pattern (channel region of a second active layer 32), FIG. 5, [0091], [0122];
a third interlayer insulating layer (the fourth insulation layer 14) covering the second gate electrode layer (second top gate electrode 33); FIG. 5, [0091]; and
a first source-drain electrode layer (fourth conductive layer including 24, 25, 26, 34, 35) on the third interlayer insulating layer (14) and connected to the lower metal layer (bottom gate electrode 21), the first active pattern (22), and the second active pattern (32), FIG. 5, [0091], [0130].
Huang discloses that a device as taught reduces thickness, simplifies manufacturing processes, and reduces production cost [0148]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Han’s device in order to reduce thickness, simplify manufacturing processes, and reduce production costs as disclosed by Huang [0148].
Regarding Claim 9, The combination of Han and Huang discloses the display panel of claim 8.
Han does not disclose “wherein the first source-drain electrode layer includes:
a first source electrode connected to a source region of the first active pattern; a first drain electrode connected to a drain area of the first active pattern; a second source electrode connected to the lower metal layer and a source region of the second active pattern; and a second drain electrode connected to a drain area of the second active pattern.”
Huang discloses: wherein the first source-drain electrode layer (fourth conductive layer including 24, 25, 26, 34, 35) includes:
a first source electrode (24) connected to a source region of the first active pattern (22), FIG. 5, [0091];
a first drain electrode (25) connected to a drain area of the first active pattern (22), FIG. 5, [0091];
a second drain electrode (35) connected to a drain area of the second active pattern (32), FIG. 5, [0091].
Han [0277] discloses the lower metal layer including third power line PL3.
The combination of Han and Huang discloses: a second source electrode (Huang: 34) connected to the lower metal layer (Han: lower metal layer) and a source region of the second active pattern (Huang: 32, FIG. 5, [0091]).
Huang discloses that a device as taught reduces thickness, simplifies manufacturing processes, and reduces production cost [0148]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Han’s device in order to reduce thickness, simplify manufacturing processes, and reduces production costs as disclosed by Huang [0148].
Regarding Claim 10, The combination of Han and Huang discloses the display panel of claim 8.
Han discloses: a first planarization insulating layer (PLN1) covering the first source-drain electrode layer (SD1), FIG. 31, [0272];
a second source-drain electrode layer (SD2) on the first planarization insulating layer (PLN1) and connected to the first source-drain electrode layer (SD1), FIG. 31, [0272]; and
a second planarization insulating layer (PLN2) on the second source-drain electrode layer (SD2) and exposing at least a portion of the second source-drain electrode layer (contact hole through PLN2 exposes a portion of SD2), FIG. 31, [0275].
Regarding Claim 11, The combination of Han and Huang discloses the display panel of claim 10.
Han discloses: wherein the second source-drain electrode layer (SD2) and the light receiving element (OPD) are connected in an area in which at least a portion of the second planarization insulating layer (PLN2) is removed so that at least a portion of the second source-drain electrode layer is exposed (contact hole through PLN2 exposes a portion of SD2), FIG. 31, [0273], [0275].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KRISHNA PALANISWAMY whose telephone number is (571)272-6239. The examiner can normally be reached Monday - Friday 8:30AM - 5PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Krishna J. Palaniswamy/
Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
