DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10 & 14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 recites the limitation "the quantum chip" in line 2. There is insufficient antecedent basis for this limitation in the claim. For examination purposes, examiner has interpreted “the quantum chip” to read “a quantum chip”.
Claim 14 recites the limitations “a transmission device”, “a substrate”, “a micro-strip line layer”, “a dielectric layer”, “a ground layer and a port pad”, “a ground plate”, and “a conductor strip” in lines 1, 3, 4, 5, 6, 7, & 8, respectively. The limitations have been previously introduced in claim 1, of which claim 14 depends upon. It is unclear if the claim is introducing new limitations or referring to the previously introduced limitations. Further clarification is necessary. For examination purposes, examiner has interpreted “a method for fabricating a transmission device according to claim 1” to read “a method for fabricating a transmission device
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 8, 10-11, & 13-20 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Elsherbini et al. (US 2019/0044047 A1), hereinafter Elsherbini.
Regarding claim 1, Elsherbini discloses, in figure 3, a transmission device, comprising:
a substrate (Para [0060], “package substrate 314”);
a micro-strip line layer (Para [0068], “metal layer…328-2…implementing interconnect lines”), formed on the substrate (Para [0068], “metal layers 328…of the package substrate 314”);
a dielectric layer (Para [0066], “insulating material 322 may be a dielectric material”), formed on the micro-strip line layer (layer 328-2 is formed on the dielectric 322); and
a ground layer (Para [0078], “superconductor 320 connected to the ground potential provides a ground plane”…coupled to a first ground providing metal layer 328-1) and a port pad (Para [0073], “first level interconnects 312…black circles to indicate signal connections”…coupled to port pads formed by a separate portion of metal layer 328-1), formed on the dielectric layer (all portions of metal layer 328-1 provided on the dielectric 322), wherein the ground layer is electrically connected to a ground plate of the micro-strip line layer (see figure 3 disclosing the ground layer connection established between the vias between metal layers 328-1 to 328-5, thus electrically connecting ground from 328-1 to a ground plate on the interconnect metal layer 328-2), and the port pad is electrically connected to a conductor strip of the micro-strip line layer (Para [0079], “signals from the signal first level interconnects 312 may be routed [to] the second metal layer 328-2”…routed from the black circles and port pad formed by separate portion of metal layer 328-1).
Regarding claim 2, Elsherbini discloses the transmission device according to claim 1, and continues to disclose, in figure 3, wherein the transmission device comprises multiple micro-strip line layers, and the multiple micro-strip line layers are stacked sequentially on the substrate (Para [0068], “metal layers 328-1, 328-2, 328-3, 328-4, and 328-5 implementing interconnect lines”…are sequentially stacked on the substrate 314).
Regarding claim 3, Elsherbini discloses the transmission device according to claim 1, and continues to disclose, in figure 3, wherein the micro-strip line layer comprises multiple conductor strips (metal layer 328-2 is comprised of multiple conductor strips, see figure 3).
Regarding claim 4, Elsherbini discloses the transmission device according to claim 1, and continues to disclose, in figure 3, wherein the micro-strip line layer is provided with a symmetric micro-strip transmission line or an asymmetric micro-strip line (metal line layer 328-2 is an asymmetric metal layer with respect to a middle vertical plane).
Regarding claim 5, Elsherbini discloses the transmission device according to claim 1, and continues to disclose, in figure 3, wherein a deposition hole is formed between the ground layer and the ground plate (Para [0067], “conductive vias and/or lines that provide the conductive pathways…in/on the package substrate 314 (e.g. conductive pathways 324) may be formed using…subtractive fabrication techniques”), wherein an electrical element is formed in the deposition hole (Para [0067], “conductive via”), and the electrical element is configured to achieve an electrical connection between the ground layer and the ground plate (conductive via forming the electrical connection between ground from 328-1 to a ground plate on the interconnect metal layer 328-2).
Regarding claim 8, Elsherbini discloses the transmission device according to claim 1, and continues to disclose, in figure 3, wherein the dielectric layer is made of a-Si, silicon dioxide, or silicon nitride (Para [0058] & [0070], “insulating material, which could include any suitable material, such as an interlayer dielectric (ILD). Examples of insulating materials may include silicon oxide, silicon nitride…322 may be a dielectric material…and may take the form of any of the embodiments of the insulating materials disclosed herein”).
Regarding claim 10, as best understood based on the 35 U.S.C. 112(b) rejection made above, Elsherbini discloses the transmission device according to claim 1, and continues to disclose, in figure 3, wherein the port pad comprises a first port configured to be electrically connected to a quantum chip (Para [0063], “corresponding first level interconnects 312, may be connected to any suitable elements of the quantum circuit implemented on the qubit die 304, e.g. any of the quantum circuits 100, 200 described above”), and a second port configured to be electrically connected to a controlling and reading apparatus (Para [0063], “corresponding first level interconnects 312, may be electrically connected…for controlling a quantum state of one or more superconducting qubits of the superconducting qubit device, as described above…for detecting a quantum state of one or more superconducting qubits of the superconducting qubit device, as described above.”), wherein a flux layer is formed on the first port (Para [0063], “corresponding first level interconnects 312, may be electrically connected to one or more flux bias lines of the superconducting qubit device implemented by the quantum circuit of the qubit die 304”).
Regarding claim 11, Elsherbini discloses the transmission device according to claim 1, and continues to disclose, in figure 3, A quantum device integration component, comprising:
a quantum chip, on which a superconducting circuit is formed (Para [0060], “quantum circuit 100…may be included in/on a die and coupled to a package substrate [314] to form a superconducting device package”); and
the transmission device (comprised of the package substrate 314), wherein the quantum chip is mounted on the transmission device via Flip Chip or Wire Bond (Para [0073], “the first level interconnects 312 may be flip chip (or controlled collapse chip connection, C4) bumps disposed initially on the qubit die 304 or on the package substrate 314”), the ground layer and the quantum chip are common-grounded (328-1 and the quantum chip 304 grounded to 320), and the conductor strip is coupled to the superconducting circuit (Para [0079], “signals from the signal first level interconnects 312 [i.e., coupled to the superconducting circuit formed on quantum chip 304] may be routed [to] the second metal layer 328-2”…routed from the black circles and port pad formed by separate portion of metal layer 328-1).
Regarding claim 13, Elsherbini discloses the transmission device according to claim 1, and continues to disclose, in figure 3 & 9, a quantum computer, which is at least provided with the transmission device (Para [0101], “quantum computing device 2000 that may include any of the qubit device packages disclosed herein”).
Regarding claim 14, Elsherbini discloses, in figure 3, a method for fabricating transmission device, comprising:
providing a substrate (Para [0060], “package substrate 314”);
forming a micro-strip line layer (Para [0068], “metal layer…328-2…implementing interconnect lines”) on the substrate (Para [0068], “metal layers 328…of the package substrate 314”);
forming a dielectric layer (Para [0066], “insulating material 322 may be a dielectric material”) on the micro-strip line layer (layer 328-2 is formed on the dielectric 322); and
forming a ground layer (Para [0078], “superconductor 320 connected to the ground potential provides a ground plane”…coupled to a first ground providing metal layer 328-1) and a port pad (Para [0073], “first level interconnects 312…black circles to indicate signal connections”…coupled to port pads formed by a separate portion of metal layer 328-1) on the dielectric layer (all portions of metal layer 328-1 provided on the dielectric 322), wherein the ground layer is electrically connected to a ground plate of the micro-strip line layer (see figure 3 disclosing the ground layer connection established between the vias between metal layers 328-1 to 328-5, thus electrically connecting ground from 328-1 to a ground plate on the interconnect metal layer 328-2), and the port pad is electrically connected to a conductor strip of the micro-strip line layer (Para [0079], “signals from the signal first level interconnects 312 may be routed [to] the second metal layer 328-2”…routed from the black circles and port pad formed by separate portion of metal layer 328-1).
Regarding claim 15, Elsherbini discloses the transmission device according to claim 2, and continues to disclose, in figure 3, wherein the micro-strip line layer is provided with a symmetric micro-strip transmission line or an asymmetric micro-strip line (metal line layer 328-2 is an asymmetric metal layer with respect to a middle vertical plane).
Regarding claim 16, Elsherbini discloses the transmission device according to claim 2, and continues to disclose, in figure 3, A quantum device integration component, comprising:
a quantum chip, on which a superconducting circuit is formed (Para [0060], “quantum circuit 100…may be included in/on a die and coupled to a package substrate [314] to form a superconducting device package”); and
the transmission device (comprised of the package substrate 314), wherein the quantum chip is mounted on the transmission device via Flip Chip or Wire Bond (Para [0073], “the first level interconnects 312 may be flip chip (or controlled collapse chip connection, C4) bumps disposed initially on the qubit die 304 or on the package substrate 314”), the ground layer and the quantum chip are common-grounded (328-1 and the quantum chip 304 grounded to 320), and the conductor strip is coupled to the superconducting circuit (Para [0079], “signals from the signal first level interconnects 312 [i.e., coupled to the superconducting circuit formed on quantum chip 304] may be routed [to] the second metal layer 328-2”…routed from the black circles and port pad formed by separate portion of metal layer 328-1).
Regarding claim 17, Elsherbini discloses the transmission device according to claim 3, and continues to disclose, in figure 3, A quantum device integration component, comprising:
a quantum chip, on which a superconducting circuit is formed (Para [0060], “quantum circuit 100…may be included in/on a die and coupled to a package substrate [314] to form a superconducting device package”); and
the transmission device (comprised of the package substrate 314), wherein the quantum chip is mounted on the transmission device via Flip Chip or Wire Bond (Para [0073], “the first level interconnects 312 may be flip chip (or controlled collapse chip connection, C4) bumps disposed initially on the qubit die 304 or on the package substrate 314”), the ground layer and the quantum chip are common-grounded (328-1 and the quantum chip 304 grounded to 320), and the conductor strip is coupled to the superconducting circuit (Para [0079], “signals from the signal first level interconnects 312 [i.e., coupled to the superconducting circuit formed on quantum chip 304] may be routed [to] the second metal layer 328-2”…routed from the black circles and port pad formed by separate portion of metal layer 328-1).
Regarding claim 18, Elsherbini discloses the transmission device according to claim 4, and continues to disclose, in figure 3, A quantum device integration component, comprising:
a quantum chip, on which a superconducting circuit is formed (Para [0060], “quantum circuit 100…may be included in/on a die and coupled to a package substrate [314] to form a superconducting device package”); and
the transmission device (comprised of the package substrate 314), wherein the quantum chip is mounted on the transmission device via Flip Chip or Wire Bond (Para [0073], “the first level interconnects 312 may be flip chip (or controlled collapse chip connection, C4) bumps disposed initially on the qubit die 304 or on the package substrate 314”), the ground layer and the quantum chip are common-grounded (328-1 and the quantum chip 304 grounded to 320), and the conductor strip is coupled to the superconducting circuit (Para [0079], “signals from the signal first level interconnects 312 [i.e., coupled to the superconducting circuit formed on quantum chip 304] may be routed [to] the second metal layer 328-2”…routed from the black circles and port pad formed by separate portion of metal layer 328-1).
Regarding claim 19, Elsherbini discloses the transmission device according to claim 5, and continues to disclose, in figure 3, A quantum device integration component, comprising:
a quantum chip, on which a superconducting circuit is formed (Para [0060], “quantum circuit 100…may be included in/on a die and coupled to a package substrate [314] to form a superconducting device package”); and
the transmission device (comprised of the package substrate 314), wherein the quantum chip is mounted on the transmission device via Flip Chip or Wire Bond (Para [0073], “the first level interconnects 312 may be flip chip (or controlled collapse chip connection, C4) bumps disposed initially on the qubit die 304 or on the package substrate 314”), the ground layer and the quantum chip are common-grounded (328-1 and the quantum chip 304 grounded to 320), and the conductor strip is coupled to the superconducting circuit (Para [0079], “signals from the signal first level interconnects 312 [i.e., coupled to the superconducting circuit formed on quantum chip 304] may be routed [to] the second metal layer 328-2”…routed from the black circles and port pad formed by separate portion of metal layer 328-1).
Regarding claim 20, Elsherbini discloses the quantum device integration component according to claim 1, and continues to disclose, in figure 3 & 9, a quantum computer, which is at least provided with the quantum device integration component (Para [0101], “quantum computing device 2000 that may include any of the qubit device packages disclosed herein”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-7, 9, & 12 are rejected under 35 U.S.C. 103 as being unpatentable over Elsherbini in view of Jeffrey et al. (US 2021/0175095 A1), hereinafter Jeffrey.
Regarding claim 6, Elsherbini discloses the transmission device according to claim 5, but fails to disclose wherein the electrical element is a superconducting material plated on an inner wall of the deposition hole, or a superconducting material filled inside of the deposition hole.
However, Jeffrey discloses, in figure 1A, wherein the electrical element is a superconducting material plated on an inner wall of the deposition hole (Para [0078], “superconductors…deposited using deposition processes”), or a superconducting material filled inside of the deposition hole (Para [0046], “The conductive vias 150 and the wiring layers 130 can include any suitable conductor, such as superconductor material”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the superconducting vias of Jeffrey in the transmission device of Elsherbini, to achieve the benefit of implementing electrical conductive vias that exhibit superconducting properties [i.e., improved performance at critical temperatures] in a quantum computational system (Jeffrey, Para [0079]).
Regarding claim 7, Elsherbini in view of Jeffrey disclose the transmission device of claim 6, and Jeffrey continues to disclose, in figure 1A, herein the superconducting material is Al, Nb, or TiN (Para [0046], “conductive vias 150 and the wiring layers 130 can include any suitable conductor, such as superconductor material including aluminum, titanium nitride, niobium titanium, niobium titanium nitride, ruthenium, molybdenum, or niobium”).
Regarding claim 9, Elsherbini discloses the transmission device according to claim 1, but fails to disclose wherein the thickness of each of the ground plate, the conductor strip, and the ground layer is between 20 nm and 150 nm.
However, Jeffrey discloses, in figure 1A, wherein the thickness of each of the ground plate, the conductor strip, and the ground layer is between 20 nm and 150 nm (Para [0046] & [0057], “wiring layers 130 may be formed as thin films, in which the thickness varies, e.g., from several nanometers to several hundreds of nanometers…the thickness of the interconnect pads and the barrier layer may be a few nanometers to several tens of nanometers to several hundred nanometers.”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the thickness of Jeffrey in the metal layers of Elsherbini, since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions [i.e., minimizing the size of the transmission device by decreasing the thickness of utilized layers and interconnect structures], and the combination yielded nothing more than predictable results to one of ordinary skill in the art. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415‐421, 82 USPQ2d 1385).
Regarding claim 12, Elsherbini discloses the quantum device integration component according to claim 11, but fails to disclose wherein a through-hole is formed on the quantum chip, a superconducting interconnector is formed in the through-hole, and the superconducting interconnector and the port pad are connected in contact.
However, Jeffrey discloses, in figure 2A, wherein a through-hole is formed on the quantum chip (Para [0057], “the bump bonds 32 are electrically connected through and formed on interconnect pads on one or both of the qubit chip 24 and the carrier chip 22”), a superconducting interconnector is formed in the through-hole (Para [0056] & [0057], “bump bonds 32 may be formed from superconductor material…interconnect pads may be formed from a superconductor material”), and the superconducting interconnector and the port pad are connected in contact (Para [0056], “bump bonds 32 also provide an electrical connection between circuit elements on the qubit chip 24 and circuit elements on the carrier chip 22”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the superconducting interconnector of Jeffrey in the quantum device integration component of Elsherbini, to achieve the benefit of implementing electrically conductive vias that exhibit superconducting properties [i.e., improved performance at critical temperatures] in a quantum computational system (Jeffrey, Para [0079]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Roberts, W. Benjamin, Superconductive Materials and Some of Their Properties, Volume 482 of NBS, U.S. Department of Commerce, Dec. 1969, Section II-1. [disclosing the general properties of superconductor materials].
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/TYLER J PERENY/ Examiner, Art Unit 2842