Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In the response to this office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application.
ALLOWABLE SUBJECT MATTER
Claims 6-7 and 11-27 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 6 is objected to because the cited references do not disclose “ wherein the pixel driving circuits are arranged in an array; and a number of the first reset signal sublines is N11, a number of the first bias signal sublines is N12, and a number of rows of the pixel driving circuits is N10, wherein N11≤N10, N12≤N10, and N10, N11 and N12 are positive integers, wherein along the second direction, the first reset signal sublines and the first bias signal sublines are alternately arranged, and N10≥N11+N12. Claim 7 is objected to because the cited references do not disclose “wherein the pixel driving circuits are arranged in an array; and a number of the second reset signal sublines is N21, a number of the second bias signal sublines is N22, and a number of columns of the pixel driving circuits is N20, wherein N21≤N20, N22≤N20, and N20, N21 and N22 are positive integers, wherein along the first direction, the second reset signal sublines and the second bias signal sublines are alternately arranged, and N20≥N21+N22” . Claim 11 is objected to because the cited references do not disclose “wherein the pixel driving circuits are arranged in an array; and a number of third reset signal sublines is N13, and a number of rows of the pixel driving circuits is N10, wherein N13≤N10, and N13 and N10 are positive integers. Claims 12-22 are objected to because the cited references do not disclose “wherein the display panel comprises a substrate, a first metal layer, a second metal layer and a third metal layer, wherein the second metal layer is disposed on a side of the first metal layer facing away from the substrate, and the third metal layer is disposed between the first metal layer and the second metal layer; the first metal layer comprises the first reset signal sublines; the second metal layer comprises the second reset signal sublines and the second bias signal sublines, and the second reset signal sublines are insulated from the second bias signal sublines; and the third metal layer comprises the first bias signal sublines.” Claims 23-27 are objected to because the cited references do not disclose “wherein each of the plurality of data lines in the second display region is connected to a respective fan-out wire of the plurality of fan-out wires through a connection wire; and the connection wire is disposed in the display region and comprises a first connection wire segment extending along the first direction and a second connection wire segment extending along the second direction, wherein the first connection wire segment is electrically connected to each of the plurality of data lines in the second display region, and the second connection wire segment is electrically connected to the respective fan-out wire”.
CLAIM REJECTIONS - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 , if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
1. Claims 1-5, 8-10, and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. US 20240153460 in view of Park et al 20240324367 hereinafter “Park2”.
Consider claim 1. Park discloses A display panel fig. 2 10, comprising pixel driving circuits fig. 2 PX1-3. display element connected to pixel circuits [0064]. also see fig. 3 and signal lines fig 3 [0073] signal lines, wherein
a pixel driving circuit of the pixel driving circuits fig. 3 PX includes pixel circuit comprises a drive transistor fig. 3 [0075] drive transistor T1 and a bias transistor fig. 3 [0082] T8, and the signal lines comprise bias signal lines fig. 3 Bias voltage line BL including supply voltage line 19a 19b fig. 5-7;
the drive transistor comprises a gate fig. 3 gate of T1, a first electrode and a second electrode fig. 3 source and drain of T1; and the bias transistor is electrically connected between a bias signal line of the bias signal lines and at least one of the first electrode or the second electrode of the drive transistor see fig. 3 T8 is between source and drain of T1 and BL; and
the bias signal lines comprise first bias signal sublines extending along a first direction and arranged along a second direction fig. 3 fig. 9 BL extending in X-axis direction and second bias signal sublines extending along the second direction and arranged along the first direction 19a 19b fig. 5-7 fig. 9 19 extending in Y-axis direction, wherein the first direction intersects the second direction , and the first bias signal sublines and the second bias signal sublines are electrically connected. see fig. 9 19 is connected to BL via contact holes 19.
Park however does not disclose the pixel driving circuit comprises first and second bias signal sublines in the display area.
Park2 however discloses the first and second bias signal sublines in the display area fig. 5 fig. 10 HVBL and VVBL located in the display area in and between subpixel circuits PC.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the display device of Park to include first bias signal sublines and second bias signal sublines in the display area fig. 5 HVBL and VVBL located in the display area in and between subpixel circuits PC., as taught by Park2, to help enable high rate driving without a decrease in resolution [0002].
Consider claim 2. Park as modified by Park2 disclose the display panel of claim 1, wherein the pixel driving circuit further comprises a first reset transistor Park fig. 3 T7. Park2 fig. 3 T7 and a light-emitting element Park fig. 3 OLED. Park2 fig. 3 LED, and the signal lines further comprise first reset signal lines Park fig.3 VL2 and 17. Also see Park2 fig. 3 VAL and fig. 5, wherein the first reset transistor is electrically connected between a first reset signal line of the first reset signal lines and the light-emitting element Park fig. 3 T7 is between VL2 and OLED. Park2 fig. 3 T7 between OLED and VAL; and
the first reset signal lines comprise first reset signal sublines and second reset signal sublines Park2 fig. 5 HVAL and VVAL, wherein the first reset signal sublines extend along the first direction and arranged along the second direction Park2 fig. 5 HVAL and VVAL, the second reset signal sublines extend along the second direction and arranged along the first direction Park2 fig. 5 HVAL and VVAL x-y direction, and the first reset signal sublines and the second reset signal sublines are electrically connected Park2 fig. 5 fig. 10 HVAL and VVAL via CNT3.
Motivation to combine is similar to motivation in claim 1.
Consider claim 3. Park as modified by Park2 disclose the display panel of claim 2, wherein the first bias signal sublines are arranged in a different layer from the second bias signal sublines Park2 fig. 4 [0115] HVBL HVAL are arranged on insulating layer 117 [0120] VVBL and VVAL are arranged on 119, and the first reset signal sublines are arranged in a different layer from the second reset signal sublines. Park2 fig. 4 [0115] HVBL HVAL are arranged on insulating layer 117 [0120] VVBL and VVAL are arranged on 119.
Motivation to combine is similar to motivation in claim 1.
Consider claim 4. Park as modified by Park2 disclose the display panel of claim 3, wherein the first reset signal lines and the bias signal lines are at least partially arranged in a same layer and insulated from each other Park2 fig. 4 [0115] HVBL HVAL are arranged on insulating layer 117 [0120] VVBL and VVAL are arranged on 119.
Motivation to combine is similar to motivation in claim 1.
Consider claim 5. Park as modified by Park2 disclose the display panel of claim 3, wherein the display panel comprises a substrate, a first metal layer and a second metal layer, wherein the second metal layer is disposed on a side of the first metal layer facing away from the substrate; the first metal layer comprises the first reset signal sublines and the first bias signal sublines, and the first reset signal sublines are insulated from the first bias signal sublines Park2 fig. 4 fig. 5 fig. 9 [0115] [0116] HVBL HVAL are arranged on insulating layer 117 and are from the same material [0120][0121] VVBL and VVAL are arranged on 119 and are from the same material; and the second metal layer comprises the second reset signal sublines and the second bias signal sublines, and the second reset signal sublines are insulated from the second bias signal sublines Park2 fig. 4 fig. 5 fig. 9 [0115] [0116] HVBL HVAL are arranged on insulating layer 117 and are from the same material [0120][0121] VVBL and VVAL are arranged on 119 and are from the same material.
Motivation to combine is similar to motivation in claim 1.
Consider claim 8. Park as modified by Park2 disclose the display panel of claim 5, wherein the pixel driving circuit further comprises a second reset transistor Park fig. 3 T4. Park2 fig. 3 T4, and the signal lines further comprise second reset signal lines Park fig. 3 VL1. Park2 fig. 3 VIL, wherein the second reset transistor is electrically connected between a second reset signal line of the second reset signal lines and the gate of the drive transistor; and the second reset signal lines extend along at least one of the first direction or the second direction Park fig. 3 T4 is connected between VL1 and gate of T1. Park2 fig. 3 T4 is connected between VIL and gate of T1.
Consider claim 9. Park as modified by Park2 disclose the display panel of claim 8, wherein the second reset signal lines comprise third reset signal sublines extending along the first direction, wherein the third reset signal sublines are arranged in a different layer from the bias signal lines Park2 fig. 5 fig. 10 HVIL and VVIL. [0115][0120] VVIL is different layer than HVBL and [0117] HVIL is in different layer than HVBL and VVBL.
Motivation to combine is similar to motivation in claim 1.
Consider claim 10. Park as modified by Park2 disclose the display panel of claim 9, wherein along a direction perpendicular to a plane where the substrate is located, the third reset signal sublines at least partially overlap the first bias signal sublines Park2 fig. 5 fig. 10 VVIL [0120].
Consider claim 28. Park discloses a display device fig. 1 1 comprising a display panel fig. 2 10, wherein the display panel comprises pixel driving circuits fig. 2 PX1-3. display element connected to pixel circuits [0064]. also see fig. 3 and signal lines fig 3 [0073] signal lines, wherein
a pixel driving circuit of the pixel driving circuits fig. 3 PX includes pixel circuit comprises a drive transistor fig. 3 [0075] drive transistor T1 and a bias transistor fig. 3 [0082] T8, and the signal lines comprise bias signal lines fig. 3 Bias voltage line BL including supply voltage line 19a 19b fig. 5-7;
the drive transistor comprises a gate fig. 3 gate of T1, a first electrode and a second electrode fig. 3 source and drain of T1; and the bias transistor is electrically connected between a bias signal line of the bias signal lines and at least one of the first electrode or the second electrode of the drive transistor see fig. 3 T8 is between source and drain of T1 and BL; and
the bias signal lines comprise first bias signal sublines extending along a first direction and arranged along a second direction fig. 3 fig. 9 BL extending in X-axis direction and second bias signal sublines extending along the second direction and arranged along the first direction 19a 19b fig. 5-7 fig. 9 19 extending in Y-axis direction, wherein the first direction intersects the second direction , and the first bias signal sublines and the second bias signal sublines are electrically connected see fig. 9 19 is connected to BL via contact holes 19.
Park however does not disclose the pixel driving circuit comprises first and second bias signal sublines in the display area.
Park2 however discloses the first and second bias signal sublines in the display area fig. 5 fig. 10 HVBL and VVBL located in the display area in and between subpixel circuits PC.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the display device of Park to include first bias signal sublines and second bias signal sublines in the display area fig. 5 HVBL and VVBL located in the display area in and between subpixel circuits PC., as taught by Park2, to help enable high rate driving without a decrease in resolution [0002].
CONCLUSION
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IBRAHIM A KHAN whose telephone number is (571)270-7998. The examiner can normally be reached on 10am-6pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Nitin Patel can be reached on 571-272-7677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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IBRAHIM A. KHAN
Primary Examiner
Art Unit 2628
/IBRAHIM A KHAN/ 6/13/2028Primary Examiner, Art Unit 2628
Prosecution Insights