Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) filed on January 18, 2024 and November 18, 2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Group I (Claims 1-13) and Species I (Fig. 1,7-8) in the reply filed on April 29, 2026 are acknowledged.
Claims 14-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species and Invention, there being no allowable generic or linking claim.
Drawings
The subject matter of this application admits of illustration by a drawing to facilitate understanding of the invention. Applicant is required to furnish a drawing under 37 CFR 1.81(c). No new matter may be introduced in the required drawing. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d).
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “D” has been used to designate both a first drain electrode and a second drain electrode in figures 1, 7, and 8.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01.
The omitted structural cooperative relationships are: A common drain formed by a first and second drain electrode. This structural cooperative relationship is considered essential because without it the written description does not clearly define what constitutes “a common drain electrode” (e.g. two physically independent drain electrodes in physical contact, two physically independent drain electrodes in electrical contact, a drain electrode with two compositionally distinct regions, etc).
Claims 2-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as dependent upon the rejected base claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3-6, and 8-13 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (KR102218375B1) in view of Rawat et al. (IEEE Transactions on Electron Devices, vol. 68, no. 7, pp. 3622-3629, July 2021) for the following reasons:
Regarding claim 1;
Kim et al. in Fig. 3A and Fig. 4 teaches A semiconductor device comprising: a substrate (e.g. Fig. 4); a first material layer and a second material layer on the substrate, the first material layer and the second material layer being junctioned to each other in a lateral direction to form a coherent interface (e.g. Fig. 4 ref 210, 310); a first source electrode and a first drain electrode on the first material layer (e.g. Fig. 3A, Fig. 4 ref 250, 260; [Description of Embodiments] “The first transistor 200 includes a first active layer 210…, a source electrode 250, and a drain electrode 260”); a first gate electrode between the first source electrode and the first drain electrode (e.g. Fig. 3A, Fig. 4 ref 240; [Description of Embodiments] “The first transistor 200 includes… a gate electrode 240…”); a second source electrode and a second drain electrode on the second material layer (e.g. Fig. 3A, Fig. 4 ref 250, 260; [Description of Embodiments] “The second transistor 300 includes a first active layer 310…, a source electrode 250, and a drain electrode 260”); and a second gate electrode between the second source electrode and the second drain electrode (e.g. Fig. 3A, Fig. 4 ref 240; [Description of Embodiments] “The second transistor 300 includes… a gate electrode 240…”).
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Kim et al. is silent to first and second material layers comprising a two-dimensional material as claimed.
However, Rawat et al. teaches that a semiconductor device, such as a CMOS inverter, configured with two different layered channel materials (a layered material and a 2-D material are being considered synonymous for the purposes of this examination).
At the effective time of filing, it would have been obvious to someone having ordinary
skill in the art to modify the first and second material layers taught by Kim et al. with two-dimensional materials taught by Rawat et al. because devices formed from such materials have been shown to exhibit improved performance and scalability (e.g. [Introduction] 1, [Impact of Channel Length] 19-20, [Conclusion]).
Regarding claim 3;
Rawat et al. further teaches in Table 1, that the lattice constant values of the first and second material layers can be 0.332nm and or 0.318nm respectively (e.g. Tbl. 1 gives the lattice constant of MoS2 as 0.318nm, and the lattice constant of WSe2 as 0.332nm).
These values teach that a lattice constant difference between a material of the first two-dimensional material layer and a material of the second two-dimensional material layer is 10 % or less.
Regarding claim 4;
Rawat et al. further teaches in Table 1, that the band gap energy values of the first and second material layers can be 1.8eV and or 1.53eV respectively (e.g. Tbl. 1 gives the band gap energy of MoS2 as 1.8eV, and the band gap energy of WSe2 as 1.53eV).
These values teach that a semiconductor material of the first two-dimensional material layer and a semiconductor material of the second two-dimensional material layer each have a bandgap of about 0.1 eV to about 3.0 eV.
Regarding claim 5;
Rawat et al. further teaches that the semiconductor device can be made with the first two-dimensional material layer and the second two-dimensional material layer each independently comprise transition metal dichalcogenide (TMD) (e.g. “single atomic thick 2-D materials (2DMs), such as transition metal dichalcogenides (TMDs; MoS2, MoSe2, WS2, WSe2, WTe2, and so on) and black phosphorus (BP) [1], have opened up new avenues for high-speed and low-power (LP) devices.”), black phosphorus, or graphene.
Regarding claim 6;
Rawat et al. further teaches that the first two-dimensional material layer, the second two-dimensional material layer, or both the first two-dimensional material layer and the second two- dimensional material layer include the TMD, the TMD comprises a metal element and a chalcogen element, the metal element includes one of Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, and Re, and the chalcogen element includes one of S, Se, and Te (e.g. “heterogeneous CMOS inverter configurations with two different layered materials for the channel, such as nMOS using MoS2 and pMOS using α -MoTe2, BP, WSe2, and Si-nanowire, have actively been investigated”).
Regarding claim 7;
Rawat et al. further teaches that MoS2 and WSe2 are “layered materials” (e.g. “…two different layered materials for the channel, such as nMOS using MoS2 and pMOS using α -MoTe2, BP, WSe2…”) composed of at least a layer of a single atom thickness (e.g. “…single atomic thick 2-D materials (2DMs), such as transition metal dichalcogenides (TMDs; MoS2, MoSe2, WS2, WSe2, WTe2, and so on) and black phosphorus (BP)…”).
This definition teaches that the first two-dimensional material layer and the second two-dimensional material layer each comprise about 1 layer to about 10 layers.
Regarding claim 8;
Kim et al. further teaches in Fig. 3A a semiconductor device further comprising: a first gate insulating layer between the first two-dimensional material layer and the first gate electrode; and a second gate insulating layer between the second two-dimensional material layer and the second gate electrode.
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Regarding claim 9;
Kim et al. further teaches in the specification a semiconductor device wherein a first one of the first two-dimensional material layer and the second two- dimensional material layer comprises an n-type semiconductor material, and a second one of the first two-dimensional material layer and second two- dimensional material layer comprises a p-type semiconductor material (e.g. [Description of Embodiments] “A P-type semiconductor may be applied to the first transistor and an N-type semiconductor may be applied to the second transistor. An N-type semiconductor may be applied to the first transistor and a P-type semiconductor may be applied to the second transistor.”).
Regarding claim 10;
Kim et al. further teaches in the specification a semiconductor device wherein the first two-dimensional material layer, the second two-dimensional material layer, the first source electrode, the first drain electrode, the second source electrode, the second drain electrode, the first gate electrode, and the second gate electrode are parts of a complementary metal-oxide-semiconductor (CMOS) inverter (e.g. [Background-Art] “In a CMOS inverter, a PMOS transistor and an NMOS transistor operate mutually, and the CMOS inverter performs a pullup operation and a pulldown operation. “, [Description of Embodiments] “The first transistor 200 and the second transistor 300 operate complementarily, and perform a pullup operation and a pulldown operation.”).
Regarding claim 13;
Kim et al. further teaches in Fig. 3A a semiconductor device wherein the first gate electrode and the second gate electrode are electrically connected to each other (e.g. [Description of Embodiments] “…the gate line of the first transistor is connected to the input signal line…the gate line of the second transistor is connected to the input signal line…”).
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Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (KR102218375B1) in view of Rawat et al. (IEEE Transactions on Electron Devices, vol. 68, no. 7, pp. 3622-3629, July 2021), further in view of Chuang et al. (Chuang et al. (US 20220359524 A1) for the following reasons:
Regarding claim 11;
Kim et al. in view of Rawat et al. teaches the semiconductor device as claimed in all preceding claims.
Kim et al. and Rawat et al. are silent to the semiconductor device having a common drain which is integrally formed from two drain electrodes.
However, Chuang et al teaches a semiconductor device where two thin film transistors share a drain electrode (e.g. Fig. 1 ref 738).
At the effective time of filing, it would have been obvious to someone having ordinary
skill in the art to modify the drain electrodes in the device taught by Kim et al. and Rawat et al. to be a common drain electrode as taught in Chuang et al. because such a configuration allows for a more compact device to be formed (e.g. [Detailed Description] “The compact common-drain configuration in which a pair of thin film transistors share a drain electrode may be used to provide an area-efficient layout…”).
Regarding claim 12;
Kim et al. further teaches that the individual drain electrodes (understood in view of Chuang et al. to be a common drain electrode formed from two drain electrodes) are positioned on opposite sides of the junction area of the two-dimensional material layers.
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Allowable Subject Matter
Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM ROBERT MANN whose telephone number is (571)270-0210. The examiner can normally be reached Monday thru Thursday 0800-1800 EST.
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/WILLIAM ROBERT MANN/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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