Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Amendment
The amendment filed on April 1, 2026 has been received and entered.
Applicant’s Amendments to the Claims have been received and acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/15/2026 is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9 and 11-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 1, lines 1-4, it is not clear whether “the DMA” refers to a controller, engine, unit, circuitry, operation, or functionality. Further, the phrase “of a processor” does not clearly define the structural or functional relationship between the DMA and the processor. As a result, it is unclear what physical or logical entity is being claimed. Additionally, the claim recites that “the DMA comprises:…”, suggesting structural elements, which is inconsistent with the undefined nature of “DMA” as recited. This inconsistency renders the scope of the claim unclear. Similar problems exist in claims 2-9, 11, 13, and 17.
In claim 5, line 10, a matrix buffer of the DMA is unclear since DMA describes a data transfer technique rather than a definite structure, and the claim fails to specify whether the DMA is hardware component, a functional unit, or an operation performed by the processor. Similar problems exist in claims 8, 14, and 17.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over BAI et al. (U.S. Publication No. 2020/0104690 A1), hereafter referred to as BAI’690 in view of Guo (U.S. Publication No. 2020/0349424 A1), hereafter referred to as Guo’424.
Referring to claim 1, BAI’690 as claimed, a direct memory access module (DMA) of a processor (NPU 700, see Fig. 7), wherein the processor supports a first data format of tensor data (process tensors in artificial networks, see paras. [0006], [0030]-[0032], and [0089]), and wherein the DMA comprises: a DMA controller (DMAC) (controller 770 and NDMA core 710, see Fig. 7) configured to: in response to a second data format of tensor data stored in an external memory being different from the first data format, convert, in a process of transmitting to-be-converted tensor data between a memory of the processor and the external memory (stream data blocks of a data stripe to/from an external memory of the NDMA core. In addition, the instructions loaded into the NPU may comprise program code to pre-process and post-process the data blocks in a buffer of the NDMA core during streaming of the data blocks, see paras. [0035], [0077] and Fig. 7; also note: the read engine is configured to transfer fragmented data from the external memory 760 into client memories (e.g. read buffer 722 and/or write buffer 732) for image processing or for configuration, see paras. [0074] and [0075]; and data conversion from image format to NPU data types for a read operation with conversion back to image format for 2D and 3D storage, see para. [0079]), the to-be-converted tensor data from the first data format into the second data format or from the second data format into the first data format, to obtain converted tensor data, wherein the first data format and the second data format respectively indicate a placement manner of the to-be-converted tensor data or the converted tensor data when the to- be-converted tensor data or the converted tensor data is stored (In operation, the MDMA core retrieves a full dword (e.g. 256-bit) from the external memory and crops off unneeded pixels and re-aligns the pixels when writing to the read client RCLT., see para. [0078]).
However, BAI’690 does not appear to disclose the data formats indicating an order of dimensions forming one or more vectors.
Guo’424 discloses converting the data formats of tensor data, the data formats indicating an order of dimensions forming one or more vectors (a NN selects a memory layout among a plurality of different memory layouts…The NN stores multi-dimensional kernel computation data using the selected memory layout during NN inference. The memory layouts to be selected can be CHWN, NHWC, NCHW layout. If the NN kernel computation data is not the selected memory layout, the NN transforms the NN kernel computation data for the selected memory layout, see paras. [0014], [0015], [0042]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify BAI’690’s invention to comprise converting the data formats of tensor data, the data formats indicating an order of dimensions forming one or more vectors, as taught by Guo’424, in order to convert between memory layouts to improve interference performance (see paras. [0001], [0003], and [0013]).
As to claim 2, BAI’690 also discloses a transpose buffer (TPB), and the TPB comprises a write port and a read port, and wherein the DMAC is configured to: write the to-be-converted tensor data into the TPB through the write port in a first direction (arrow pointing to read buffer 722 and out to client buffer, see Fig. 7), when; in response to a product of a quantity of rows of data being stored in the first direction of the TPB and a splitting width meeting a read port bit width, read a first part of data of the to-be-converted tensor data from the TPB through the read port in a second direction at the splitting width, and splice and store the first part of data in an order of the first direction, to obtain the converted tensor data (partitioned into any desirable number of vertical slices…In one example, the image is an m-sliced image, in which the line width of the image is partitioned into m line segments, which may or may not equal the N-lines of image., see paras. [0064]-[0066]; also note: the read engine includes a read buffer for storing (e.g., a bus width of configuration data…In operation, the read engine retrieves (e.g. one bus width number of bits of NDMA data from the external memory and stores those bits in the read buffer…the stored bits of data may be subjected to hardware pre-processing and post-processing within the read buffer, see paras. [0076] and [0077]), wherein the splitting width is a parameter for splitting data in one dimensional direction of the to-be-converted tensor data, and the first direction is perpendicular to the second direction (stream data blocks of a data stripe to/from an external memory of the NDMA core. In addition, the instructions loaded into the NPU may comprise program code to pre-process and post-process the data blocks in a buffer of the NDMA core during streaming of the data blocks, see paras. [0035], [0077] and Fig. 7; also note: the read engine is configured to transfer fragmented data from the external memory 760 into client memories (e.g. read buffer 722 and/or write buffer 732) for image processing or for configuration, see paras. [0074] and [0075]; and data conversion from image format to NPU data types for a read operation with conversion back to image format for 2D and 3D storage, see para. [0079).
As to claim 3, BAI’690 also discloses the TPB comprises a first buffer and a second buffer, the first buffer comprises a first write port (buffers such as read buffer 722 and to client buffers, see Fig. 7) and a first read port, and the second buffer comprises a second write port and a second read port (buffers such as write buffer 732 and to client buffer, see Fig. 7), and wherein the DMAC is configured to read the first part of data of the to-be-converted tensor data in the TPB from the second buffer through the second read port in the second direction at the splitting width when writing the to-be-converted tensor data into the first buffer through the first write port in the first direction, and splice the first part of data in the order of the first direction, or wherein the DMAC is configured to read the first part of data of the to-be-converted tensor data in the TPB from the first buffer through the first read port in the second direction at the splitting width when writing the to-be-converted tensor data into the second buffer through the second write port in the first direction, and splice the first part of data in the order of the first direction (stream data blocks of a data stripe to/from an external memory of the NDMA core. In addition, the instructions loaded into the NPU may comprise program code to pre-process and post-process the data blocks in a buffer of the NDMA core during streaming of the data blocks, see paras. [0035], [0077] and Fig. 7; also note: the read engine is configured to transfer fragmented data from the external memory 760 into client memories (e.g. read buffer 722 and/or write buffer 732) for image processing or for configuration, see paras. [0074] and [0075]; and data conversion from image format to NPU data types for a read operation with conversion back to image format for 2D and 3D storage, see para. [0079).
As to claim 4, BAI’690 also discloses a reorder buffer (ROB), and the to-be-converted tensor data is to-be-read tensor data stored in the external memory of an apparatus comprising the processor (data is stored in an external memory in a raster order of lines in a Dim0 direction (in pixels), and continuously in a Dim1 direction. The 3D data storage is repeated over Dim0-Dim1 raster order in a Dim2 direction…Data access to a stripe of 3D rectangular blocks is performed in a predetermined order, see para. [0070]), wherein the DMAC is configured to determine a cascading manner based on the to-be- converted tensor data, the splitting width, and the read port bit width, wherein the cascading manner is a manner of combining two dimensions higher than a lowest dimension of the to-be- converted tensor data, wherein the DMAC is configured to generate, based on the cascading manner or a bus bit width, a read request for reading the to-be-converted tensor data, wherein the read request is used to read first tensor data, and the first tensor data is at least a part of data of the to-be-converted tensor data, wherein the DMAC is configured to send a read command in a preset order based on the read request and the bus bit width (determines whether a DMA command from a controller is received…all configuration registers are programmed to define, for example, image information, bus information, and address information…a read engine of the NDMA core retrieves a predetermined number of bits (e.g. a bus width) of image data from the external memory and stores those bits in the read buffer of the NDMA core, see paras. [0087]-[0090]), wherein the read command carries a number specified in the preset order, and the preset order is an order from a lower dimension to a higher dimension based on the two dimensions and wherein the read command is used to read second tensor data in the first tensor data, the second tensor data is at least a part of data of the first tensor data, and the number carried in the read command indicates an order of writing the second tensor data into the ROB (As described, Dim0 refers to a dimension that moves sequentially through contiguous NDMA words in external memory; the term Dim1 refers to a dimension used when data is transferred in a 3D block (e.g. as shown in FIG. 6B), and the term Dim2 refers to a dimension used when data is transferred as a 2D or 3D block, see paras. [0070]-[0071]; In operation, the read engine retrieves (one bus width number of) bits of image data (e.g. NDMA data) from the external memory and stores those bits in the read buffer, see para. [0077]; the read engine reads out the bits of image data, and each pixel is unpacked to a byte boundary using, for example, 256-bit data words, see paras. [0078]-[0079]).
As to claim 5, BAI’690 also discloses the DMAC further configured to: read the second tensor data from the ROB in an order of the number, and write the second tensor data into the TPB through the write port in the first direction, and wherein the DMAC is further configured to read, in response to the product of the quantity of rows of data being stored in the first direction of the TPB and the splitting width meeting the read port bit width (a read engine of the NDMA core retrieves a predetermined number of bits (e.g. a bus width) of image data from the external memory and stores those bits in the read buffer of the NDMA core, see paras. [0087]-[0090]), a second part of data of the second tensor data from the TPB through the read port in the second direction at the splitting width, splice the second part of data in the order of the first direction, and store spliced second part of data into a matrix buffer of the DMA (stream data blocks of a data stripe to/from an external memory of the NDMA core. In addition, the instructions loaded into the NPU may comprise program code to pre-process and post-process the data blocks in a buffer of the NDMA core during streaming of the data blocks, see paras. [0035], [0077] and Fig. 7; also note: the read engine is configured to transfer fragmented data from the external memory 760 into client memories (e.g. read buffer 722 and/or write buffer 732) for image processing or for configuration, see paras. [0074] and [0075]; and data conversion from image format to NPU data types for a read operation with conversion back to image format for 2D and 3D storage, see para. [0079]).
As to claim 6, BAI’690 also discloses the read command further comprises a logical address of the second tensor data or a size of the second tensor data (location/address and size, see paras. [0066]-[0069]), and the size of the second tensor data is less than or equal to the bus bit width (determines whether a DMA command from a controller is received…all configuration registers are programmed to define, for example, image information, bus information, and address information…a read engine of the NDMA core retrieves a predetermined number of bits (e.g. a bus width) of image data from the external memory and stores those bits in the read buffer of the NDMA core, see paras. [0087]-[0090]), and wherein the logical address of the read command changes with a dimension other than the lowest dimension of the to-be-read tensor data based on an order of the number carried in the read command (address, see paras. [0066]-[0069] and Figs. 5B-C, 6A).
As to claim 7, BAI’690 also discloses in response to a remainder of a quantity of lowest dimensions of the to-be-read tensor data and a quantity of pieces of data corresponding to the splitting width being greater than 0, the DMAC is configured to perform supplementation processing on the lowest dimension based on the quantity of pieces of data corresponding to the splitting width and the remainder (streaming of data refers to movement of data in a stripe, block by block, in response to a single NDMA command and repeated until stripe of data is moved to/from a buffer, see paras. [0062]-[0069], Figs. 5A-C).
As to claim 8, BAI’690 also discloses a reorder buffer (ROB), and the to-be-converted tensor data is to-be-output tensor data stored in a matrix buffer of the DMA (buffers such as read/write buffers and client buffers, see Fig. 7), and wherein the DMAC is configured to: sequentially read the to-be-output tensor data from the matrix buffer based on the bus bit width, and write the to-be-output tensor data into the TPB through the write port in the first direction, wherein the DMAC is configured to read, in response to the product of the quantity of rows of data being stored in the first direction of the TPB and the splitting width meeting the read port bit width (a read engine of the NDMA core retrieves a predetermined number of bits (e.g. a bus width) of image data from the external memory and stores those bits in the read buffer of the NDMA core, see paras. [0087]-[0090]), a third part of data of the to-be-output tensor data from the TPB through the read port in the second direction at the splitting width, splice the third part of data in the order of the first direction to obtain third tensor data, and store the third tensor data into the ROB in an order of reading the third tensor data from the read port, and wherein the DMAC is configured to generate a write command based on the third tensor data stored in the ROB (stream data blocks of a data stripe to/from an external memory of the NDMA core. In addition, the instructions loaded into the NPU may comprise program code to pre-process and post-process the data blocks in a buffer of the NDMA core during streaming of the data blocks, see paras. [0035], [0077] and Fig. 7; also note: the read engine is configured to transfer fragmented data from the external memory 760 into client memories (e.g. read buffer 722 and/or write buffer 732) for image processing or for configuration, see paras. [0074] and [0075]; and data conversion from image format to NPU data types for a read operation with conversion back to image format for 2D and 3D storage, see para. [0079]), wherein the write command carries a number that is specified based on an order of storing the third tensor data into the ROB, and the number carried in the write command indicates an order of writing the third tensor data into the external memory of the processor (streaming of data refers to movement of data in a stripe, block by block, in response to a single NDMA command (e.g., read/write) and repeated until stripe of data is moved to/from a buffer, see paras. [0062]-[0069], Figs. 5A-C).
As to claim 9, BAI’690 also discloses in response to a lowest dimension of the to-be-output tensor data being different from a preset lowest dimension, wherein the DMAC is configured to delete a supplemented part of the third tensor data based on the lowest dimension of the to-be-output tensor data and the preset lowest dimension before storing the third tensor data into the ROB (The read engine adds correspond paddings (left, right, top, bottom or all around a cube) or crops out unused pixels for pre-processing of the MDMA data….In operation, the MDMA core retrieves a full dword from the external memory and crops off unneeded pixels and re-aligns the pixels when writing to the read client RCLT. Cropping is also used to shift a block boundary when a stripe is in Dim0 direction and left padding is specified, see paras. [0078]-[0079], Figs. 6B and 8A).
Note claims 10, 19, and 20 recite similar limitations of claim 1. Therefore they are rejected based on the same reason accordingly.
Note claim 11 recites similar limitations of claim 2. Therefore it is rejected based on the same reason accordingly.
Note claim 12 recites similar limitations of claim 3. Therefore it is rejected based on the same reason accordingly.
Note claim 13 recites similar limitations of claim 4. Therefore it is rejected based on the same reason accordingly.
Note claim 14 recites similar limitations of claim 5. Therefore it is rejected based on the same reason accordingly.
Note claim 15 recites the corresponding limitations of claim 6. Therefore it is rejected based on the same reason accordingly.
Note claim 16 recites the corresponding limitations of claim 7. Therefore it is rejected based on the same reason accordingly.
Note claim 17 recites similar limitations of claim 8. Therefore it is rejected based on the same reason accordingly.
Note claim 18 recite similar limitations of claim 9. Therefore it is rejected based on the same reason accordingly.
Response to Arguments
Applicant's arguments filed 5/15/2026 have been fully considered but they are moot due to new grounds of rejection.
In summary, BAI’690 and Guo’424 teach the claimed limitations as set forth.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111(c).
In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
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/TITUS WONG/Primary Examiner, Art Unit 2181
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