DETAILED ACTION
This communication is in response to the application filed 1/18/24 in which claims 1-3 were presented for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Badaroglu (US 2023/0025068 A1; published Jan. 26, 2023) in view of Sumbul (US 2019/0042199 A1; published Feb. 7, 2019).
Regarding claim 1, Badaroglu discloses [a] learning system, comprising:
a plurality of analog compute blocks; and (Badaroglu ¶ 28 (“Aspects of the present disclosure provide apparatus, methods, processing systems, and computer-readable mediums for performing data-intensive processing, such as implementing machine learning models. Some aspects provide a hybrid neural network architecture using both compute-in-memory (CIM) and neural processing unit (NPU) processing elements (PEs), where the CIM PEs [e.g., analog compute blocks] and the NPU PEs can share resources (e.g., memory), can concurrently operate, and can transfer data from one type of PE to another type of PE within the same neural network layer or in different neural network layers (e.g., adjacent layers).”), ¶ 60 (“As used herein, the term “CIM” may refer to either or both analog CIM and digital CIM, unless it is clear from context that only analog CIM or only digital CIM is meant.”))
a plurality of analog-digital-analog compute blocks interleaved with the plurality of analog compute blocks, (Badaroglu ¶ 28 (“Some aspects provide a hybrid neural network architecture using both compute-in-memory (CIM) and neural processing unit (NPU) processing elements (PEs), where the CIM PEs and the NPU PEs [e.g., analog-digital compute blocks] can share resources (e.g., memory), can concurrently operate, and can transfer data from one type of PE to another type of PE within the same neural network layer or in different neural network layers (e.g., adjacent layers) [e.g., interleaved].”).
Badaroglu does not expressly disclose an analog-digital-analog compute block including an analog-to-digital converter, a digital compute unit, and a digital-to-analog converter (but see Sumbul ¶ 54 (“FIGS. 10A, 10B, and 11 illustrate examples of cascading multiple CIM arrays and multiple analog processors. FIG. 10A is a block diagram showing how CIM compute blocks can be cascaded using ADCs and digital processing to process, for example, two consecutive neural network layers. The first compute block (e.g., the CIM arrays 1000A and 1000B and the analog processor 1002A) is coupled with a second compute block (e.g., CIM arrays 1000C and 1000D and the analog processor 1002B) via an ADC 1006A [e.g., analog-to-digital converter] and a digital processor 1004 [e.g., digital compute unit]. The CIM arrays 1000A and 1000B of the first compute block can store a first layer of weights and inputs and the CIM arrays 1000C and 1000D of the second compute block can store a second layer of weights and inputs of a neural network. The weights and inputs from the CIM arrays 1000A and 1000B are input to the analog processor 1002A, where a multiply and accumulate operation is performed. The output of the MAC operation is then stored in the CIM array 1000D. To store the outputs from the first layer in the array 1000D, the outputs are converted to the digital domain via the ADC 1006A and interpreted and stored by the digital processor 1004. The inputs stored in the array 1000D [e.g., digital-to-analog converter] are then read and provided as analog voltages to the analog processor 1002B along with the analog inputs from the CIM array 1000C, which stores weights for the second layer of the neural network. The analog processor 1002B then performs a multiply and accumulate operation on the inputs and outputs an analog voltage. The analog voltage can then be transformed to the digital domain via a second ADC 1006B.”)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Badaroglu to incorporate the teachings of Sumbul to cascade the analog CIM with a digital CIM by converting the output of the analog CIM to a digital signal, processing the digital signal, and converting the digital output to an analog signal, at least because doing so would enable a hybrid neural network architecture which can transfer data from one type of PE to another type of PE within the same or different neural network layers.
Regarding claim 2, Badaroglu, in view of Sumbul, discloses the invention of claim 1 as discussed above. Badaroglu further discloses wherein an analog compute block includes a plurality of nodes coupled with at least one analog compute unit (Badaroglu ¶ 59 (“For example, a mobile device may include a memory device configured for storing data and performing CIM operations. The mobile device may be configured to perform an ML/AI operation based on data generated by the mobile device, such as image data generated by a camera sensor of the mobile device. A memory controller unit (MCU) of the mobile device may thus load weights from another on-board memory (e.g., flash or RAM) into a CIM array of the memory device and allocate input feature buffers and output (e.g., output activation) buffers. The processing device may then commence processing of the image data by loading, for example, a layer in the input buffer and processing the layer with weights loaded into the CIM array. This processing may be repeated for each layer of the image data, and the outputs (e.g., output activations) may be stored in the output buffers and then used by the mobile device for an ML/AI task, such as facial recognition.”)).
Regarding claim 3, Badaroglu, in view of Sumbul, discloses the invention of claim 1 as discussed above. Badaroglu further discloses wherein the digital compute unit is a digital-in-memory-compute unit (Badaroglu ¶ 60 (“As described above, conventional CIM processes may perform computation using analog signals, which may result in inaccuracies in the computation results, adversely impacting neural network computations. One emerging solution for analog CIM schemes is digital compute-in-memory (DCIM) schemes, in which computations are performed using digital signals.”)).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kendall, Jack, et al. "Training end-to-end analog neural networks with equilibrium propagation." arXiv preprint arXiv:2006.01981 (2020).
Chen, Jinwu, Tianzhu Xiong, and Xin Si. "A charge-digital hybrid compute-in-memory macro with full precision 8-bit multiply-accumulation for edge computing devices." 2022 IEEE 15th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC). IEEE, 2022.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAHID KHAN whose telephone number is (571)270-0419. The examiner can normally be reached M-F, 9-5 est.
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/SHAHID K KHAN/Primary Examiner, Art Unit 2146
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