DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. TW 112104860 , filed on 02/10/2023. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/19/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The disclosure is objected to because of the following informalities:
Par. 44, 46, 48, 60: refers to the second N-type transistor as MM2 but in fig. 3a, it’s MN2
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2 and 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20180019711 by Wang et al. in view of US 20110102084 by Kim et al.
Regarding claim 1, Wang teaches a power amplification output circuit (Fig. 4) comprising:
an output transformer comprising a first side inductor and a second side inductor (#115);
a cascode power amplifier (#107) electrically coupled between a pair of cascode differential input terminals (input coming into #107) and a pair of cascode differential output terminals (output coming out of #107) and electrically coupled to the first side inductor (#115) through the pair of cascode differential output terminals; and
an inverter-type power amplifier (#109a) electrically coupled between a pair of inverter-type differential input terminals (input going into #109a) and a pair of inverter-type differential output terminals (output coming out of #109a) and electrically coupled to the first side inductor (#115) through the pair of inverter-type differential output terminals;
wherein the cascode power amplifier (#107) is activated under a normal power output mode (Par. 36; the main amplification is on and amplifying the signal) to receive a pair of differential radio frequency input signals (#101) through the pair of cascode differential input terminals to perform power amplifying to the pair of differential radio frequency input signals and output the amplified differential radio frequency input signals to the output transformer (#115) through the pair of cascode differential output terminals and further to an antenna (Par. 9; Fig. 7 #706) through the second side inductor;
the inverter-type power amplifier (#109a) is activated under a back off power output mode (Par. 36) to receive the pair of differential radio frequency input signals through the pair of inverter-type differential input terminals to perform power amplifying to the pair of differential radio frequency input signals and output the amplified differential radio frequency input signals to the output transformer through the pair of inverter-type differential output terminals and further to the antenna through the second side inductor.
Wang doesn’t mention that the auxiliary amplifier #109a is an inverter-type, however, Kim teaches a multi-stage power amplifiers with the first stage consisting of inverters (Fig. 1, 2) in a cascode arrangement in which signals are output to a first side inductor L1. Since both Wang and Kim are analogous art, it would be obvious to a person of ordinary skill in the art to use the inverted transistor structure of Kim with the auxiliary power amplifier #109a in Wang due to the fact that they are used in the similar context of power amplifiers.
Regarding claim 2, the combination of Wang and Kim teaches the power amplification output circuit of claim 1, wherein the cascode power amplifier (Wang Fig. 4 #107) comprises:
a first cascode branch circuit comprising a first upper N-type transistor and a first lower N-type transistor coupled in series between a first terminal of the pair of cascode differential input terminals and a ground terminal (see annotated figure); and
a second cascode branch circuit comprising a second upper N-type transistor and a second lower N-type transistor coupled in series between a second terminal of the pair of cascode differential input terminals and the ground terminal (see annotated figure);
wherein the first upper N-type transistor and the second upper N-type transistor are electrically coupled to a power supply terminal through a center tap of the first side inductor (Wang #115 there’s a supply voltage node coupled to the center tap) and are controlled by an upper driving voltage;
the first lower N-type transistor and the second lower N-type transistor are controlled by a lower driving voltage and receive the pair of differential radio frequency input signals from the pair of cascode differential input terminals (the lower NMOS transistors in #107 receive the differential and bias signals that emanate from #405).
Wang Fig. 4 shows bias voltage lines connected to the gates of the upper NMOS transistors but the amount of bias that is applied to the cascode arrangement of NMOS transistors in #107 is not specified. However, biasing cascode amplifiers is very well known in the art. Fig. 1a and Col. 3 line 52-53 of US 5012123 by Ayasli et al. teaches a cascode amplifier circuit where the top transistor has an upper driving (bias) voltage and the bottom transistor has a lower driving (bias voltage).
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Annotated Fig. 4
Regarding claim 9, Wang teaches a signal transmission apparatus comprising:
a signal source circuit configured to generate a pair of differential radio frequency input signals (Fig. 1 #102; Fig. 7 #701);
a power amplification output circuit (Fig. 4), comprising:
an output transformer comprising a first side inductor and a second side inductor (#115);
a cascode power amplifier (#107) electrically coupled between a pair of cascode differential input terminals (input coming into #107) and a pair of cascode differential output terminals (output coming out of #107) and electrically coupled to the first side inductor (#115) through the pair of cascode differential output terminals; and
an inverter-type power amplifier (#109a) electrically coupled between a pair of inverter-type differential input terminals (input going into #109a) and a pair of inverter-type differential output terminals (output coming out of #109a) and electrically coupled to the first side inductor (#115) through the pair of inverter-type differential output terminals;
a mode control circuit configured to generate a mode control signal to the cascode power amplifier and the inverter-type power amplifier such that the cascode power amplifier and the inverter-type power amplifier operate in one of a normal power output mode and a back off power output mode (Wang Par. 47);
wherein the cascode power amplifier (#107) is activated under a normal power output mode (Par. 36; the main amplification is on and amplifying the signal) to receive a pair of differential radio frequency input signals (#101) through the pair of cascode differential input terminals to perform power amplifying to the pair of differential radio frequency input signals and output the amplified differential radio frequency input signals to the output transformer (#115) through the pair of cascode differential output terminals and further to an antenna (Par. 9; Fig. 7 #706) through the second side inductor;
the inverter-type power amplifier (#109a) is activated under a back off power output mode (Par. 36) to receive the pair of differential radio frequency input signals through the pair of inverter-type differential input terminals to perform power amplifying to the pair of differential radio frequency input signals and output the amplified differential radio frequency input signals to the output transformer through the pair of inverter-type differential output terminals and further to the antenna through the second side inductor.
Wang doesn’t mention that the auxiliary amplifier #109a is an inverter-type, however, Kim teaches a multi-stage power amplifiers with the first stage consisting of inverters (Fig. 1, 2) in a cascode arrangement in which signals are output to a first side inductor L1. Since both Wang and Kim are analogous art, it would be obvious to a person of ordinary skill in the art to use the inverted transistor structure of Kim with the auxiliary power amplifier #109a in Wang due to the fact that they are used in the similar context of power amplifiers.
Regarding claim 10, the combination of Wang and Kim teaches the power amplification output circuit of claim 9, wherein the cascode power amplifier (Wang Fig. 4 #107) comprises:
a first cascode branch circuit comprising a first upper N-type transistor and a first lower N-type transistor coupled in series between a first terminal of the pair of cascode differential input terminals and a ground terminal (see annotated figure); and
a second cascode branch circuit comprising a second upper N-type transistor and a second lower N-type transistor coupled in series between a second terminal of the pair of cascode differential input terminals and the ground terminal (see annotated figure);
wherein the first upper N-type transistor and the second upper N-type transistor are electrically coupled to a power supply terminal through a center tap of the first side inductor (Wang #115 there’s a supply voltage node coupled to the center tap) and are controlled by an upper driving voltage;
the first lower N-type transistor and the second lower N-type transistor are controlled by a lower driving voltage and receive the pair of differential radio frequency input signals from the pair of cascode differential input terminals (the lower NMOS transistors in #107 receive the differential and bias signals that emanate from #405).
Wang Fig. 4 shows bias voltage lines connected to the gates of the upper NMOS transistors but the amount of bias that is applied to the cascode arrangement of NMOS transistors in #107 is not specified. However, biasing cascode amplifiers is very well known in the art. Fig. 1a and Col. 3 line 52-53 of US 5012123 by Ayasli et al. teaches a cascode amplifier circuit where the top transistor has an upper driving (bias) voltage and the bottom transistor has a lower driving (bias voltage).
Allowable Subject Matter
Claims 3-8 and 11-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 11595075 by Mohammadnezhad et al. teaches parallel amplifiers that turn on an off based on circuit needs.
EP 2700160 by Presit teaches a differential cascode amplifier that has different bias values for the transistors.
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/NAREH SHAMIRYAN/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
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