DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
The response filed 05/27/2026 is accepted, in which, Applicant elects Species A without traverse. Applicant asserts Species A corresponds to Figs 4, 7-9, 18, and 19; and claims 1, 2, 5, 12-18, and 22-35. Claims 3, 4, 6-11, and 19-21 are withdrawn at this time. Claims 1 and 23 are independent with claims 1, 2, 5, 12-18, and 22-35 awaiting an action on the merits as follows.
Allowable Subject Matter
Claims 1, 2, 5, 12-18, and 22-35 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Regarding claim 1, prior art of record fails to teach or suggest:
A bipolar junction transistor with adjustable gain, comprising: a semiconductor substrate of a first conductivity type; a doped layer of the first conductivity type, which is formed on the semiconductor substrate of the first conductivity type; a doped well region of a second conductivity type, which is formed in the doped layer of the first conductivity type, and the second conductivity type is opposite to the first conductivity type, wherein a first heavily doped region of the second conductivity type, a second heavily doped region of the second conductivity type, a third heavily doped region of the first conductivity type, a fourth heavily doped region of the first conductivity type and a fifth heavily doped region of the first conductivity type are further disposed in the doped well region of the second conductivity type, the fifth heavily doped region of the first conductivity type is electrically coupled with a first pin, the third heavily doped region of the first conductivity type and the fourth heavily doped region of the first conductivity type are electrically connected in common and coupled with a second pin, the first heavily doped region of the second conductivity type and the second heavily doped region of the second conductivity type are spaced apart by the third heavily doped region of the first conductivity type, the fourth heavily doped region of the first conductivity type and the fifth heavily doped region of the first conductivity type, and wherein the first heavily doped region of the second conductivity type is further electrically connected with a sixth heavily doped region and the second heavily doped region of the second conductivity type is further electrically connected with a seventh heavily doped region, and wherein an eighth heavily doped region which is disposed adjacent to the sixth heavily doped region and a ninth heavily doped region which is disposed adjacent to the seventh heavily doped region are coupled with the second pin; and a first detection circuit disposed between the sixth heavily doped region and the eighth heavily doped region, and a second detection circuit disposed between the seventh heavily doped region and the ninth heavily doped region.
Emphasis on the underlined portion.
Regarding claim 23, prior art of record fails to teach or suggest:
A bipolar junction transistor with adjustable gain, comprising: a semiconductor substrate of a first conductivity type; a doped layer of the first conductivity type, which is formed on the semiconductor substrate of the first conductivity type; a doped well region of a second conductivity type, which is formed in the doped layer of the first conductivity type, and the second conductivity type is opposite to the first conductivity type, wherein a third heavily doped region of the first conductivity type, a fourth heavily doped region of the first conductivity type, a fifth heavily doped region of the first conductivity type, a tenth heavily doped region of the second conductivity type, an eleventh heavily doped region of the first conductivity type, a twelfth heavily doped region of the second conductivity type and a thirteenth heavily doped region of the first conductivity type are further disposed in the doped well region of the second conductivity type, the fifth heavily doped region of the first conductivity type is electrically coupled with a first pin, the third heavily doped region of the first conductivity type and the fourth heavily doped region of the first conductivity type are electrically connected in common and coupled with a second pin, and wherein the tenth heavily doped region of the second conductivity type and the eleventh heavily doped region of the first conductivity type are electrically connected in common, the twelfth heavily doped region of the second conductivity type and the thirteenth heavily doped region of the first conductivity type are electrically connected in common, and wherein the tenth heavily doped region of the second conductivity type and the eleventh heavily doped region of the first conductivity type are disposed on one side of the third heavily doped region of the first conductivity type, the fourth heavily doped region of the first conductivity type and the fifth heavily doped region of the first conductivity type, and the twelfth heavily doped region of the second conductivity type and the thirteenth heavily doped region of the first conductivity type are disposed on an opposite side of the third heavily doped region of the first conductivity type, the fourth heavily doped region of the first conductivity type and the fifth heavily doped region of the first conductivity type; and a first detection circuit disposed between the eleventh heavily doped region of the first conductivity type and the third heavily doped region of the first conductivity type, and a second detection circuit disposed between the thirteenth heavily doped region of the first conductivity type and the fourth heavily doped region of the first conductivity type.
Emphasis on the underlined portion.
To solve the concern of electrostatic discharge (ESD) in bipolar junction transistors it is common to use parasitic silicon-controlled rectifiers (SCR). Those designs using SCRs found in the search typically have a p-type substrate.
One prior art reference, Zhan (US 8994068 B2), found in the search describes how it is commonplace to provide an ESD protection clamp across the terminals of modern integrated circuits and electronic assemblies that are at risk of damage due to ESD events.
ESD protection clamps are circuit elements used to protect integrated circuit (IC) devices from voltage and current spikes that may be associated with an electrostatic discharge. To protect an IC device, an ESD clamp is connected between an input or output terminal of the device and a ground or common terminal. During normal operation, the ESD clamp does not conduct. But when subjected to an excessive voltage, the ESD clamp becomes conductive, conducting current to ground and limiting voltage to desired safe level, thereby protecting the IC to which the ESD clamp is connected (Zhan, [Col 3, Ln 19-28]).
Zhan goes on to teach when protecting a device having a number of terminals, ESD protection devices may be connected across each terminal and a ground terminal to provide comprehensive protection to the IC (Zhan, [Col 4, Ln 2-6]).
However, as with other similar prior art found in the search, Zhan's design does not have heavily doped regions embedded in a doped well of the second conductivity type formed in a doped layer of the first conductivity type, on a substrate of the first conductivity type, as claimed in claims 1 and 23; nor the two detection circuits connected to certain heavily doped regions embedded in the doped well region of the second conductivity type.
As with Zhan, similar prior art of record typically has differently organized doped well regions compared to the instant application to create the ESD protection for high versus low voltage events.
Another reference found in the search, Ko (US 20180012883 A1), discloses a p-type well horizontally adjacent to a n-type well in order for the ESD protection to properly mitigate an ESD event. Ko teaches several embodiments, but fails to disclose two separate detection circuits connected to heavily doped regions embedded in a second conductivity type well embedded in a first conductivity type doped layer on a first conductivity type substrate as claimed in claims 1 and 23.
When considering two detection circuits, one example of prior art of record is Altolaguirre (US 10147717 B2). Altolaguirre, cited as CN106505066A in the disclosure, teaches an ESD protection circuit that utilizes a dual silicon-controlled rectifier (DSCR) device with a triggering circuit that symmetrically triggers the DSCR device in response to polarities of the ESD stress in order to achieve good ESD robustness while maintaining low standby leakage current and relatively small silicon footprint (Altolaguirre, [Col 3, Ln 16-19]).
Altolaguirre's design is different than the claimed invention in that the ESD device disclosed contains a p-type well embedded between two n-type wells. So, while Altolaguirre teaches two detection circuits, the structure of the device is different than the bipolar junction transistor claimed in claims 1 and 23.
Altolaguirre states the DSCR device may be implemented by N-well based or P-well based DSCR (nDSCR or pDSCR). Similarly, the transistors of the triggering circuit may be implemented by n-type or p-type transistors. Therefore, the doping type of the wells and doping regions specified here (e.g., N-type, P-type, N +-type, P+-type, etc.) are to make the disclosure more comprehensible, however, it is not intended to limit the disclosure. The doping type of the regions are based on the type of the DSCR (Altolaguirre, [Col 8, Ln 35-44]). However, Examiner does not interpret this description to provide obvious insight for one of ordinary skill in the art to rearrange the elements of Altolaguirre to arrive at the claimed invention.
Wang (US 20150194808 A1), cited as foreign reference TW201528476A by Applicant, discloses a PNP transistor and an electronic element having an N-type well in the internal circuit that can construct a parasitic silicon-controlled rectifier (SCR). Fig 2 of Wang shows the internal circuit is generally configured with a guard ring and a regulation capacitor to prevent a noise interference and regulate the power voltage VDD (Wang, [0020]).
Wang goes on to teach the protection capability of the ESD protection device can be further improved through the diode and the resistor (Wang, [0025]), but fails to disclose two such detection circuits.
No prior art found in the search discloses the bipolar junction transistor as claimed in claims 1 and 23. Therefore, if claims 1 and 23 were written to overcome the 112b rejection below, claims 1, 2, 5, 12-18, and 22-35 would be allowable.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 2, 5, 12-18, and 22-35 are rejected for indefiniteness.
Regarding claim 1, the claim recites, "for being operable to respectively generate a first output voltage and a second output voltage;" "receiving the first output voltage;" and "receiving the second output voltage … for determining at least one current path when the input voltage varies under different operating conditions." The claim is indefinite because while claim 1 begins by reciting an apparatus/device, claim 1 further includes a method of using the structure in "for being operable to respectively generate a first output voltage and a second output voltage;" " receiving the first output voltage;" and "receiving the second output voltage … for determining at least one current path when the input voltage varies under different operating conditions." The claim is not considered a product by process claim because the claim does not state that any feature was made using "for being operable to respectively generate a first output voltage and a second output voltage;" " receiving the first output voltage;" and "receiving the second output voltage … for determining at least one current path when the input voltage varies under different operating conditions." The claim recites that the apparatus/device is used to perform these operations.
A single claim that includes both an apparatus and a method of using the apparatus/device is indefinite (See MPEP 2173.05(p)(II)). It is unclear if infringement would occur when the apparatus/device is created or when the apparatus/device is used in the performing of "for being operable to respectively generate a first output voltage and a second output voltage;" " receiving the first output voltage;" and "receiving the second output voltage … for determining at least one current path when the input voltage varies under different operating conditions."
Regarding claims 14, 15, 33, and 34, the claims recite, "the first detection circuit and the second detection circuit generate the first output voltage and the second output voltage as the power supply voltage;" "so as to provide a positive [(negative) in claims 15 and 34] surged operating mode;" and "the first detection circuit and the second detection circuit generate the first output voltage and the second output voltage having a virtual ground voltage." The claims are indefinite because while claim 14 and 15 begin by reciting an apparatus/device, claims 14 and 15 further include a method of using the structure in "the first detection circuit and the second detection circuit generate the first output voltage and the second output voltage as the power supply voltage;" "so as to provide a positive [(negative) in claims 15 and 34] surged operating mode;" and "the first detection circuit and the second detection circuit generate the first output voltage and the second output voltage having a virtual ground voltage." The claims are not considered a product by process claims because the claims do not state that any feature was made using "the first detection circuit and the second detection circuit generate the first output voltage and the second output voltage as the power supply voltage;" "so as to provide a positive [(negative) in claims 15 and 34] surged operating mode;" and "the first detection circuit and the second detection circuit generate the first output voltage and the second output voltage having a virtual ground voltage." The claims recite that the apparatus/device is used to perform these operations.
A single claim that includes both an apparatus and a method of using the apparatus/device is indefinite (See MPEP 2173.05(p)(II)). It is unclear if infringement would occur when the apparatus/device is created or when the apparatus/device is used in the performing of "the first detection circuit and the second detection circuit generate the first output voltage and the second output voltage as the power supply voltage;" "so as to provide a positive [(negative) in claims 15 and 34] surged operating mode;" and "the first detection circuit and the second detection circuit generate the first output voltage and the second output voltage having a virtual ground voltage."
Regarding claim 17, which states, "which is constructed by from the fifth heavily doped region… " is indefinite because "constructed by from" is unclear what the fifth heavily doped region and following elements are doing. To further prosecution, Examiner will assume the claim should read, "which is constructed [[by]] from the fifth heavily doped region…" Proper correction is required.
Regarding claim 18, the claim recites, "at least one inversion layer is formed underneath the first conducting layer and the second conducting layer." The claim is indefinite because while claim 18 begins by reciting an apparatus/device, claim 18 further includes a method of using the structure in "at least one inversion layer is formed underneath the first conducting layer and the second conducting layer." The claim is not considered a product by process claim because the claim does not state that any feature was made using "at least one inversion layer is formed underneath the first conducting layer and the second conducting layer." The claim recites that the apparatus/device is used to perform these operations.
A single claim that includes both an apparatus and a method of using the apparatus/device is indefinite (See MPEP 2173.05(p)(II)). It is unclear if infringement would occur when the apparatus/device is created or when the apparatus/device is used in the performing of "at least one inversion layer is formed underneath the first conducting layer and the second conducting layer."
Regarding claim 23, the claim recites, "for being operable to respectively generate a first output voltage and a second output voltage;" and "for determining at least one current path when the input voltage varies under different operating conditions." The claim is indefinite because while claim 23 begins by reciting an apparatus/device, claim 23 further includes a method of using the structure in "for being operable to respectively generate a first output voltage and a second output voltage;" and "for determining at least one current path when the input voltage varies under different operating conditions." The claim is not considered a product by process claim because the claim does not state that any feature was made using "for being operable to respectively generate a first output voltage and a second output voltage;" and "for determining at least one current path when the input voltage varies under different operating conditions." The claim recites that the apparatus/device is used to perform these operations.
A single claim that includes both an apparatus and a method of using the apparatus/device is indefinite (See MPEP 2173.05(p)(II)). It is unclear if infringement would occur when the apparatus/device is created or when the apparatus/device is used in the performing of "for being operable to respectively generate a first output voltage and a second output voltage;" and "for determining at least one current path when the input voltage varies under different operating conditions."
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zhan (US 8994068 B2) - N-type substrate ESD device
Ko (US 20180012883 A1) - basic ESD for H/L Voltage
Altolaguirre (US 10147717 B2) - 2 detection circuits
Wang (US 20150194808 A1) - SCR with guard ring
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jeremy D Watts whose telephone number is (703)756-1055. The examiner can normally be reached M-R 8:00am-4:30pm, F 8:00-3pm EST.
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/JEREMY DANIEL WATTS/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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