DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgement is made to a claim of priority to Korean application KR10-2023-0010240 filed on January 26th, 2023. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) filed on January 19th, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is being considered by the examiner.
Election/Restrictions
Applicant's election without traverse of Group I (claims 1-10) and species A (fig. 2 & 3) in the reply filed on June 6th, 2026 is acknowledged.
The requirement is made FINAL, claims 1-10 are being examined on their merits
and all non-elected claims (i.e. claims 11-20) are withdrawn from consideration at this time.
Drawings
The drawings are objected to under 37 CFR 1.83(a) because they fail to show a clear relationship between the schematic diagram of a semiconductor device shown in figure 1, the cross-sectional view of the semiconductor device shown in figure 2, and the schematic perspective view of a semiconductor device shown in figure 12-14 as described in the specification. In figure 1 the only details that are clearly shown are where the first substrate region, dummy region, and second substrate region are with relation to one another and it is unclear what the applicant is considering as the gate structures, diffusion break structures, etc. in that figure. Similarly, in figure 12, there are no indications of what cross-section, or what parts of the described device relate to the figure 2 cross section. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
In addition to Replacement Sheets containing the corrected drawing figure(s), applicant is required to submit a marked-up copy of each Replacement Sheet including annotations indicating the changes made to the previous version. The marked-up copy must be clearly labeled as “Annotated Sheets” and must be presented in the amendment or remarks section that explains the change(s) to the drawings. See 37 CFR 1.121(d)(1). Failure to timely submit the proposed drawing and marked-up copy will result in the abandonment of the application.
Specification
The following guidelines illustrate the preferred layout for the specification of a utility application. These guidelines are suggested for the applicant’s use.
Arrangement of the Specification
As provided in 37 CFR 1.77(b), the specification of a utility application should include the following sections in order. Each of the lettered items should appear in upper case, without underlining or bold type, as a section heading. If no text follows the section heading, the phrase “Not Applicable” should follow the section heading:
(a) TITLE OF THE INVENTION.
(b) CROSS-REFERENCE TO RELATED APPLICATIONS.
(c) STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT.
(d) THE NAMES OF THE PARTIES TO A JOINT RESEARCH AGREEMENT.
(e) INCORPORATION-BY-REFERENCE OF MATERIAL SUBMITTED ON A READ-ONLY OPTICAL DISC, AS A TEXT FILE OR AN XML FILE VIA THE PATENT ELECTRONIC SYSTEM.
(f) STATEMENT REGARDING PRIOR DISCLOSURES BY THE INVENTOR OR A JOINT INVENTOR.
(g) BACKGROUND OF THE INVENTION.
(1) Field of the Invention.
(2) Description of Related Art including information disclosed under 37 CFR 1.97 and 1.98.
(h) BRIEF SUMMARY OF THE INVENTION.
(i) BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S).
(j) DETAILED DESCRIPTION OF THE INVENTION.
(k) CLAIM OR CLAIMS (commencing on a separate sheet).
(l) ABSTRACT OF THE DISCLOSURE (commencing on a separate sheet).
(m) SEQUENCE LISTING. (See MPEP § 2422.03 and 37 CFR 1.821 - 1.825). A “Sequence Listing” is required on paper if the application discloses a nucleotide or amino acid sequence as defined in 37 CFR 1.821(a) and if the required “Sequence Listing” is not submitted as an electronic document either on read-only optical disc or as a text file via the patent electronic system.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 5, 9, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US20220320312A1) in view of Liu et al. (US9570442B1) for the following reasons:
Regarding claim 1;
Park et al. teaches a semiconductor device (e.g. Fig. 3A+3C ref 100b) comprising: a substrate having a first region and a second region spaced apart from each other (e.g. Fig. 3A+3C ref 101, ref 105W, 105N); a plurality of first gate structures disposed in the first region, spaced apart from each other in a first horizontal direction, extending in a second horizontal direction perpendicular to the first horizontal direction, and having a first width (e.g. Fig. 3A+3C ref 160A); a plurality of second gate structures disposed in the second region, spaced apart from each other in the first horizontal direction, extending in the second horizontal direction, and having a second width greater than the first width (e.g. Fig. 3A+3C ref 160B); and a plurality of dummy diffusion breaks arranged between the first region and the second region, extending in the second horizontal direction (e.g. Fig. 3A+3C, ref 170,171b,172).
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Park et al. is silent to a plurality of single diffusion breaks arranged between the plurality of first gate structures and extending in the second horizontal direction as claimed.
However, Liu et al. teaches a FinFET device with a self-aligned single diffusion break structure (e.g. Fig. 2B ref 202).
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At the effective time of filing, it would have been obvious to someone having ordinary
skill in the art to incorporate the self-aligned single diffusion break structure taught in Liu et al. into the semiconductor device structure taught in Park et al. because the inclusion of the single diffusion breaks between adjacent source/drain regions would apply a stress to adjacent channels which would increase carrier mobility in both channels (e.g. Liu et al., detailed description “… the self-aligned SDB isolation structure applies stress to a first channel corresponding to the first FinFET and to a second channel corresponding to the second FinFET. Applying such channel stress can increase carrier mobility within the first and second channels, thus increasing the performance of the first and second FinFETs.”), leading to an improved FinFET device structure with improved electrical properties.
Regarding claim 2;
Park et al. and Liu et al. are silent to an explicit teaching of the width of the dummy diffusion region and self-aligned single diffusion break respectively as claimed.
However, at the effective time of filing, it would have been obvious to someone having ordinary skill in the art to form the incorporated self-aligned single diffusion breaks taught in Liu et al. and the dummy diffusion break structure taught in Park et al. with substantially the same width because doing so would reduce the size of the resulting product, leading to a more efficient chip area usage and reduced manufacturing cost. Further, a change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04.
Regarding claim 5;
Park et al. further teaches a semiconductor device further comprising an interlayer insulating layer, wherein: the interlayer insulating layer surrounds each of the dummy diffusion breaks in the first horizontal direction (e.g. Fig. 1A-1B ref 190), and a material of the dummy diffusion breaks has a lower etch rate than a material of the interlayer insulating layer (e.g. Detailed description [0064] “The interlayer insulating layer 190 may include, for example, at least one of an oxide, a nitride, and an oxynitride, and may include a low-k material.”, [0058] “… the dummy structure 170 may include an insulating isolation pattern 178 and a spacer pattern 174 covering at least one side of the insulating isolation pattern 178… The insulating isolation pattern 178 may include at least one of, for example, SiO, SiN, SiCN, SiOC, SiON and SiOCN.”).
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Park et al. is silent to the interlayer insulating layer surrounding the plurality of single diffusion breaks arranged between the plurality of first gate structures and extending in the second horizontal direction as claimed.
However, Liu et al. teaches a FinFET device with a self-aligned single diffusion break structure (e.g. Fig. 2B ref 202).
At the effective time of filing, it would have been obvious to someone having ordinary
skill in the art to form the interlayer insulating layer taught in Park et al. to surround the incorporated self-aligned single diffusion breaks taught in Liu et al. because surrounding the single diffusion breaks taught in Liu et al. in the interlayer insulating material taught in Park et al. serves to further electrically isolate device elements from other active elements in the resulting semiconductor device such as the source/drain, and channel elements leading to a more robust device.
Regarding claim 9;
Park et al. further teaches a fin-type active pattern that is arranged below the first gate structures in a vertical direction perpendicular to the first horizontal direction and the second horizontal direction (e.g. see examiner markup).
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Regarding claim 10;
Park et al. further teaches a plurality of stacked nanosheets (under BRI the examiner is interpreting “nanosheet” to encompass a stacked sheet/layer structure in lieu of applicant explicit definition of “nanosheet” in specification) that are arranged below the first gate structures in a vertical direction perpendicular to the first horizontal direction and the second horizontal direction (e.g. see examiner markup).
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Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US20220320312A1) in view of Liu et al. (US9570442B1), further in view of Rastogi et al. (US10361198B2) for the following reasons:
Regarding claim 8;
Park et al. and Liu et al. teach the semiconductor device as claimed in claim 1.
Park et al. is silent to the plurality of dummy diffusion breaks being separated by a constant distance in the first horizontal direction as claimed.
However, Rastogi et al. teaches a semiconductor device in figure 1 which includes a dummy region (e.g. fig. 1 ref DX) disposed between a first and second active region (e.g. Fig. 1 ref RX1, RX2, Detailed description [0023] “…a dummy region DX may be arranged between the first and second active regions RX1 and RX2”) which includes a plurality of dummy fins (interpreted to function in an identical manner as diffusion breaks) spaced apart by a constant distance (e.g. fig. 1 ref DF, Detailed description [0025] “Selectively, in the dummy region DX, a plurality of dummy fin active regions DF may be arranged to protrude from the substrate 110.”)
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At the effective time of filing, it would have been obvious to someone having ordinary
skill in the art to form the dummy structure taught in Park et al. as the laterally spaced plurality of dummy structures taught in Rastogi et al. because providing multiple dummy/diffusion break structures between the two active regions provides redundant electrical isolation structures, ensuring that one device does not interfere with the other during operation.
Allowable Subject Matter
Claims 3-4, and 6-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM ROBERT MANN whose telephone number is (571)270-0210. The examiner can normally be reached Monday thru Thursday 0800-1800 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM ROBERT MANN/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights