DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/14/2025 has been entered.
Response to Amendment
The amendments filed 11/14/2025 have been accepted. Claims 1-19 are still pending. Claims 1 and 17 are amended. Applicant’s amendments to the claims have overcome each and every 112 rejection previously set forth in the Final Office Action mailed 8/14/2025.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 5, 7, 8, 11, 12, and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Glasco et al. (US Patent 8,271,734, hereafter referred to as Glasco) in view of Mayhew et al. (US PGPub 2005/0228952, hereafter referred to as Mayhew) in view of Swoboda (US PGPub 2006/0259828).
Regarding claim 1, Glasco teaches an apparatus comprising: cache circuitry providing a plurality of cache lines to store data for access by a processing element, and cache control circuitry arranged to control storage of data in the cache circuitry (Fig. 5A, Col. 10, lines 40-59, shows the cache system which includes control circuitry that is used to manage the cache and receive requests from a CPU (processing element)), wherein the cache control circuitry is arranged to manage storage of data within the cache circuitry for data blocks of size X exceeding a size of data that is storable within a single cache line of the cache circuitry (Fig. 5B, Col. 12, lines 25-46, shows the various formats that the data can be stored in wherein in the uncompressed stated the data takes up two cache lines), wherein the cache control circuitry is arranged, for each data block to be stored in the cache circuitry, to determine in which state of a plurality of states to store that data block in the cache circuitry, the plurality of states comprising an uncompressed state where the data block is stored within a plurality Y of cache lines and at least one compressed state where the data block is represented in a form occupying less than Y cache lines within the cache circuitry, based on evaluating data of that data block to determine whether there is any available state that would allow that data block to be stored in a compressed state within the cache (Fig. 5B, Col. 12, lines 25-46, as stated previously, shows the various states the data can be stored in which can be uncompressed or compressed with a particular ratio. This means that a determination of which format to use has to be made when storing the data. Fig. 5B, Col. 12, lines 25-46, as stated previously, there is an uncompressed state that can be stored in two cache lines and compressed versions that can be stored in one cache line or half a cache line. This means that a determination of which format to use has to be made when storing the data meaning the data would have to be evaluated. This is confirmed by looking at Fig. 6B and Col. 13, lines 24-57 which outline the process of writing data), and the cache control circuitry is arranged to maintain a plurality of metadata entries in memory (Col. 11, lines 30-53, describes the tags (metadata entries) that are used to manage the data), where each metadata entry is associated with a data block of size X and is arranged to identify which state has been chosen by the cache control circuitry to represent that data block when stored in the cache circuitry (Col. 11, lines 30-53, the metadata associated with the data in the cache will also have information specifying the format (state) that the data is stored in based on what was chosen for the data). Glasco does not teach cache control circuitry to control storage of data with associated memory addresses in main memory in the cache circuitry, and metadata entries in the main memory.
Mayhew teaches cache control circuitry to control storage of data with associated memory addresses in main memory in the cache circuitry (Paragraphs [0027] and [0029], states that data stored in the cache can be associated with main memory elements meaning there would be an associated main memory address associated with the data as well), and metadata entries (Paragraph [0038], shows the table listing the cache line which represent the data in the cache and would have a corresponding location in the main memory as the data exists in both the cache and main memory). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Glasco to utilize the invalidation process of Mayhew so that the amount of traffic created is minimized (Mayhew, Paragraph [0025]). Glasco and Mayhew do not explicitly teach a plurality of metadata entries in the main memory.
Swoboda teaches a plurality of metadata entries in the main memory (Fig. 1 and Paragraph [0028], shows the program page attribute table that is stored in the main memory). Since both Glasco/Mayhew and Swoboda teach storing metadata entries it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the prior art elements according to known methods by modifying the teachings of Glasco and Mayhew with that of Swoboda by also storing metadata entries in multiple memories to obtain the predictable result of a plurality of metadata entries in the main memory (as all this does is store additional metadata entries in the main memory).
Regarding claim 2, Glasco, Mayhew, and Swoboda teach all the limitations to claim 1. Glasco further teaches wherein the at least one compressed state comprises a data compression compressed state where the data forming a given data block is subjected to a compression algorithm to generate a compressed form of that data occupying a number of cache lines less than Y (Fig. 5B, Col. 12, lines 25-46, as stated in the rejection to claim 1, since the data is being compressed with a certain ratio it means that there has to be a compression algorithm being used to ensure compliance). The combination of and reason for combining are the same as those given in claim 1.
Regarding claim 5, Glasco, Mayhew, and Swoboda teach all the limitations to claim 1. Glasco further teaches wherein: the cache control circuitry is responsive to a write transaction issued by the processing element providing a memory address indication for an item of data to be written into the cache circuitry, to determine with reference to the memory address indication an associated data block, to determine an updated version of the associated data block produced by writing the item of data to the associated data block, to store the updated version of the associated data block in a given state chosen in dependence on the data forming the updated version of the associated data block, to store the updated version of the associated data block in a given state chosen in dependence on the data forming the updated version of the associated data block, and to update the metadata entry provided for the associated data block as required to identify the given state (Fig. 6B, Col. 13, lines 24-57, describes the process of performing a write operation which involves first receiving a write request from a client, using the tags to look up the address and determine a target data format. Then it will write the data to the cache line and update any metadata that is required (particularly if an eviction had to occur)). The combination of and reason for combining are the same as those given in claim 1.
Regarding claim 7, Glasco, Mayhew, and Swoboda teach all the limitations to claim 1. Glasco further teaches wherein when the item of data specified by the write transaction is less than size X, the cache control circuitry is arranged, at least in the presence of a qualifying condition, to perform a lookup in the cache circuitry to seek to obtain remaining data of the associated data block from the cache circuitry if available, so as to enable the updated version of the associated data block to be produced (Fig. 6B, Col. 13, lines 41-57, describes the part of the write process when only a partial tile is to be written. In this case the control circuitry will read out the rest of the cache line that the data is to be stored in, combine the new data with the old and then write the combination back to the cache line). The combination of and reason for combining are the same as those given in claim 1.
Regarding claim 8, Glasco, Mayhew, and Swoboda teach all the limitations to claim 1. Glasco further teaches wherein the cache control circuitry is arranged to access the metadata entry for the associated data block (Fig. 6B, Col. 13, lines 24-57, as stated in the rejection to claim 5, the metadata is accessed when performing any write request), and to determine that the qualifying condition is present when the metadata entry identifies the associated data block as being in the uncompressed state (Fig. 6B, Col. 13, lines 41-57, shows that the associated data can be uncompressed and since the metadata is accessed first it means the determination of the format (compressed/uncompressed) is made before determining the qualifying condition). The combination of and reason for combining are the same as those given in claim 1.
Regarding claim 11, Glasco, Mayhew, and Swoboda teach all the limitations of claim 1. Mayhew further teaches wherein: when the cache control circuitry causes the state associated with a given data block stored in the cache circuitry to be changed, the cache control circuitry is arranged to cause invalidation of any cache lines in the cache storage that will store stale data as a result of the change of state (Paragraph [0031], states that a data element can be modified (state changes) which then causes data in other caches to be invalidated as the copies are now stale). The combination of and reason for combining are the same as those given in claim 1.
Regarding claim 12, Glasco, Mayhew, and Swoboda teach all the limitations to claim 1. Glasco further teaches wherein: the cache control circuitry is responsive to a read transaction issued by the processing element providing a memory address indication for an item of data to be read from the cache circuitry, to determine with reference to the memory address indication an associated data block, to access the metadata entry for that associated data block to determine the state in which the associated data block is stored, and to process the read request in dependence on the determined state for the associated data block (Fig. 6A, Col. 13, lines 1-23, describes the process of reading data wherein a read request is received, a tag lookup is performed to determine the location of the data and the format it is in, followed by reading of the data from the identified location). The combination of and reason for combining are the same as those given in claim 1.
Regarding claim 17, claim 17 is the method claim associated with claim 1. Since Glasco, Mayhew, and Swoboda teach all the limitations to claim 1, they also teach all the limitations to claim 17; therefore the rejection to claim 1 also applies to claim 17.
Regarding claim 18, claim 18 is the system claim associated with claim 1. Since Glasco, Mayhew, and Swoboda teach all the limitations to claim 1 and Glasco further teaches at least one packaged chip; at least one system component; and a board, wherein the at least one packaged chip and the at least one system component are assembled on the board (Fig. 1 and Col. 3, lines 5-41, shows the system which contains components that are made up of packaged chips on a board), they also teach all the limitations to claim 18; therefore ethe rejection to claim 1 also applies to claim 18.
Regarding claim 19, claim 19 is the product claim associated with claim 18. Since Glasco, Mayhew, and Swoboda teach all the limitations of claim 18 and Glasco further teaches the system of claim 18 assembled on a further board with at least one other product component (Fig. 1 and Col. 3, lines 5-41, shows multiple components all of which are separate components), they also teach all the limitations of claim 19; therefore the rejection to claim 18 also applies to claim 19.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Glasco, Mayhew, and Swoboda in view of Diamand et al. (US PGPub 2019/0095331, hereafter referred to as Diamand).
Regarding claim 3, Glasco, Mayhew, and Swoboda teach all the limitations of claim 1. Glasco and Mayhew do not teach wherein the at least one compressed state comprises a zero detected state where the data in a given data block associated with at least one cache line is determined to be all zero, the all zero data is not stored in the cache circuitry and the metadata entry associated with the given data block is arranged to identify the data within the given data block that is all zero.
Diamand teaches wherein the at least one compressed state comprises a zero detected state where the data in a given data block associated with at least one cache line is determined to be all zero, the all zero data is not stored in the cache circuitry and the metadata entry associated with the given data block is arranged to identify the data within the given data block that is all zero (Paragraphs [0049] and [0058], describes the various compression methods which includes all zeros compression wherein if the data to be stored is all zeros the metadata associated with the data will be made to indicate that the data is all zeros and the data itself will not be stored). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Glasco, Mayhew, and Swoboda to utilize the various compression methods of Diamand so as to improve system memory performance (Diamand, Paragraph [0010]).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Glasco, Mayhew, and Swoboda in view of Avudaiyappa et al. (US PGPub 2013/0238874, hereafter referred to as Avudaiyappa).
Regarding claim 13, Glasco, Mayhew, and Swoboda teach all the limitations of claim 1. Glasco, Mayhew, and Swoboda do not teach comprising at least one metadata cache in which to cache metadata entries, each metadata cache providing cache lines in which to store a number of metadata entries, and a size of the cache lines in a given metadata cache being dependent on a location of the metadata cache within the apparatus.
Avudaiyappa teaches at least one metadata cache in which to cache metadata entries, each metadata cache providing cache lines in which to store a number of metadata entries (Fig. 1A and Paragraphs [0021]-[0023], states the existence of TLBs (metadata cache) that is used to cache page table entries. While the term cache line is not explicitly used, as the TLB is storing entries it means that a cache line or equivalent unit of data is being used to store the entries), and a size of the cache lines in a given metadata cache being dependent on a location of the metadata cache within the apparatus (Paragraph [0021]-[0023], one of ordinary skill would recognize that the unit of data being used to store the entries would have to be dependent upon the memory device the TLB resides as it would have to conform to the storage elements of that memory device). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Glasco, Mayhew, and Swoboda to use the TLB setup of Avudaiyappa so the overhead incurred from such software maintenance can be avoided (Avudaiyappa, Paragraph [0032]).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Glasco, Mayhew, and Swoboda in view of Geng et al. (US PGPub 2023/0236979, hereafter referred to as Geng).
Regarding claim 16, Glasco, Mayhew, and Swoboda teach all the limitations of claim 1. Glasco, Mayhew, and Swoboda do not teach wherein the plurality of states are chosen so as to remove a need for a read-modify-write operation in at least one scenario when a data block stored in the cache circuitry is updated.
Geng teaches wherein the plurality of states are chosen so as to remove a need for a read-modify-write operation in at least one scenario when a data block stored in the cache circuitry is updated (Paragraph [0073], states that one of the possible scenarios is an all zero scenario where the data is all zeros which would result in only a read-modify write being performed for the metadata while the read-modify-write for the data itself is skipped (unneeded)). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Glasco, Mayhew, and Swoboda to utilize the all zero method of Geng so to minimize the overheads of traditional compression systems (Geng, Paragraph [0003]).
Allowable Subject Matter
Claims 4, 6, 9, 10, 14, and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 11/14/2025 have been fully considered but they are not persuasive. The applicant first argues that Glasco does not teach storing data in a particular state based on evaluating the data. The examiner respectfully disagrees. As stated in the rejection to claim 1, Glasco in Fig. 6B and Col. 13, lines 24-56 goes through the process of writing data to a cache line which does require evaluation of the data. It should be noted the claims do not specify how the data is evaluated to determine which state to store the data in.
Regarding the argument against Mayhew, the argument is moot as the applicant amended the claim to overcome the rejection. To address this, new reference Swoboda ahs been incorporated into the rejection to help teach the amended limitation to the independent claims.
Conclusion
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/NICHOLAS A. PAPERNO/Examiner, Art Unit 2132