Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is in response to the Amendment filed 01/12/2026. In the instant Amendment, claims 1-15 and 17-20 are amended; claims 1, 18 and 20 are independent claims. Claims 1-20 are pending in this application. THIS ACTION IS MADE FINAL.
Response to Arguments
The claim objection to claims 2-16 is withdrawn.
The 35 U.S.C. 112(f) claim interpretation has been maintained.
The 35 U.S.C. 101 rejection to claims 1-20 as being directed to an abstract idea for a mental process has been withdrawn.
Applicant’s arguments with respect to claims 1, 18 and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: a predictor configured to: analyze/predict/select (claim 1); an active state predictor configured to indicate (claim 4); a steady state predictor configured to indicate a positive event and to indicate a negative event (claim 5); the predictor is configured to predict (claim 7); a transition predictor operable to: analyze/identify/set (claim 11) and a sequence predictor configured to analyze/to increase (claim 12).
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 18 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Moore et al (“Moore,” US 20070271405).
Regarding claim 1, Moore discloses an access controller configured to control access to a shared resource by a plurality of accessors operable to issue requests for access to the shared resource, (Moore, [0002], Arbiters are used in computer systems to control access to a common bus used by multiple devices. Arbiters insure that only a single device uses the bus at one time; [0017], PCI Bridge 110 [access controller] contains an arbiter 208 [access controller] shown in FIG. 2 which grants access to the devices sharing bus 112 [shared resource]. Only one device is granted control of bus 112 at one time in order to initiate transactions on that bus and Signals comprising bus 112 include unique (i.e., out-of-band dedicated signal lines for each PCI device) request and grant signals between each PCI device 114, 116, 118, and 120 [plurality of accessors] and arbiter 208 in PCI bridge 110; [0023] request signals from each device)
the access controller comprising a predictor configured to: (Moore, Abstract, A PCI bridge device includes an arbiter that uses state information comprised of knowledge of the bus protocol and a history of recent transactions to predict the type of transaction a requestor will issue; [0018], The request preprocessor 216 includes transaction history and data availability logic 212, request masking logic 210, and feature enables 214; [0007], an arbiter uses state information comprised of knowledge of the bus protocol and a history of recent transactions to predict the transaction a requester will issue)
predict a future request state of at least one of the accessors based on a type of at least one event determined based, at least in part, on an analysis of an activity of an accessor; (Moore, [0020], Input # 1 is generated by the transaction history and data availability logic 212. This input can be a single logic bit that records the occurrence of the issuance of a retry by target logic 202 to the associated device 114, 116, 118, or 120 in response to that device issuing a read transaction on PCI bus 112; [0021], Input # 2 in the truth table in FIG. 3 is also generated by the transaction history and data availability logic 212. This input further defines the type of retry detected as being a Disconnect Without Data issued during the first data phase of a read transaction issued by the associated PCI device on PCI bus 112. This input, once set valid, will remain valid until at least one of the requested data is delivered to the requesting device as part of a subsequent read transaction. Using inputs # 1 and #2, the transaction history and data availability logic 212 can determine a read retry has been issued, and can further predict if the associated device will re-issue the read transaction if subsequently granted the bus; [0002], Predicting the type of bus transaction a requestor will issue if granted the bus allows the arbiter to prioritize the requesters in a manner that maximizes bus utilization; [0010], it is probable that an initiator will issue multiple reads, each retried, until the addressed data is finally available in the PCI bridge)
and
grant, to a selected one of the plurality of accessors, access to the shared resource on a future processor cycle, the selected one of the plurality of accessors is to be selected based, at least in part, on the predicted future request state of the at least one of the accessors, (Moore, [0007], the arbiter does not grant access to devices that will predictably issue transactions that do not result in the transfer of data; [0012], An arbiter that includes the knowledge of mandatory retrying of reads along with the availability of data for each requestor by associating the requestor with the data would be able to selectively deny grants to requestors which will predictably be retried; [0024], When device 114's data becomes available inside PCI bridge 110, the /REQ1 signal is unmasked (case # 2 in the truth table in FIG. 3). The other devices' requests, /REQ2, /REQ3, and /REQ4, remain masked in request masking 210 within the request preprocessor 216. As a result, device 114 is granted the bus and completes its read transaction; [0018], The request preprocessor 216, then, augments the arbitration process by masking requesters that it has predicted will issue read transactions that will be retried; [0002], Predicting the type of bus transaction a requestor will issue if granted the bus allows the arbiter to prioritize the requesters in a manner that maximizes bus utilization)
Regarding claim 18, claim 18 is directed to a method. Claim 18 is similar in scope to claim 1 and is therefore, rejected under similar rationale.
Regarding claim 20, claim 20 is directed to a non-transitory computer readable medium. Claim 20 is similar in scope to claim 1 and is therefore, rejected under similar rationale.
Claims 2-3 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Moore et al (“Moore,” US 20070271405) and further in view of Singleton et al (“Singleton,” US 20160210381).
Regarding claim 2, Moore discloses the access controller according to claim 1.
Moore fails to explicitly disclose wherein analyzing the activity of an accessor comprises testing for an access request on a past and/or current processor cycle.
However, in an analogous art, Singleton discloses wherein analyzing the activity of an accessor comprises testing for an access request on a past and/or current processor cycle (Singleton describes [0157] wherein analyzing the activity of an accessor comprises testing [0040] for an access request [0007], [0049], [0037] on a past and/or current processor cycle [0094]-[0095])
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Singleton with Moore to include wherein analyzing the activity of an accessor comprises testing for an access request on a past and/or current processor cycle. One would have been motivated to provide methods and systems for verifying operation of an arbiter in a hardware design (Singleton, [0006]).
Regarding claim 3, Moore discloses the access controller according to claim 1.
Moore fails to explicitly disclose wherein analyzing the activity of an accessor comprises testing for a used grant of access on a past and/or current processor cycle.
However, in an analogous art, Singleton discloses wherein analyzing the activity of an accessor comprises testing for a used grant of access on a past and/or current processor cycle, (Singleton describes [0157], wherein analyzing the activity of an accessor comprises testing [0040] for a used grant of access [0042], [0049], [0037] on a past and/or current processor cycle [0094]-[0095])
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Singleton with Moore to include wherein analyzing the activity of an accessor comprises testing for a used grant of access on a past and/or current processor cycle. One would have been motivated to provide methods and systems for verifying operation of an arbiter in a hardware design (Singleton, [0006]).
Regarding claim 19, Moore discloses the method according to claim 18.
Moore fail to explicitly disclose wherein the analysis of the activity of an accessor comprises testing for an access request on a past and/or current processor cycle and testing for a used grant of access on a past and/or current processor cycle.
However, in an analogous art, Singleton discloses wherein the analysis of the activity of an accessor comprises testing for an access request on a past and/or current processor cycle and testing for a used grant of access on a past and/or current processor cycle (Singleton describes [0157] wherein analysis of the activity of an accessor comprises testing [0040] for an access request [0007], [0049], [0037] on a past and/or current processor cycle [0094]-[0095])
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Singleton with Moore to include wherein the analysis of the activity of an accessor comprises testing for an access request on a past and/or current processor cycle and testing for a used grant of access on a past and/or current processor cycle. One would have been motivated to provide methods and systems for verifying operation of an arbiter in a hardware design (Singleton, [0006]).
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Moore et al (“Moore,” US 20070271405) and further in view of Fertig et al (“Fertig,” US 20090024835).
Regarding claim 4, Moore discloses the access controller according to claim 1.
Moore fails to explicitly disclose wherein the predictor comprises an active state predictor configured to indicate a positive event when an accessor does not request access on a first processor cycle and does request access on a second processor cycle subsequent to the first processor cycle.
However, in an analogous art, Fertig discloses wherein the predictor comprises an active state predictor configured to indicate a positive event when an accessor does not request access on a first processor cycle and does request access on a second processor cycle subsequent to the first processor cycle, (Fertig describes [0009] wherein the predictor comprises an active state predictor [0011] configured to indicate a positive event [0045] when an accessor does not request access [0009], [0034]-[0035] on a first processor cycle [0035] and does request access [0009], [0034]-[0035] on a second processor cycle [0035] subsequent to the first processor cycle [0035])
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Fertig with Moore to include wherein the predictor comprises an active state predictor configured to indicate a positive event when an accessor does not request access on a first processor cycle and does request access on a second processor cycle subsequent to the first processor cycle. One would have been motivated to achieve speculative pre-fetching of data from system memory (Fertig, [0002]).
Regarding claim 5, Moore discloses the access controller according to claim 1.
Moore fails to explicitly disclose wherein the predictor comprises a steady state predictor configured to indicate a positive event when an accessor does request access and is granted access on a first processor cycle and does request access on a second processor cycle subsequent to the first processor cycle, and to indicate a negative event when an accessor does request access and is granted access on a first processor cycle and does not request access on a second processor cycle subsequent to the first processor cycle.
However, in an analogous art, Fertig discloses wherein the predictor comprises a steady state predictor configured to indicate a positive event when an accessor does request access and is granted access on a first processor cycle and does request access on a second processor cycle subsequent to the first processor cycle, and to indicate a negative event when an accessor does request access and is granted access on a first processor cycle and does not request access on a second processor cycle subsequent to the first processor cycle, (Fertig describes [0009] wherein the predictor comprises a steady state predictor [0011] configured to indicate a positive event [0045] when an accessor does request access and is granted access on a first processor cycle and does request access [0009], [0034]-[0035] on a second processor cycle [0035] subsequent to the first processor cycle [0035], and to indicate a negative event [0009], [0034]-[0035] when an accessor does request access [0009], [0034]-[0035] and is granted access [0009], [0034]-[0035] on a first processor cycle [0035] and does not request access [0009], [0034]-[0035] on a second processor cycle [0035]) subsequent to the first processor cycle [0035])
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Fertig with Moore to include wherein the predictor comprises a steady state predictor configured to indicate a positive event when an accessor does request access and is granted access on a first processor cycle and does request access on a second processor cycle subsequent to the first processor cycle, and to indicate a negative event when an accessor does request access and is granted access on a first processor cycle and does not request access on a second processor cycle subsequent to the first processor cycle. One would have been motivated to achieve speculative pre-fetching of data from system memory (Fertig, [0002]).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Moore et al (“Moore,” US 20070271405) in view of Fertig et al (“Fertig,” US 20090024835) and further in view of Ansari et al (“Ansari,” US 20130036288).
Regarding claim 6, Moore and Fertig discloses the access controller according to claim 5.
Moore and Fertig fail to explicitly disclose wherein the first processor cycle and second processor cycle are consecutive.
However, in an analogous art, Ansari discloses wherein the first processor cycle and second processor cycle are consecutive, (Ansari describes [0089], [0111] wherein the first processor cycle and second processor cycle are consecutive)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ansari with Moore and Fertig to include wherein the first processor cycle and second processor cycle are consecutive. One would have been motivated to assign processing resources used to manage transport operations between a first memory cluster and one or more other memory clusters (Ansari, [0008]).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Moore et al (“Moore,” US 20070271405) and further in view of Kamemaru et al (“Kamemaru,” US 6,341,334).
Regarding claim 7, Moore discloses the access controller according to claim 1.
Moore fails to explicitly disclose wherein the predictor is configured to predict a future request state as high when it has determined there have been two consecutive positive events.
However, in an analogous art, Kamemaru discloses wherein the predictor is configured to predict a future request state as high when it has determined there have been two consecutive positive events, (Kamemaru describes wherein the predictor (Col. 2, Lines 4-12) is configured to predict a future request state (Col. 2, Lines 41-56) as high (Col. 14, Lines 41-53) when it has determined there have been two consecutive positive events (Col. 21, Lines 20-38))
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kamemaru with Moore to include wherein the predictor is configured to predict a future request state as high when it has determined there have been two consecutive positive events. One would have been motivated to provide a method to bridge a plurality of buses and a multiprocessor system utilizing the bridge method and bus bridge (Kamemaru, Col. 1, Lines 7-9).
Claims 8-10 and 14-17 are rejected under 35 U.S.C. 103 as being
unpatentable over Moore et al (“Moore,” US 20070271405) and further in view of Bao et al ("Bao," US 8,886,899).
Regarding claim 8, Moore discloses the access controller according to claim 1.
Moore fails to explicitly disclose wherein the access controller comprises at least one two-bit memory for at least one respective accessor, each two-bit memory for storing an event bit indicating a determined event for that accessor and a prediction bit indicating the predicted future request state of that accessor
However, in an analogous art, Bao discloses wherein the access controller comprises at least one two-bit memory for at least one respective accessor, each two-bit memory for storing an event bit indicating a determined event for that accessor and a prediction bit indicating the predicted future request state of that accessor, (Bao describes wherein the access controller (Col. 36, Line 19) comprises at least one two-bit memory (Col. 38, Lines 14-28) for at least one respective accessor, each two-bit memory (Col. 38, Lines 14-28) for storing an event bit indicating a determined event for that accessor (Col. 38, Lines 14-28) and a prediction bit (Col. 46, Lines 58-67; Col. 47, Lines 1-3) indicating the predicted future request state of that accessor (Col. 65, Lines 28-54)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Bao with Moore to include wherein the access controller comprises at least one two-bit memory for at least one respective accessor, each two-bit memory for storing an event bit indicating a determined event for that accessor and a prediction bit indicating the predicted future request state of that accessor. One would have been motivated to managing memory requests based on priority, and managing processes, data access, and communication in a parallel processing environment (Bao, Col. 1, Lines 14-16).
Regarding claim 9, Moore discloses the access controller according to claim 1.
Moore fails to explicitly disclose wherein the access controller comprises at least one two-register memory for at least one respective accessor, each two-register memory for storing an event register indicating a determined event for that accessor and a prediction register indicating a predicted future request state of at least one accessor
However, in an analogous art, Bao discloses wherein the access controller comprises at least one two-register memory for at least one respective accessor, the or each two-register memory for storing an event register indicating a determined event for that accessor and a prediction register indicating a predicted future request state of at least one accessor, (Bao describes wherein the access controller (Col. 1, Lines 43-53) comprises at least one two-register memory (Col. 3, Line 59) for at least one respective accessor, each two-register memory (Col. 3, Line 59) for storing an event register indicating a determined event for that accessor (Col. 38, Lines 14-28; Col. 4, Lines 19-32) and a prediction register (Col. 46, Lines 58-67; Col. 47, Lines 1-3; Col. 3, Line 59) indicating a predicted future request state of at least one accessor (Col. 65, Lines 28-54; Col. 46, Lines 47-67; Col. 47, Lines 1-3)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Bao with Moore to include wherein the access controller comprises at least one two-register memory for at least one respective accessor, each two-register memory for storing an event register indicating a determined event for that accessor and a prediction register indicating a predicted future request state of at least one accessor. One would have been motivated to managing memory requests based on priority, and managing processes, data access, and communication in a parallel processing environment (Bao, Col. 1, Lines 14-16).
Regarding claim 10, Moore discloses the access controller according to claim 9.
Moore fails to explicitly disclose wherein the indicating a predicted future request state of at least one of the accessors comprises determining an event, comparing the determined event to the event register, and when the determined event is the same as a previously determined event represented by the event register, setting the prediction register to a value of the event register
However, in an analogous art, Bao discloses wherein the indicating a predicted future request state of at least one of the accessors comprises determining an event, comparing the determined event to the event register, and when the determined event is the same as a previously determined event represented by the event register, setting the prediction register to a value of the event register, (Bao describes wherein the indicating a predicted future request state of at least one of the accessors (Col. 65, Lines 28-54; Col. 46, Lines 47-67; Col. 47, Lines 1-3) comprises determining an event, comparing the determined event to the event register, (Col 38, Lines 9-28) and when the determined event is the same as a previously determined event represented by the event register, (Col. 38, Lines 9-28) setting the prediction register to a value of the event register (Col. 38, Lines 9-28; Col. 65, Lines 28-54; Col. 46, Lines 47-67; Col. 47, Lines 1-3 )
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Bao with Moore to include wherein the indicating a predicted future request state of at least one of the accessors comprises determining an event, comparing the determined event to the event register, and when the determined event is the same as a previously determined event represented by the event register, setting the prediction register to a value of the event register. One would have been motivated to managing memory requests based on priority, and managing processes, data access, and communication in a parallel processing environment (Bao, Col. 1, Lines 14-16).
Regarding claim 14, Moore discloses the access controller according to claim 1.
Moore fails to explicitly disclose wherein the access controller is to determine whether an accessor is a sole accessor requesting access and, when the sole accessor is predicted not to request on the next processor cycle, to grant access to another accessor in a round-robin order or when that accessor is predicted not to request on the next processor cycle, to grant access to another accessor in a least-recently granted order,
However, in an analogous art, Bao discloses wherein the access controller is to determine whether an accessor is a sole accessor requesting access and, when the sole accessor is predicted not to request on the next processor cycle, to grant access to another accessor in a round-robin order or when that accessor is predicted not to request on the next processor cycle, to grant access to another accessor in a least-recently granted order (Bao describes wherein the access controller (Col. 1, Lines 43-53) is to determine whether an accessor is a sole accessor requesting access (Col. 42, Lines 5-7; Col. 11, Lines 25-26) and, when the sole accessor is predicted not to request on the next processor cycle (Col. 29, Line 27), to grant access to another accessor (Col. 11, Line 25) in a round-robin order (Col. 15, Lines 53-62) or when that accessor is predicted not to request on the next processor cycle (Col. 29, Line 27; Col. 46, Lines 37-67; Col. 47, Line 1-3), to grant access to another accessor (Col. 11, Line 25) in a least-recently granted order (Col. 39, Lines 25-61))
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Bao with Moore to include wherein the access controller is to determine whether an accessor is a sole accessor requesting access and, when the sole accessor is predicted not to request on the next processor cycle, to grant access to another accessor in a round-robin order or when that accessor is predicted not to request on the next processor cycle, to grant access to another accessor in a least-recently granted order. One would have been motivated to managing memory requests based on priority, and managing processes, data access, and communication in a parallel processing environment (Bao, Col. 1, Lines 14-16).
Regarding claim 15, Moore discloses the access controller according to claim 1.
Moore fails to explicitly disclose wherein the shared resource comprises a memory and wherein at least one request issued by an accessor comprises a request for read or write access to the memory
Bao further discloses wherein the resource comprises a memory and wherein at least one request issued by an accessor comprises a request for read or write access to the memory, (Bao describes (Col. 15, Line 63) wherein the shared resource comprises a memory (Col. 20, Line 48) and wherein at least one request issued by an accessor (Col. 19, Lines 20-23) comprises a request for read (Col. 5, Lines 57-59) or write access to the memory (Col. 20, Line 48; Col. 5, Lines 57-59))
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Bao with Moore to include wherein the shared resource comprises a memory and wherein at least one request issued by an accessor comprises a request for read or write access to the memory. One would have been motivated to managing memory requests based on priority, and managing processes, data access, and communication in a parallel processing environment (Bao, Col. 1, Lines 14-16).
Regarding claim 16, Moore discloses an electronic crossbar structure for mediating between a plurality of accessors and a plurality of shared resources and comprising a plurality of access controllers according to claim 1.
Moore fails to explicitly disclose an electronic crossbar structure for mediating between a plurality of accessors and a plurality of shared resources and comprising a plurality of access controllers according to claim 1
However, in an analogous art, Bao discloses an electronic crossbar structure for mediating between a plurality of accessors and a plurality of shared resources and comprising a plurality of access controllers according to claim 1, (Bao describes an electronic crossbar structure (Col. 4, Lines 39-42) for mediating between a plurality of accessors (Col. 16, Lines 8-12) and a plurality of shared resources (Col. 15, Lines 63-67; Col. 16, Lines 1-7) and comprising a plurality of access controllers (Col. 35, Line 37) according to claim 1)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Bao with Moore to include an electronic crossbar structure for mediating between a plurality of accessors and a plurality of shared resources and comprising a plurality of access controllers according to claim 1. One would have been motivated to managing memory requests based on priority, and managing processes, data access, and communication in a parallel processing environment (Bao, Col. 1, Lines 14-16).
Regarding claim 17, Moore discloses a processor accelerator comprising the electronic crossbar structure according to claim 16.
Moore fails to explicitly disclose wherein the accessors comprise computational units of a processor and the plurality of shared resources comprise memory buffer resources shared by the computational units
However, in an analogous art, Bao discloses wherein the accessors comprise computational units of a processor and the plurality of shared resources comprise memory buffer resources shared by the computational units, (Bao describes wherein the accessors (Col. 53, Line 41) comprise computational units of a processor (Col. 66, Lines 10-24) and the plurality of shared resources (Col. 15, Lines 63-67; Col. 16, Lines 1-7) comprise memory buffer resources (Col. 35, Lines 63-67; Col. 36, Lines 1-4) shared by the computational units (Col. 66, Lines 10-24))
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Bao with Moore to include wherein the accessors comprise computational units of a processor and the plurality of shared resources comprise memory buffer resources shared by the computational units. One would have been motivated to managing memory requests based on priority, and managing processes, data access, and communication in a parallel processing environment (Bao, Col. 1, Lines 14-16).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Moore et al (“Moore,” US 20070271405) and further in view of Rungta et al (“Rungta,” US 20180074865).
Regarding claim 11, Moore discloses the access controller according to claim 9.
Moore fails to explicitly disclose wherein the predictor comprises a transition predictor operable to: analyse a history of used grants of access to detect past instances of transitions from a first accessor to a second accessor; identify a determined event representing a used grant of access to the first accessor; and set the prediction register to a value representing the second accessor.
However, in an analogous art, Rungta discloses wherein the predictor comprises a transition predictor operable to: analyse a history of used grants of access to detect past instances of transitions from a first accessor to a second accessor; identify a determined event representing a used grant of access to the first accessor; and set the prediction register to a value representing the second accessor, (Rungta describes wherein the predictor [0025], [0030] comprises a transition predictor operable to: [0029], [0035] analyse a history of used grants of access [0035] to detect past instances of transitions [0029], [0035] from a first accessor to a second accessor; [0074])
identify a determined event representing a used grant of access to the first accessor; (Rungta, [0025], [0035], [0074])
and set the prediction register [0018], [0025] to a value representing the second accessor [0074])
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Rungta with Moore to include wherein the predictor comprises a transition predictor operable to: analyse a history of used grants of access to detect past instances of transitions from a first accessor to a second accessor; identify a determined event representing a used grant of access to the first accessor; and set the prediction register to a value representing the second accessor. One would have been motivated to lockless execution during read-mostly workload periods (Rungta, [0001]).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Moore et al (“Moore,” US 20070271405) in view of Rungta et al (“Rungta,” US 20180074865) and further in view of Singleton et al (“Singleton,” US 20160210381).
Regarding claim 12, Moore disclose the access controller according to claim 1.
Moore fails to explicitly disclose wherein the predictor comprises a sequence predictor configured to analyze a history of used grants of access to detect past instances of repetitive patterns of accessors using granted access over a sequence of processor cycles and to increase a selection priority of an accessor in the plurality of accessors in response to a determination that it is predicted to be a next requester in a current instance of a repetitive pattern.
However, in an analogous art, Rungta discloses wherein the predictor comprises a sequence predictor configured to analyze a history of used grants of access to detect past instances of repetitive patterns of accessors using granted access over a sequence of processor cycles and to increase a selection priority of an accessor in the plurality of accessors in response to a determination that it is predicted to be a next requester in a current instance of a repetitive pattern, (Rungta describes wherein the predictor comprises a sequence predictor configured [0077], to analyze a history of used grants of access [0035] to detect past instances of repetitive patterns of accessors [0025], [0029] using granted access over a sequence of processor cycles [0027])
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Rungta with Moore to include wherein the predictor comprises a sequence predictor configured to analyze a history of used grants of access to detect past instances of repetitive patterns of accessors using granted access over a sequence of processor cycles and to increase a selection priority of an accessor in the plurality of accessors in response to a determination that it is predicted to be a next requester in a current instance of a repetitive pattern. One would have been motivated to lockless execution during read-mostly workload periods (Rungta, [0001]).
Moore and Rungta fail to explicitly disclose and to increase a selection priority of an accessor in the plurality of accessors in response to a determination that it is predicted to be a next requester in a current instance of a repetitive pattern.
However, in an analogous art, Singleton discloses and to increase a selection priority of an accessor in the plurality of accessors in response to a determination that it is predicted to be a next requester in a current instance of a repetitive pattern, (Singleton describes and to increase a selection priority [0033]-[0035] of an accessor in the plurality of accessors [0037] in response to a determination that it is predicted [0083] to be a next requester [0030] in a current instance of a repetitive pattern [0030])
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Singleton with Moore and Rungta to include and to increase a selection priority of an accessor in the plurality of accessors in response to a determination that it is predicted to be a next requester in a current instance of a repetitive pattern. One would have been motivated to provide methods and systems for verifying operation of an arbiter in a hardware design (Singleton, [0006]).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Moore et al (“Moore,” US 20070271405) and further in view of Bogin et al (“Bogin,” US 6,215,703).
Regarding claim 13, Moore discloses the access controller according to claim 1.
Moore fails to explicitly disclose wherein the access controller is to grant access to the accessor granted access on a most recent previous processor cycle when no other accessor is requesting access.
However, in an analogous art, Bogin discloses wherein the access controller is to grant access to the accessor granted access on a most recent previous processor cycle when no other accessor is requesting access, (Bogin describes (Col. 1, Lines 50-64) wherein the access controller (Col. 3, Lines 4-16) is to grant access to the accessor granted access (Col. 1, Lines 52-53) on a most recent previous processor cycle (Col. 3, Lines 42-53) when no other accessor is requesting access (Col. 4, Lines 10-58; FIG 4))
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Bogin with Moore to include wherein the access controller is to grant access to the accessor granted access on a most recent previous processor cycle when no other accessor is requesting access. One would have been motivated to provide arbitration between multiple agents in order to gain control of a memory system (Bogin, Col. 1, Lines 5-8).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES J WILCOX whose telephone number is (571)270-3774. The examiner can normally be reached M-F: 8 A.M. to 5 P.M..
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/JAMES J WILCOX/Examiner, Art Unit 2439
/RODERICK TOLENTINO/Primary Examiner, Art Unit 2439
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