DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in the application. Claims 14-20 are withdrawn from further consideration.
Election/Restrictions
Applicant’s election without traverse of Group I: claims 1-13 in the reply filed on 30 June 2026 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement(s) (IDS), Form PTO-1449, filed 19 January 2024. The information therein was considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3 and 5-7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang et al. (US 2017/0005067) (hereinafter, “Yang”).
Re: independent claim 1, Yang discloses in fig. 20 a semiconductor package comprising: a first redistribution structure (within 140a); a semiconductor chip (131a) on the first redistribution structure (within 140a); a pad insulation layer (148) on a lower surface of the first redistribution structure (140a); a conductive pad (142, 120b) extending into a lower surface of the pad insulation layer (148) and electrically connected to the first redistribution structure (within 140a); and a plurality of alignment patterns (120a, 124 [0044]) on an edge of the pad insulation layer (148), each of the plurality of alignment patterns (120a, 124) including a first portion (120a) extending into the lower surface of the pad insulation layer (148) and a second portion (124) extending away from the lower surface of the pad insulation layer (148).
Re: claim 2, Yang discloses in fig. 20 the semiconductor package of claim 1, wherein a width of the first portion (120a) is greater than that of the second portion (124).
Re: claim 3, Yang discloses in fig. 20 the semiconductor package of claim 2, wherein the width of the first portion (120a) is greater than that of the conductive pad (142).
Re: claim 5, Yang discloses in fig. 20 the semiconductor package of claim 1, wherein the second portion (124) extends below a lower surface of the conductive pad (142).
Re: claim 6, Yang discloses in fig. 20 the semiconductor package of claim 5, wherein a lower surface of the first portion (120a) is at a same level as the lower surface of the conductive pad (120b).
Re: claim 7, Yang discloses in fig. 20 the semiconductor package of claim 1, wherein the plurality of alignment patterns (120a, 124) include a same material as the conductive pad (120b) [0035].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 2017/0005067) (hereinafter, “Yang”).
Re: claims 4 and 8, Yang discloses in fig. 20 the semiconductor package of claims 1-2.
Yang does not explicitly disclose wherein a ratio of the width of the first portion to the width of the second portion is 1:4 to 1:1; and as recited in claim 8, wherein a thickness of the second portion is within 10 μm.
However, these limitations would have been obvious to one of ordinary skill in the art at the time of the invention since it has been held that claimed ranges of a result effective variable are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art. In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996). These claims are prima facie obvious without showing that the claimed ranges achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Boesch, 205 USPQ 215 (CCPA 1980) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious). See MPEP § 2144.05.
Allowable Subject Matter
Claims 12-13 are allowed.
Claims 9-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record fails to teach the claimed limitations in combination namely, as recited in independent claim 12, a semiconductor package comprising: a first redistribution structure including an active area and a dummy area around the active area; a semiconductor chip on the first redistribution structure in the active area; a second redistribution structure on the semiconductor chip; a conductive post connecting an upper surface of the first redistribution structure and a lower surface of the second redistribution structure in the active area; a pad insulation layer on a lower surface of the first redistribution structure; a conductive pad extending into the lower surface of the pad insulation layer and electrically connected to the first redistribution structure, in the active area; a solder extending away from a lower surface of the conductive pad; and a plurality of alignment patterns, each of the plurality of alignment patterns including a first portion extending into the lower surface of the pad insulation layer and a second portion extending away from the lower surface of the pad insulation layer, in the dummy area, wherein a width of the first portion is greater than that of the second portion; and as recited in claim 9, the semiconductor package of claim 1, wherein the conductive pad further includes: a protruding portion extending away from the lower surface of the pad insulation layer, and a lower surface of the protruding portion is at a same level as a lower surface of the second portion; and as recited in claim 10, the semiconductor package of claim 1, further comprising a second redistribution structure on the semiconductor chip; and a conductive post that physically and electrically connects the first redistribution structure and the second redistribution structure, wherein the plurality of alignment patterns are outside the conductive post.
Conclusion
The examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. When responding to this office action, applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALLISON BERNSTEIN whose telephone number is (571)272-9011. The examiner can normally be reached M-F 8AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached on 571-272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALLISON BERNSTEIN/Primary Examiner, Art Unit 2824 7/20/2026
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