Office Action Predictor
Last updated: April 16, 2026
Application No. 18/417,590

MULTILAYER ELECTRONIC COMPONENT

Final Rejection §102§103
Filed
Jan 19, 2024
Examiner
RAMASWAMY, ARUN
Art Unit
2848
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electro-Mechanics Co., LTD.
OA Round
2 (Final)
84%
Grant Probability
Favorable
3-4
OA Rounds
2y 7m
To Grant
98%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allow Rate
660 granted / 784 resolved
+16.2% vs TC avg
Moderate +14% lift
Without
With
+14.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
37 currently pending
Career history
821
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
54.8%
+14.8% vs TC avg
§102
30.6%
-9.4% vs TC avg
§112
9.0%
-31.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 784 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant's arguments filed September 16, 2025, have been fully considered but they are not persuasive. On pages 5-7 of Remarks, Applicant argues that the prior art of Kim et al. (US Publication 2016/0233024) fails to disclose lines L1 and L2, and therefore, does not disclose an angle T formed between these two lines, and, rather, the “bending angle” of Kim is defined relative to the surface of the component body. The Applicant further argues that Kim does not recognize the design consideration of the Instant Application, and, therefore, the claimed feature is not inherently disclosed by Kim. The Examiner respectfully disagrees with the above assertion. The Examiner would like to point out that the prior art rejection is not based upon inherency. Although Kim discloses the angle of the internal electrode (21, 22 – Figure 5) makes with the end surface (SL1, SL2 – Figure 5), an angle between a virtual line L1 and L2 can be calculated. Reproduced below is Figure 5 of Kim with Examiner’s Comments. PNG media_image1.png 430 535 media_image1.png Greyscale Figure 5 of Kim with Examiner’s Comments (Figure 5EC) When a bending angle between the internal electrode and the end surface is 80°, for example, an angle between L2 and L3 is 80°. An angle between L3 and L1 is 90°, and thus, an angle between L1 and L2 is 10°, producing a tangential value of 0.18. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-3, 6, and 10-11 is/are rejected under 35 U.S.C. 102(a)(1) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Kim et al. (US Publication 2016/0233024). In re claim 1, Kim discloses a multilayer electronic component comprising: a body (50 – Figure 1, ¶27) including a dielectric layer (10 – Figure 5, ¶25) and first and second internal electrodes (21, 22 – Figure 5, ¶28) alternately disposed in a first direction (‘T’ direction – Figure 5) with the dielectric layer interposed therebetween (Figure 5), and including a first surface (ST – Figure 1, ¶27) and a second surface (SB – Figure 1, ¶27) opposing each other in the first direction (Figure 1), a third surface (SL1 – Figure 5, ¶27) and a fourth surface (SL2 – Figure 5, ¶27) connected to the first surface and the second surface and opposing each other in a second direction (‘L’ direction – Figure 1, Figure 5), and a fifth surface and a sixth surface (SW1, SW2 – Figure 5, ¶27) connected to the first surface to the fourth surface and opposing each other in a third direction (‘W’ direction – Figure 5); a first external electrode (31 – Figure 1, ¶35) disposed on the third surface and connected to the first internal electrode (21 – Figure 5); and a second external electrode (32 – Figure 1, ¶35) disposed on the fourth surface and connected to the second internal electrode (22 – Figure 5), wherein the first internal electrode (21 – Figure 5) is connected to the third surface (SL1 – Figure 5) and is spaced apart from the fourth surface (SL2 – Figure 5), and the second internal electrode (22 – Figure 5) is connected to the fourth surface (SL2 – Figure 5) and is spaced apart from the third surface (SL1 – Figure 5), the first internal electrode includes a first bent portion bent in a region adjacent to the third surface, and the second internal electrode includes a second bent portion bent in a region adjacent to the fourth surface, and when a straight line in parallel with the second direction and in contact with the first or second internal electrode (21, 22 – Figure 5) is referred to as L1, a straight line connecting a point, at which the first internal electrode (21 – Figure 5) is in contact with the third surface (SL1 – Figure 5), and the first bent portion or a straight line connecting a point, at which the second internal electrode (22 – Figure 5) is in contact with the fourth surface (SL2 – Figure 5), and the second bent portion is referred to as L2, an acute angle formed by L1 and L2 is referred to as T, and an average value of the T is referred to as ϴ, tan (ϴ) satisfies 0.1 or more and 0.5 or less (¶9,¶66; Note that a bending angle of 75° to 95° creates an acute angle (ϴ) between L1 and L2 to fall between 5° and 15°. The tan (ϴ) falls within the range of 0.09 to 0.27) . In re claim 2, Kim discloses the multilayer electronic component according to claim 1, as explained above. Kim further discloses wherein the first and second bent portions (bent portions of 21 and 22 – Figure 5) are bent in the first direction (T direction – Figure 5) (Figure 5). In re claim 3, Kim discloses the multilayer electronic component according to claim 1, as explained above. Kim does not disclose wherein a number of layers of the first and second internal electrodes stacked in the body is 800 or more. However, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to use the well-known fact of increasing the number of first and second internal electrode layers to increase the capacitance of the device, since it has been held that mere duplication of the essential working part of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. In re claim 6, Kim discloses the multilayer electronic component according to claim 1, as explained above. Kim further discloses wherein the first and second bent portions (bent portions of 21, 22 – Figure 5) each extend in the third direction (21, 22 – Figure 6; Note that the internal electrodes extend in the width direction, and therefore, the bent portions extend in the width direction.). In re claim 10, Kim discloses the multilayer electronic component according to claim 1, as explained above. Kim does not disclose wherein when an average thickness of the first and second internal electrodes is referred to as te and an average thickness of the dielectric layer is referred to as td, td > 2 × te is satisfied. However, it is well-known in the art that the thickness of the dielectric layer is correlated to the capacitance of the device, and the thickness of the internal electrodes are correlated with the ESR characteristics of the device. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to adjust the thickness of the dielectric layers and internal electrode layers to achieve a device having desired balance between capacitance, ESR characteristics, and miniaturization characteristics per user specifications , since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). In re claim 11, Kim discloses the multilayer electronic component according to claim 1, as explained above. Kim further discloses wherein in the body (50 – Figure 5), when a space from an end of the first internal electrode (21 – Figure 5, Figure 6) in the second direction (‘L’ direction – Figure 5) to the fourth surface (SL2 – Figure 5) and a space from an end of the second internal electrode (22 – Figure 5) in the second direction to the third surface (SL1 – Figure 5) are a first margin portion, the average width of the first margin portion (D – Figure 3, ¶6) in the second direction is 70 μm or more and 170 μm or less (Table 1: Example 9). Claim(s) 4-5 and 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Publication 2016/0233024) in view of Tanaka (US Publication 2021/0166874). In re claim 4, Kim discloses the multilayer electronic component according to claim 1, as explained above. Kim does not disclose wherein the first internal electrode includes two or more first bent portions, including the first bent portion, disposed between an end of the second internal electrode and the third surface in the second direction, and the second internal electrode includes two or more second bent portions, including the second bent portion, disposed between an end of the first internal electrode and the fourth surface in the second direction. Tanaka discloses wherein the first internal electrode (14 – Figure 4, Figure 6, ¶23) includes two or more first bent portions (132a, 132b - Figure 4, Figure 6, ¶35), including the first bent portion, disposed between an end of the second internal electrode (14 – Figure 4, Figure 6, ¶33) and the third surface (15a - Figure 6, ¶21) in the second direction (‘L’ direction – Figure 6), and the second internal electrode (14 – Figure 6, ¶23) includes two or more second bent portions (Figure 4, Figure 6), including the second bent portion (Figure 4, Figure 6), disposed between an end of the first internal electrode (13 – Figure 6) and the fourth surface in the second direction (15b – Figure 6, ¶21). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate multiple bent portions to improve the adhesion between the internal electrode and dielectric layers. In re claim 5, Kim in view of Tanaka discloses the multilayer electronic component according to claim 4, as explained above. Kim further discloses wherein the L2 is a straight line connecting a point, at which the first internal electrode (21 – Figure 5) is in contact with the third surface (SL1 – Figure 5), and a first bent portion (Figure 5) which is closest to the third surface (SL1 – Figure 5), or a straight line connecting a point, at which the second internal electrode (22 – Figure 5) is in contact with the fourth surface (SL2 – Figure 5), and a second bent portion (Figure 5) which is closest to the fourth surface (SL2 – Figure 5). Kim does not disclose two or more first bent portions and the two or more second bent portions. Tanaka discloses two or more first bent portions (bent portions of 13 – Figure 6, Figure 4) and the two or more second bent portions (bent portions of 14 – Figure 6, Figure 4). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate multiple bent portions to improve the adhesion between the internal electrode and dielectric layers. In re claim 7, Kim in view of Tanaka discloses the multilayer electronic component according to claim 4, as explained above. Kim further discloses wherein a point at which the first internal electrode (21 – Figure 5) is in contact with the third surface (SL1 – Figure 5) and a point at which the second internal electrode (22 – Figure 5) is in contact with the fourth surface (SL2 – Figure 5) are spaced apart from the L1 (Figure 5; The bent portions of Kim occur at the end surfaces.). In re claim 8, Kim in view of Tanaka discloses the multilayer electronic component according to claim 4, as explained above. Kim does not disclose wherein the two or more first and second bent portions are disposed on one side in the first direction based on the L1. Tanaka discloses wherein the two or more first and second bent portions (bent portion of 13, 14 connected to end surfaces 15a, 15b and 132a of 13, 14 – Figure 6, Figure 4) are disposed on one side in the first direction based on the L1 (Figure 6; Note that the Examiner is taking the first bent portion to be connected to the end surface and the second bent portion to be adjacent to the first bent portion.). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate multiple bent portions to improve the adhesion between the internal electrode and dielectric layers. Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Publication 2016/0233024) in view of Ahn et al. (US Publication 2012/0327556). In re claim 9, Kim discloses the multilayer electronic component according to claim 1, as explained above. Kim further discloses an average thickness of the dielectric layer (10 – Figure 5) is referred to as td, and td is less than 2.8 μm (¶31). Kim does not disclose when an average thickness of the first and second internal electrodes is referred to as te and te is less than 1 μm. Ahn discloses an average thickness of the first and second internal electrodes is referred to as te and te is less than 1 μm (¶49). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the internal electrode thickness of Ahn to provide for an electronic component having desired ESR characteristics. Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Publication 2016/0233024) in view of Lee (US Publication 2013/0250472). In re claim 9, Kim discloses the multilayer electronic component according to claim 1, as explained above. Kim further discloses wherein in the body (50 – Figure 5), a region in which the first and second internal electrodes (21, 22 – Figure 5) overlap each other in the first direction (‘T’ direction – Figure 5) is referred to as a capacitance formation portion (Figure 5), a cover portion (portion of 50 above and below topmost and bottommost 22 – Figure 5) is disposed on one surface and the other surface of the capacitance formation portion in the first direction (Figure 5). Kim does not disclose an average thickness of the cover portion is 70 μm or more and 180 μm or less. Lee discloses an average thickness of the cover portion (Tc – Figure 2, ¶11) is 70 μm or more and 180 μm or less (Table 2, Table 3). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the cover layer thickness of Lee to provide for an electronic component having desired mechanical strength and miniaturization characteristics per user specifications. Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Publication 2016/0233024) in view of Kim ‘014 et al. (US Publication 2014/0301014) In re claim 13, Kim discloses the multilayer electronic component according to claim 1, as explained above. Kim further discloses wherein in the body (50 – Figure 5), when a region in which the first and second internal electrodes (21, 22 – Figure 5, Figure 6) overlap each other in the first direction (‘T’ direction – Figure 5) is referred to as a capacitance formation portion (Figure 5), a second margin portion is disposed on one surface and the other surface of the capacitance formation portion in the third direction (portion of 10 above and below 21, 22 – Figure 6). Kim does not disclose an average width of the second margin portion in the third direction is 70 μm or more and 170 μm or less. Kim ‘014 discloses that adjusting the margin width is a balance between mechanical strength and capacitance of the device (¶79). It would have been obvious to person having ordinary skill in the art before the effective filing date of the invention to adjust the margin thickness, as taught by Kim ‘014, to achieve a device having desired mechanical strength and capacitance properties, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Barbee, Jr. et al. (US Patent 5,486,277) Figure 3 THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARUN RAMASWAMY whose telephone number is (571)270-1962. The examiner can normally be reached Monday - Friday, 9:00 am - 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at (571) 272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ARUN RAMASWAMY/ Primary Examiner, Art Unit 2848
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Prosecution Timeline

Jan 19, 2024
Application Filed
Jun 12, 2025
Non-Final Rejection — §102, §103
Sep 16, 2025
Response Filed
Dec 21, 2025
Final Rejection — §102, §103
Mar 30, 2026
Request for Continued Examination
Apr 08, 2026
Response after Non-Final Action

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
84%
Grant Probability
98%
With Interview (+14.2%)
2y 7m
Median Time to Grant
Moderate
PTA Risk
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