DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. Claims 1-21 are pending.
3. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/03/2026 has been entered.
Response to Arguments
4. Applicant’s arguments with respect to the amended independent claims have been considered but are moot in view of the new ground(s) of rejection in which the Examiner has cited newly presented prior art, Horwich et al. (US Pub. No. 2021/0374080 A1 hereinafter “Horwich”), as necessitated by the amended independent claims.
Claim Rejections - 35 USC § 103
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 1-4, 6-11, 13-18, 20 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Romem et al. (US Pub. No. 2017/0132172 hereinafter “Romem” – IDS Submission) in view of Horwich et al. (US Pub. No. 2021/0374080 A1 hereinafter “Horwich”).
Referring to claim 1, Romem discloses a method for data access (Romem – Par. [0021, 0025]), wherein the method comprises:
receiving, by a memory expansion card (Romem – Figs. 1A & 2 shows a network interface controller (NIC) 100A having a control logic 110.), a first data access request generated by a computing device based on an internal bus protocol, wherein the internal bus protocol comprises a bus protocol for accessing internal memory space of the computing device, and the first data access request comprises a virtual address in the internal memory space (Romem – Par. [0021] discloses access instructions are received by the control logic 110 for the virtual storage 230. An access instruction includes at least one virtual address and an action to be performed corresponding to that virtual address. An action may be, for example, ‘read’, ‘write’, ‘erase’, etc. The access instruction is delivered over the first communication protocol.);
performing, by the memory expansion card (Romem – Figs. 1A & 2 shows a network interface controller (NIC) 100A having a control logic 110.), protocol conversion on the first data access request to obtain a second data access request in a format of an external bus protocol, wherein the external bus protocol comprises a bus protocol for accessing external memory space of the computing device, and the second data access request comprises a physical address in the external memory space (Romem – Par. [0021] discloses the access instruction is delivered over the first communication protocol and converted by the control logic 110 to the mapped physical address. The NIC 100A sends the converted access instruction through a network over a second communication protocol to the storage device corresponding to the physical address.);
accessing, by the memory expansion card, the external memory space based on the second data access request (Romem – Par. [0021, 0025] disclose the second access instruction is sent by the NIC over a second communication protocol to at least a storage server of the plurality of storage servers corresponding to the at least one of the plurality of physical addresses for accessing the remote storage devices.).
Romem fails to explicitly disclose accessing, by the memory expansion card, the external memory space based on the second data access request to obtain an access result; and transmitting, by the memory expansion card, the access result to the computing device.
Horwich discloses accessing, by the memory expansion card, the external memory space based on the data access request to obtain an access result; and transmitting, by the memory expansion card, the access result to the computing device (Horwich – Figs. 1, 8A & Par. [0094] disclose a coherent memory expansion device comprising a coherent memory expansion controller (CMXC) 120 having a control logic 125. As shown in FIG. 8A, in response to a first submission 801 for demand read, control logic 125 is configured to transfer a payload 811 specified in submission 801 from the NVM 140 to the demand read cache 327B, and to return demand data 812 specified in the submission 801 in response to a request 810 for the demand data from the CPU 112. The request 810 can be, for example, in the form of a memory read command using the CXL.mem protocol.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Horwich’s teachings with Romem’s techniques for providing a high density, high bandwidth, and low cost memory expansion device includes non-volatile memory (NVM, e.g., NAND Flash) as tier 1 memory for low-cost virtual memory capacity expansion, optional device DRAM as tier 2 coherent memory for physical memory capacity and bandwidth expansion, and device cache as tier 3 coherent memory for low latency (Horwich – Par. [0005]).
Referring to claim 2, Romem and Horwich disclose the method according to claim 1, wherein the virtual address in the internal memory space is a first virtual address visible to the computing device, and the method further comprises: converting, by the memory expansion card, the first virtual address visible to the computing device into a second virtual address visible to the memory expansion card; and converting, by the memory expansion card, the second virtual address into the physical address in the external memory space based on a mapping relationship between a virtual address and a physical address in an index (Romem – See Fig. 4 & Par. [0024].).
Referring to claim 3, Romem and Horwich disclose the method according to claim 1, wherein: the external memory space comprises at least one of a local external memory space or a remote external memory space; and when the external memory space comprises the remote external memory space, the accessing, by the memory expansion card, the external memory space based on the second data access request comprises: accessing, by the memory expansion card, the remote external memory space through remote direct memory access (RDMA) based on the second data access request (Romem – Par. [0021, 0025] disclose the second access instruction is sent by the NIC over a second communication protocol to at least a storage server of the plurality of storage servers corresponding to the at least one of the plurality of physical addresses for accessing the remote storage devices. The second communication protocol may implement, in some embodiments, remote direct memory access (RDMA) protocols.).
Referring to claim 6, Romem and Horwich disclose the method according to claim 1, wherein the memory expansion card is integrated into the computing device or is inserted into the computing device in a hot swap manner (Romem – Figs. 1A, 2 & Par. [0018] discloses the NIC 100A integrated into the client device 200.).
Referring to claim 7, Romem and Horwich disclose the method according to claim 1, wherein the memory expansion card (Romem – Figs. 1A & 2 shows a network interface controller (NIC) 100A having a control logic 110.) comprises a redundant array of independent disks (Romem – Par. [0020] discloses the control logic 110 may include a high availability module and a data protection module. Such modules may be provided, for example, by implementing protocols for redundant array of independent disks (RAID).).
Referring to claim 8, Romem discloses a memory expansion card (Romem – Figs. 1A & 2 shows a network interface controller (NIC) 100A having a control logic 110.), comprising:
at least one processor (Romem – Fig. 1A shows a processor 120.);
one or more memories coupled to the at least one processor and storing programming instructions for execution by the at least one processor to perform operations comprising (Romem – Fig. 1A & Par. [0018] disclose primary memory 130 includes instructions that when executed by the processor 120 performs a method described in more detail herein.):
receiving a first data access request generated by a computing device based on an internal bus protocol, wherein the internal bus protocol comprises a bus protocol for accessing internal memory space of the computing device, and the first data access request comprises a virtual address in the internal memory space (Romem – Par. [0021] discloses access instructions are received by the control logic 110 for the virtual storage 230. An access instruction includes at least one virtual address and an action to be performed corresponding to that virtual address. An action may be, for example, ‘read’, ‘write’, ‘erase’, etc. The access instruction is delivered over the first communication protocol.);
performing protocol conversion on the first data access request to obtain a second data access request in a format of an external bus protocol, wherein the external bus protocol comprises a bus protocol for accessing external memory space of the computing device, and the second data access request comprises a physical address in the external memory space (Romem – Par. [0021] discloses the access instruction is delivered over the first communication protocol and converted by the control logic 110 to the mapped physical address. The NIC 100A sends the converted access instruction through a network over a second communication protocol to the storage device corresponding to the physical address.);
accessing the external memory space based on the second data access request (Romem – Par. [0021, 0025] disclose the second access instruction is sent by the NIC over a second communication protocol to at least a storage server of the plurality of storage servers corresponding to the at least one of the plurality of physical addresses for accessing the remote storage devices.).
Romem fails to explicitly disclose accessing the external memory space based on the second data access request to obtain an access result; and transmitting the access result to the computing device.
Horwich discloses accessing the external memory space based on the data access request to obtain an access result; and transmitting the access result to the computing device (Horwich – Figs. 1, 8A & Par. [0094] disclose a coherent memory expansion device comprising a coherent memory expansion controller (CMXC) 120 having a control logic 125. As shown in FIG. 8A, in response to a first submission 801 for demand read, control logic 125 is configured to transfer a payload 811 specified in submission 801 from the NVM 140 to the demand read cache 327B, and to return demand data 812 specified in the submission 801 in response to a request 810 for the demand data from the CPU 112. The request 810 can be, for example, in the form of a memory read command using the CXL.mem protocol.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Horwich’s teachings with Romem’s techniques for providing a high density, high bandwidth, and low cost memory expansion device includes non-volatile memory (NVM, e.g., NAND Flash) as tier 1 memory for low-cost virtual memory capacity expansion, optional device DRAM as tier 2 coherent memory for physical memory capacity and bandwidth expansion, and device cache as tier 3 coherent memory for low latency (Horwich – Par. [0005]).
Referring to claims 9 and 16, note the rejections of claim 2 above. The Instant Claims recite substantially same limitations as the above-rejected and is therefore rejected under same prior-art teachings.
Referring to claims 10 and 17, note the rejections of claim 3 above. The Instant Claims recite substantially same limitations as the above-rejected and is therefore rejected under same prior-art teachings.
Referring to claims 13 and 20, note the rejections of claim 6 above. The Instant Claims recite substantially same limitations as the above-rejected and is therefore rejected under same prior-art teachings.
Referring to claims 14 and 21, note the rejections of claim 7 above. The Instant Claims recite substantially same limitations as the above-rejected and is therefore rejected under same prior-art teachings.
Referring to claim 15, note the rejections of claims 1 and 8 above. The Instant Claim recites substantially same limitations as the above-rejected and is therefore rejected under same prior-art teachings.
7. Claims 4, 11 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Romem in view of Horwich, and further in view of Ranjan et al. (US Pub. No. 2012/0102251 A1 hereinafter “Ranjan”).
Referring to claim 4, Romem and Horwich disclose the method according to claim 1, wherein the internal bus protocol comprises any one of a peripheral component interconnect (PCI) protocol, a peripheral component interconnect express (PCI-E) protocol, a quick path interconnect (QPI) protocol, or a universal bus (UB) protocol (Romem – Par. [0021] discloses a bus 210 supports a first communication protocol as a Peripheral Component Interconnect Express (PCI Express).), however, fails to explicitly disclose the external bus protocol comprises any one of a small computer system interface (SCSI) or a serial attached small computer system interface (SAS).
Ranjan discloses the external bus protocol comprises any one of a small computer system interface (SCSI) or a serial attached small computer system interface (SAS) (Ranjan – Fig. 1 & Par. [0004] discloses the expander device includes a switching module of the firmware that is configured to convert through a processor of the expander device the USB command to the SAS command and/or the SAS command to the USB command.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Ranjan’s teachings with Romem and Horwich’s techniques for bridging through a firmware of the expander device between a USB command of the data processing device and a SAS command of the SAS domain to communicate between the data processing device and the SAS domain (Ranjan – Par. [0003]).
Referring to claims 11 and 18, note the rejections of claim 4 above. The Instant Claims recite substantially same limitations as the above-rejected and is therefore rejected under same prior-art teachings.
8. Claims 5, 12 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Romem in view of Horwich, and further in view of Branover et al. (US Pub. No. 2018/0115495 A1 hereinafter “Branover”).
Referring to claim 5, Romem and Horwich disclose the method according to claim 1, however, fails to explicitly disclose wherein the computing device maintains at least one request queue, and when the at least one request queue comprises processes or threads corresponding to a plurality of data access requests, the computing device performs the processes or threads corresponding to the plurality of data access requests in a synchronous manner, wherein the plurality of data access requests comprise the first data access request.
Branover discloses the computing device maintains at least one request queue, and when the at least one request queue comprises processes or threads corresponding to a plurality of data access requests, the computing device performs the processes or threads corresponding to the plurality of data access requests in a synchronous manner, wherein the plurality of data access requests comprise the first data access request (Branover – Par. [0044] discloses substantially contemporaneously (as shown by the parallel illustration of steps 308 and 310 in FIG. 3), based on being notified, at least one of the other clients (i.e., that has job items to be processed using the shared resource) processes job items using the shared resource (step 310). For this operation, one or more of the other clients (e.g., other cores, the media processing subsystem, etc.) which have and/or have buffered memory access requests (i.e., memory access requests stored in a corresponding queue) processes those memory access requests.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Branover’s teachings with Romem and Horwich’s techniques for saving the electrical power required to transition the shared resource between the power states for processing job items and avoid the delay required for the transitions (Branover – Par. [0016]).
Referring to claims 12 and 19, note the rejections of claim 5 above. The Instant Claims recite substantially same limitations as the above-rejected and is therefore rejected under same prior-art teachings.
Conclusion
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R.I .Ill(c).
In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAYTON LEWIS-TAYLOR whose telephone number is (571) 270-7754. The examiner can normally be reached on Monday through Thursday, 8AM TO 4PM, EASTERN TIME.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye, can be reached on (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DAYTON LEWIS-TAYLOR/Examiner, Art Unit 2181