DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1-10 are objected to because of the following informalities:
Regarding claim 1, no transitional phrases, (for examples: “comprising”, “consisting of” or “including”) are found in the claim. Thus, it is unclear about the scope of the claim with respect to what unrecited additional components or steps, if any, are excluded from the scope of the claims, or what limitations should be considered as the body/preamble of the claims.
Depending claims 2-10 are objected to by virtue of their dependency on a based claim.
Regarding claim 3, in line 3, the term “the integer” seems to refer back to the integer “0” in line 2, if that is the case, amending “0” to “integer 0” to provide consistency.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, in line 14, the term “the distance” has no antecedent basis.
In line 18, the term “the next connecting router” has no antecedent basis. In line 23, the term “the subsequent” has no antecedent basis.
Regarding claim 3, in line 2, the term “the bottom planar” has no antecedent basis. In lines 3-4, the term “the subsequent planar” has no antecedent basis.
Regarding claim 5, in lines 8-9, the terms “the router link layer value” and “the previous assigned router” have no antecedent basis.
Regarding claim 10, in line 10, the term “the mapped value” has no antecedent basis.
Depending claims 2, 4, 6-9 are rejected by virtue of their dependency on a rejected based claim.
Allowable Subject Matter
Claim 1 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Claims 2-10 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The prior art of record fails to disclose the features for generating and assigning an ascending value to each router link layer for every link in between two routers of the same planar-axis coordinate (102); selecting one router with the smallest value of the router link layer as an origin router (103); assigning the origin router with a coordinate comprising a horizontal-axis, X, and a vertical-axis, Y (104); calculating the distance of the coordinates X and Y with respect to the router link layer for every router link layer (105); generating and assigning a coordinate comprises a horizontal-axis, X, and a vertical axis, Y, to each router adjacent to the origin router based on the distance calculated for every router link layer, followed by the next connecting router of the same planar-axis coordinate (106); applying coordinate shrinking to get all coordinates in positive integer numbers with optimized ascending order (107); and repeating the steps from generating and assigning an ascending value to each router link layer for every link in between two routers of the subsequent planar-axis coordinate to complete the generation and assignment of coordinates to all planar-axis routers (108), as recited in claim 1.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Bharadwaj et al. (Pub No.: 2020/0153757) discloses system is described that includes an integrated circuit chip having a network-on-chip. The network-on-chip includes multiple routers arranged in a topology and a separate communication link coupled between each router and each of one or more neighboring routers of that router among the multiple routers in the topology. The integrated circuit chip also includes multiple nodes, each node coupled to a router of the multiple routers. When operating, a given router of the multiple routers keeps a record of operating states of some or all of the multiple routers and corresponding communication links. The given router then routes flits to destination nodes via one or more other routers of the multiple routers based at least in part on the operating states of the some or all of the multiple routers and the corresponding communication links.
Bellovin (Pub No.: 2005/0135231) discloses a method for the efficient routing of data packets across a plurality of routers when a link is unavailable which includes connecting a plurality of nodes in a network using a plurality of routers having a plurality of links between the routers, informing the routers in the network when one or more of the links in the network will be unavailable at a specified time in the future, recalculating the routing tables to determine the most efficient routing paths when the links in the network become unavailable and, when the time in the future arrives, switching the routers in the network to the new routing tables at the same time.
Bharadwaj (Pat NO.: 11,398,980) discloses an integrated circuit includes a network on chip (NOC) that includes a plurality of processing elements and a plurality of NOC nodes, interconnected to the plurality of processing elements. The integrated circuit includes logic that is configured to: increment by one, a virtual channel identifier to produce an incremented destination VC identifier, the virtual channel (VC) identifier associated with at least portion of a packet stored in at least one virtual channel buffer; determine that a destination virtual channel buffer corresponding to the incremented destination VC identifier in a destination NOC node in the NOC is available to store the portion of the packet; and in response to the determination, send the portion of the packet and the incremented destination VC identifier to the destination NOC node.
Kumar et al. (Pub No.: 2014/0177473) discloses a network-on-chip configuration includes a first plurality of cores arranged in a two-dimensional mesh; a first plurality of routers, each of the first plurality of routers associated with a corresponding local one of the first plurality of cores, each of the first plurality of routers having a plurality of directional ports configured to provide connections to other ones of the first plurality of routers; a second plurality of cores disposed around a periphery of the two-dimensional mesh arrangement; and a second plurality of routers, each of the second plurality of routers associated with a corresponding local one of the second plurality of cores, and having a directional port configured to provide a connection to a neighboring one of the first plurality of routers.
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/KAN YUEN/Primary Examiner, Art Unit 2464