Prosecution Insights
Last updated: April 19, 2026
Application No. 18/417,875

OPTICAL FLOW SWITCHING USING PHOTONIC INTEGRATED CIRCUITS

Non-Final OA §102§103
Filed
Jan 19, 2024
Examiner
CAPUTO, LISA M
Art Unit
2874
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Lightmatter Inc.
OA Round
1 (Non-Final)
8%
Grant Probability
At Risk
1-2
OA Rounds
2y 2m
To Grant
0%
With Interview

Examiner Intelligence

Grants only 8% of cases
8%
Career Allow Rate
3 granted / 38 resolved
-60.1% vs TC avg
Minimal -8% lift
Without
With
+-7.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
22 currently pending
Career history
60
Total Applications
across all art units

Statute-Specific Performance

§101
4.5%
-35.5% vs TC avg
§103
48.0%
+8.0% vs TC avg
§102
25.4%
-14.6% vs TC avg
§112
18.6%
-21.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 38 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-2, 14, 19-21, 25-26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Seok et al. (“Wafer-scale silicon photonic switches beyond die size limit”, Optica, Vol 6, No 4, April 2019, from hereinafter “Seok”). Regarding claim 1, Seok teaches an optical flow switch (see Abstract), optical switches have been proposed as a promising alternative to enable continual scaling of data centers with increasing size and data rates (it is noted that an optical flow switch is defined as an optical switch that routes optical signals between portions of the data center or computing system in Applicant's current specification), comprising a network of photonic switches arranged between input and output ports of the optical flow switch (see Fig. 3(a); Pg 492, col 1: All three building blocks (Input, output, and switch) have a footprint of 1 cm x 1 cm), wherein the network of photonic switches spans two or more reticles (See Abstract, a 240 X 240 switch was fabricated by lithographically stitching a 3 >> 3 array of identical 80 x 80 switch blocks across reticle boundaries; see pg 491, col 2; The offset between adjacent reticles in the deep-UV stepper (ASML 5500/300) is less than 100 nm). Regarding claim 2, Seok teaches wherein the two or more reticles comprise a same reticle pattern (see page 490, col 1-2, step and repeat lithography stepper), and the network of photonic switches is formed of a repeating arrangement of the same reticle pattern (see page 490, col 2 step and repeat lithography stepper). Regarding claims 14, Seok teaches wherein the two or more reticles comprise rows or columns of reticles, each row or column of reticles being formed using a same set of reticle patterns (see page 490, col 2 step and repeat lithography stepper, blocks have rows and columns). Regarding claims 19-21, Seok teaches wherein photonic switches of the network of photonic switches that are disposed in a first reticle are coupled to photonic switches of the network of photonic switches disposed in a second reticle by waveguides (regarding claim 19). Regarding claim 20, wherein photonic switches of the network of photonic switches are disposed in an arrangement spanning two or more chip and regarding claim 21, wherein the two or more chips are coupled using optical fibers (see page 491, col 2). Regarding claim 25, Seok teaches wherein photonic switches comprise silicon photonic switches (see page 490, columns 1-2). Regarding claim 26, Seok teaches wherein the input and output ports comprise grating couplers, edge couplers, and/or v-groove couplers (see edge couplers, page 490, column 1, line 5). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 3-7, 11-13, and 22-24 are rejected under 35 U.S.C. 103 as being unpatentable over Seok in view of Hosseini et al. (USPGPub 2020/0393737, from hereinafter “Hosseini”). Regarding claims 3-7 and 11-13, Seok discloses the optical flow switch of claim 1, but does not specifically teach wherein the network of photonic switches comprises a Cantor network or a Benes network, which entails Benes switches and their placements. In the same field of endeavor, Hosseini teaches an optical switch array (see Abstract, paragraph [0063]: an optical switching apparatus comprises: Input ports receiving respective input optical waves, each coupled to a respective beam-forming structure a spatially distributed phase shifter to apply different reception optical phase shifts over different portions of the respective spatial region, where the reception optical phase shifts determine the selected reception angle and an output optical waveguide) defined by reticles (see paragraph [0068]) wherein the network of photonic switches comprises a Cantor network or a Benes network (see paragraph [0081]-[0083]: an example of 16x16 optical switching network formed with integrated optical waveguides connecting individual 2x2 switches in such configurations, a 2x2 MZI type switch can be used as the basic building block of the system and the number of waveguide crossing used in such system grows exponentially; a network with the topology shown in this example is typically called a Benes network). Additionally, regarding claims 12-13, Hosseini teaches the coupling of Benes switches and output ports (see paragraph [0082]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the network of photonic switches of Seok to comprise a Cantor network or a Benes network, as disclosed by Hosseini to provide a NxN switch architecture as known in the art (see para [0081]) in order to have an efficient, well-run system. Regarding claims 22-24, Seok fails to specifically teach wherein photonic switches of the network of photonic switches comprise a 2x2 Mach-Zehnder interferometer (MZI) switch, or further arrangements thereof, such as three MZI switches in series. Hosseini teaches an example of 16x16 optical switching network formed with integrated optical waveguides connecting individual 2x2 switches in such configurations, a 2x2 MZI type switch can be used as the basic building block of the system (see paragraph [0081]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a notoriously well-known MZI type switch/series of switches for a stable foundation for the optical switching network. Allowable Subject Matter Claims 8-10 and 15-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. For example, regarding claim 9, the best prior art of record fails to teach the specific Cantor and Benes network equation. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US Patent No. 6,259,833 to Doerr et al. Any inquiry concerning this communication or earlier communications from the examiner should be directed to LISA M CAPUTO whose telephone number is (571)272-2388. The examiner can normally be reached Monday-Friday 9-5 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached at 571-272-2397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LISA M CAPUTO/Primary Patent Examiner, Art Unit 2874
Read full office action

Prosecution Timeline

Jan 19, 2024
Application Filed
Feb 07, 2026
Non-Final Rejection — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
8%
Grant Probability
0%
With Interview (-7.9%)
2y 2m
Median Time to Grant
Low
PTA Risk
Based on 38 resolved cases by this examiner. Grant probability derived from career allow rate.

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