DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The disclosure is objected to because of the following informality: On Page 8, line 22, replace “impedances ZCM2” with “impedances ZCM1, ZCM2”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-9 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 1 and 8 recite that the two-poles are connected to source terminals of the input transistors of the master amplifier. However, the specification and drawings only show the two-poles connected to drain terminals of the input transistors of the master amplifier. Therefore, the specification fails to provide sufficient support for the claimed invention. Claims 2-7 and 9 are likewise rejected under this logic by virtue of their dependencies on claim 1.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 and 8 recite that the two-poles are connected to source terminals of the input transistors of the master amplifier. However, the specification and drawings only show the two-poles connected to drain terminals of the input transistors of the master amplifier. Therefore, it is unclear whether the two-poles are supposed to be connected to the source or drain terminals of the input transistors of the master amplifier. Amending the claims to recite connection to drain terminals is sufficient to overcome this rejection, which is how the limitations will be treated for examination purposes. Claims 2-7 and 9 are likewise rejected under this logic by virtue of their dependencies on claim 1.
Claim 6 recites the limitation “wherein a fourth impedance is connected between a further drain terminal on the one hand, and the gate terminal and a further gate terminal of the current source on the other hand” in lines 1-4. There is insufficient antecedent basis for this limitation in the claim. Amending the limitation to “wherein a fourth impedance is connected between a further drain terminal on a first side, and the gate terminal and a further gate terminal of the current source on a second side” is sufficient to overcome this rejection, which is how the limitation will be treated for examination purposes.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, and 7-8 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Kuge (Patent Publication Number US 2017/0288621 A1), hereafter referred to as Kuge.
Regarding claim 1, Kuge discloses:
A differential amplifier for operating a sensor (Kuge, Figs. 1, 3, and 22), comprising: a first two-pole (Fig. 22, SW51) including a first semiconductor switch (Fig. 22, MN11) and a second semiconductor switch (Fig. 22, MP11) connected in antiparallel to one another (Fig. 22, consider antiparallel connection of MN11 and MP11); and a second two-pole (Fig. 22, SW52) including a third semiconductor switch (Fig. 22, MN21) and a fourth semiconductor switch (Fig. 22, MP21) connected in antiparallel to one another (Fig. 22, consider antiparallel connection of MN21 and MP21); wherein a first terminal of the first two-pole is connected to a drain terminal of a current source of a master amplifier of the differential amplifier (Fig. 22, consider connection between SW11 and SW51, Fig. 3, consider connection between SW11 and drain of Tr13), and a second terminal of the first two-pole is connected to a first terminal of the second two-pole (Fig. 22, see connection between SW51 and SW52), wherein a second terminal of the second two-pole is furthermore connected to a source terminal of an input transistor of the master amplifier (Fig. 22, see connection between SW52 and SW12, Fig. 3, see connection between SW12 and drain terminal of Tr12, note claim interpretation of “source terminal of an input transistor” as “drain terminal of an input transistor” above).
Regarding claim 3, Kuge further discloses:
wherein the second terminal of the first two-pole is connected to a gate terminal of a transistor of a common-mode amplifier of the differential amplifier (Kuge, Fig. 22, see connection between SW51 and SW13, Fig. 3, see connection between SW13 and gate of Tr1).
Regarding claim 7, Kuge further discloses:
wherein the second terminal of the second two-pole is connected to a second drain terminal of the current source of the master amplifier (Kuge, Fig. 22, see connection between SW52 and SW12, Fig. 3, see connection between SW12 and drain of TR14).
Regarding claim 8, Kuge further discloses:
wherein the second terminal of the second two-pole is connected to a first source terminal of an input transistor of the master amplifier (Kuge, Fig. 22, see connection between SW52 and SW12, Fig. 3, see connection between SW12 and drain of TR12, note claim interpretation of “source terminal of an input transistor” as “drain terminal of an input transistor” as discussed above), and the first terminal of the first two-pole is connected to a second source terminal of another input transistor (Fig. 22, see connection between SW51 and SW11, Fig. 3 see connection between SW11 and drain of TR11, note claim interpretation of “second source terminal of another input transistor” as “second drain terminal of another input transistor” as discussed above).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2- are rejected under 35 U.S.C. 103 as being unpatentable over Kuge as applied to claim 1 above, and further in view of Kaczman et al. (Patent Publication Number US 2009/0191833 A1), hereafter referred to as Kaczman.
Regarding claim 2, Kuge fails to disclose:
wherein: the first two-pole includes a first impedance, which is connected in parallel to the first and second semiconductor switches, and the second two-pole includes a second impedance, which is connected in parallel to the third and fourth semiconductor switches.
However, Kaczman teaches wherein: the first two-pole includes a first impedance (Kaczman, Fig. 2, R3), which is connected in parallel to the first and second semiconductor switches (Fig. 2, see parallel connection between R3 and left transistor of 214), and the second two-pole includes a second impedance (Fig. 2, R4), which is connected in parallel to the third and fourth semiconductor switches (Fig. 2, see parallel connection between R4 and right transistor of 214).
Kuge and Kaczman are both considered to be analogous to the claimed invention because they are in the same field of improving differential amplifier circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Kuge to incorporate the teachings of Kaczman to include the common-mode feedback circuit of Kaczman in the circuit of Kuge, which would have the effect of providing gain control for the amplifier of Kuge (Kaczman, Paragraph 37, lines 16-26).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Kuge as applied to claim 1 above, and further in view of Opris et al. (Patent Publication Number US 2013/0263665 A1), hereafter referred to as Opris.
Regarding claim 4, Kuge fails to disclose:
wherein the sensor is a Mems sensor.
However, Opris teaches wherein the sensor is a Mems sensor (Opris, Paragraph 10, lines 1-7).
Kuge and Opris are both considered to be analogous to the claimed invention because they are in the same field of improving differential amplifier circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Kuge to incorporate the teachings of Opris to include the circuit of Kuge in a MEMS sensor, which would have the effect of providing a well-known real world implementation for the circuit of Opris (Kuge, Paragraph 10, lines 1-7).
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Kuge as applied to claim 1 above, and further in view of Ogawa (Patent Publication Number JP 2006/115,234 A), hereafter referred to as Ogawa.
Regarding claim 5, Kuge fails to disclose:
wherein a third impedance is connected between the drain terminal and a gate terminal of the current source.
However, Ogawa teaches wherein a third impedance (Ogawa, Fig. 1, R11) is connected between the drain terminal and a gate terminal of the current source (Fig. 1, see connection between drain of 11 and gate of 25 via resistor R11 [and R21]).
Kuge and Ogawa are both considered to be analogous to the claimed invention because they are in the same field of improving differential amplifier circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Kuge to incorporate the teachings of Ogawa to include the impedance of Ogawa in the circuit of Kuge, which would have the effect of improving operation speed of the circuit of Kuge (Ogawa, Page 1, Section “TECHNICAL-FIELD”, lines 1-2).
Regarding claim 6, Kuge fails to disclose:
wherein a fourth impedance is connected between a further drain terminal on the one hand, and the gate terminal and a further gate terminal of the current source on the other hand.
However, Ogawa further teaches wherein a fourth impedance (Ogawa, Fig. 1, R12) is connected between a further drain terminal on the one hand (Fig. 1, see connection between R12 and drain of 12), and the gate terminal and a further gate terminal of the current source on the other hand (Fig. 1, see connection between gate of 25 and R11 via R21 and connection between gate of 24 and R11 via R22).
Kuge and Ogawa are both considered to be analogous to the claimed invention because they are in the same field of improving differential amplifier circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Kuge to incorporate the teachings of Ogawa to include the impedance of Ogawa in the circuit of Kuge, which would have the effect of improving operation speed of the circuit of Kuge (Ogawa, Page 1, Section “TECHNICAL-FIELD”, lines 1-2).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kuge as applied to claim 1 above, and further in view of Makino (Patent Number TW 427,065 B), hereafter referred to as Makino.
Regarding claim 9, Kuge fails to disclose:
wherein: substrate terminals of the first semiconductor switch and of the second semiconductor switch are galvanically connected to a supply voltage, and/or substrate terminals of the third semiconductor switch and of the fourth semiconductor switch are galvanically connected to the supply voltage.
However, Makino teaches wherein: substrate terminals of the first semiconductor switch and of the second semiconductor switch are galvanically connected to a supply voltage, and/or substrate terminals of the third semiconductor switch and of the fourth semiconductor switch are galvanically connected to the supply voltage (Makino, Fig. 1, consider connection between substrate terminals of Q7 and Q8 and supply voltage 27).
Kuge and Makino are both considered to be analogous to the claimed invention because they are in the same field of improving amplifier CMOS circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Kuge to incorporate the teachings of Makino to include the switch supply voltage connections of Makino in the circuit of Kuge, which would have the effect of providing an appropriate supply voltage connection for the transistors of Kuge.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Matsuoka (Patent Publication Number US 2021/0242845 A1) discloses (Fig. 3) a differential amplifier for use in a sensor.
Cao et al. (Patent Publication Number CN 113,726,298 A) discloses (Fig. 3) a differential amplifier for use in a sensor.
Zhao et al. (Patent Publication Number CN 103,166,627 A) discloses (Figs. 1/2) differential amplifiers for use in a sensor.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lance T Bartol whose telephone number is (703)756-1267. The examiner can normally be reached Monday - Thursday 6:30 a.m. - 4:00 p.m. CT, Alternating Fridays 6:30 - 3:00.
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/LANCE TORBJORN BARTOL/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
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