Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
OFFICE ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) The claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) The claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 12 and 19 are rejected under 35 U.S.C. 102(a) (2) being anticipated by the prior art of record Suzuki (US 2023/0215858)
Regarding claims 1-3, the prior art discloses:
A processing unit, comprising:
a die, wherein the die is bifurcated; wherein the bifurcation is configured to render the die into a first slice and a second slice (first die and second die (par 16-17)); and
a substrate (substrate is inherent for die/chip mount/assemble), configured to couple with the die at a first orientation (One orientation of the two orientations in par 17),
wherein the substrate is further configured to couple with the die at a second orientation; wherein the second orientation is one-hundred and eighty degrees relative to the first orientation (second die may be rotated substantially 180° around an axis normal to the first die (par 16), one of the orientations rotated substantially 180° relative to the other (par 13))
(Claim 4) wherein the first slice and second slice have similar communication channels (common channels/connections/pads, pad of the copy of the die (par 19-20, 53-54, 62-64))
(Claim 5) wherein the communication channels include a plurality of SerDes channels (par 42).
Claims 12 and 19 recite similar subject matter and rejected for the same reason
Claims 1-20 are rejected under 35 U.S.C. 102(a) (2) being anticipated by the prior art of record Azadet (US 2023/0236999)
Regarding claims 1-3, the prior art discloses:
A processing unit, comprising:
a die, wherein the die is bifurcated; wherein the bifurcation is configured to render the die into a first slice and a second slice (fig 1A).
and a substrate (see one or more of par 2-3, 19, 23, 26, 32, 46, 48, 63, 73, 88, 98), configured to couple with the die at a first orientation,
wherein the substrate is further configured to couple with the die at a second orientation; wherein the second orientation is one-hundred and eighty degrees relative to the first orientation (fig 1A)
(Claim 4) wherein the first slice and second slice have similar communication channels (similar bumps, identical traces/routes, set of bumps (e.g., a 12-pack) are the same (par 22-24)).
(Claim 5) wherein the communication channels include a plurality of SerDes channels.
(Claim 6) wherein the plurality of SerDes channels are divided equally between the first slice and the second slice.
(Claim 7) wherein the substrate is configured with a plurality of corresponding SerDes channels (see one or more of par 7, 10, 25, 36-39, 44, 58, 71, 83, 96).
(Claim 8) wherein the substrate extends outward from the die on all four sides when coupled (fig 1)
(Claim 9) wherein the plurality of corresponding SerDes channels on the substrate are disposed on three of the four sides (fig 1).
(Claim 10) wherein the corresponding SerDes channels are communicatively coupled to the plurality of SerDes channels on the substrate through a matching plurality of traces (equal length, trace length match, identical traces/routes, set of bumps (e.g., a 12-pack) are the same (abstract, par 14-15, 22-23-24, 46, 68, 76, 93))
(Claim 11) wherein the corresponding plurality of SerDes channels on the substrate are arranged to facilitate shorter trace lengths of the matching plurality of traces (fig 1A shows shorter trace lengths resulted from rotating one die 180 degree relative to the other)
Claims 12-20 recite similar subject matter and rejected for the same reason
Claims 1-20 are rejected under 35 U.S.C. 102(a) (2) being anticipated by the prior art of record Chiu (US 2024/0128252)
Regarding claims 1-3, the prior art discloses:
A processing unit, comprising:
a die, wherein the die is bifurcated; wherein the bifurcation is configured to render the die into a first slice and a second slice (first die and second die in par 3-4, 35-39, fig 1)).
and a substrate (fig 1-3, 6-8, 13-18), configured to couple with the die at a first orientation,
wherein the substrate is further configured to couple with the die at a second orientation; wherein the second orientation is one-hundred and eighty degrees relative to the first orientation (second die 110B can be flipped/oriented and rotated 180 degrees (par 36, 62-63, 80))
(Claim 4) wherein the first slice and second slice have similar communication channels (similar/same interface/structure/mask, dies 110A and 110B can include same circuits, computation circuit 120A and the computation circuit 120B can have a same structure, dies 110A and 110B thereto and having a same function may be coupled to each other, dies inside a same semiconductor structure can communicate with each other through intra-stack connection circuit(par 28, 31, 39, 58-60, 103-104, 108)
(Claim 5) wherein the communication channels include a plurality of SerDes channels (abstract, par 33-34)
(Claim 6) wherein the plurality of SerDes channels (abstract, par 33-34) are divided equally between the first slice and the second slice (similar/same interface/structure/mask, dies 110A and 110B can include same circuits, computation circuit 120A and the computation circuit 120B can have a same structure, dies 110A and 110B thereto and having a same function may be coupled to each other, dies inside a same semiconductor structure can communicate with each other through intra-stack connection circuit(par 28, 31, 39, 58-60, 103-104, 108)
(Claim 7) wherein the substrate is configured with a plurality of corresponding SerDes channels (abstract, par 33-34)
(Claim 8) wherein the substrate extends outward from the die on all four sides when coupled (fig 1-3, 6-8, 13, 17)
(Claim 9) wherein the plurality of corresponding SerDes channels on the substrate are disposed on three of the four sides (fig 1-3, 6-8, 13, 17).
(Claim 10) wherein the corresponding SerDes channels are communicatively coupled to the plurality of SerDes channels on the substrate through a matching plurality of traces (connects the top die and the bottom die in the shortest distance, dies 110A and 110B thereto and having a same function may be coupled to each other, computation circuits in the same die can still be coupled to each other through intra-stack connection (abstract, par 39, 96))
(Claim 11) wherein the corresponding plurality of SerDes channels on the substrate are arranged to facilitate shorter trace lengths of the matching plurality of traces (connects the top die and the bottom die in the shortest distance,
vertical connections between the dies 110A and 110B provided by the intra-stack connection circuits 140A and 140B so as to shorten signal paths (abstract, par 37))
Claims 12-20 recite similar subject matter and rejected for the same reason
Claims 1 and 3-20 are rejected under 35 U.S.C. 102(a) (1) being anticipated by the prior art of record Lee (US 2025/0062288)
Regarding claims 1 and 3, the prior art discloses:
A processing unit, comprising:
a die, wherein the die is bifurcated; wherein the bifurcation is configured to render the die into a first slice and a second slice (master chip (first slice) and slave chip (second slice) in par 7, 39, 258)
and a substrate, configured to couple with the die at a first orientation (first orientation is one of layout/ arrangement/ placement / stacking/ orientation shown in one or more of fig. 3-8, 11, 15-17, 20, 23, 25),
wherein the substrate is further configured to couple with the die at a second orientation (second orientation is another one of layout/ arrangement/ placement / stacking / orientation shown in one or more of fig. 3-8, 11, 15-17, 20, 23, 25).
(Claim 4) wherein the first slice and second slice have similar communication channels (see one or more of fig 5-8, 11, 15-17, 20, 23, 25).
(Claim 5) wherein the communication channels include a plurality of SerDes channels (see one or more of fig 5-8 and/or par 73-110)
(Claim 6) wherein the plurality of SerDes channels are divided equally between the first slice and the second slice (fig 5-8).
(Claim 7) wherein the substrate is configured with a plurality of corresponding SerDes channels (one or more of fig. 3-8, 11, 15-17, 20, 23, 25).
(Claim 8) wherein the substrate extends outward from the die on all four sides when coupled (see one or more of fig 2-4, 10-14, 16-17, 19-25)
(Claim 9) wherein the plurality of corresponding SerDes channels (see one or more of fig 5-8 and/or par 73-110) on the substrate are disposed on three of the four sides (see one or more of fig 2-4, 10-14, 16-17, 19-25)
(Claim 10) wherein the corresponding SerDes channels (see one or more of fig 5-8 and/or par 73-110) are communicatively coupled to the plurality of SerDes channels on the substrate through a matching plurality of traces (see one or more of fig. 3-8, 11, 15-17, 20, 23, 25).
(Claim 11) wherein the corresponding plurality of SerDes channels on the substrate are arranged to facilitate shorter trace lengths of the matching plurality of traces (see at least: short length that connects the slice signal pads and shorter length in par 116, 217)
Claims 12-20 recite similar subject matter and rejected for the same reason
Correspondence Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL DINH whose telephone number is 571-272-1890. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s Supervisor, Jack Chiang can be reached on 571-272-7483. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PAUL DINH/ Primary Examiner, Art Unit 2851
