DETAILED ACTION
This office action is in reply communication filed on 01/21/2024
Claims 1-26 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 18, and 25-26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bushnell et al. (US 2016/0299221).
Regarding claim 1, Bushnell discloses a system [Fig. 4, ¶ 61; a system 400], comprising:
a first device [Fig. 4, ¶ 62; platforms 402] including:
a first clock to maintain a first clock time [Fig. 4, ¶ 62; first clocks 420 to maintain a first clock time];
a first n-pulse-per-second (nPPS) output interface [Fig. 4, ¶ 64; first pulsed laser 408]:
to be connected to a second nPPS input interface of a second device via a first clock connection [Fig. 4, ¶ 64; to be connected to second signal receiver 418 of second platform 404 via pulse laser 426]; and
to send a first pulse at a time A to the second nPPS input interface for receipt by the second nPPS input interface at a time B [Fig. 4, ¶ 62; to send first pulse trains 426 at time t.sub.Asend (Fig. 1, ¶ 24) to the second signal receiver 418 of the second platform 404 at time t.sub.Areceived (Fig. 1, ¶ 24)]; and
a first nPPS input interface [Fig. 4, ¶ 64; first signal receiver 416 of the first platform 404]:
to be connected to a second nPPS output interface of the second device via a second clock connection [Fig. 4, ¶ 62; to be connected to a third pulsed laser 412 of the second platform 402 via a second pulse train 428];
to receive a second pulse at a time D from the second nPPS output interface sent by the second nPPS output interface at a time C [Fig. 4, ¶ 62; to receive a second pulse train 428 at a time t.sub.Breceived (Fig. 1, ¶ 24) from the third pulsed laser 412 of the second platform 404 at a time t.sub.Bsend (Fig. 1, ¶ 24)]; and
to log the time D in a first memory [Fig. 4, ¶ 69; first and second counters 446, 448 record the respective times at which the pulses where sent and received]; and
delay computation circuitry [Fig. 3, ¶ 54; processor 308 of platform 1/(platform 402); (FIGS. 2-4 may be combined, divided, re-arranged, omitted, eliminated and/or implemented in any other way)] to compute a clock connection delay in at least one of the first clock connection or the second clock connection based on the time A, the time D, and a time difference between receiving the first pulse in the second device and sending the second pulse from the second device [Fig. 4, ¶¶ 40, 44, 70; determine the clock offset Δt, or the time difference between the local clock 420 of the first platform 402 and the local clock 422 of the second platform 404; also See ¶ 81, calculating a relative distance and/or positioning between the first and second platforms based on one more techniques for determining the relative measurements in view of the time difference calculated at block 518].
Regarding claim 2, Bushnell discloses the system according to claim 1.
Bushnell further discloses
clock synchronization circuitry to discipline the first clock of the first device, or a second clock of the second device, responsively to a pulse received by the first device or the second device, respectively, and the computed clock connection delay [see ¶ 44; the time offset Δt calculated from Equation 7 can be used to correct one of the clocks of Aircraft A or Aircraft B so the time offset Δt is equal to zero and the clocks between Aircraft A and Aircraft B are synchronized].
Regarding claim 3, the combined system of HICHEMRAJ and CATT discloses the system according to claim 1.
Bushnell further discloses
wherein the delay computation circuitry is to compute the time difference between receiving the first pulse in the second device and sending the second pulse from the second device based on the time B and the time C [see ¶¶ 70, 81; where in the balanced detector 226 is configured to determine/compute the clock offset Δt based on an average of a first time difference between a time when Aircraft A sends a pulse (according to the clock on Aircraft A) and when Aircraft B receives the pulse (according to the clock on Aircraft B) and a second time difference between a time when Aircraft B sends a pulse (according to the clock on Aircraft B) and when Aircraft A receives the pulse (according to the clock on Aircraft A) (see ¶ 44)].
.
Regarding claim 4, the combined system of HICHEMRAJ and CATT discloses the system according to claim 1.
Bushnell further discloses
wherein the time difference between receiving the first pulse in the second device and sending the second pulse from the second device is computed based on the time B and the time C [see Fig. 1, ¶¶ 22-24; wherein the time difference Δt between receiving the first pulse train 106 in the Aircraft B/second device and sending the second pulse train 108 from the Aircraft B/second device is computed based on the time t.sub.Areceived and the time t.sub.Bsend], the delay computation circuitry being to receive the computed time difference from the second device [see ¶ 25; one of Aircraft A or Aircraft B adjusts an overlap between the respective pulses transmitted by and received at the aircraft to locally adjust the locking of the pulses (see FIG. 3 and ¶¶ 55-56)].
Regarding claim 18, Bushnell discloses a system [Fig. 4, ¶ 61; a system 400], comprising:
a second device [Fig. 4, ¶ 62; platforms 404] including:
a second n-pulse-per-second (nPPS) input interface [Fig. 4, ¶ 64; second signal receiver 418]:
to be connected to a first nPPS output interface of a first device via a first clock connection [Fig. 4, ¶ 64; to be connected to first pulsed laser 408 of first platforms 402 via second pulse train 428];
to receive a first pulse at a time B from the first nPPS output interface sent by the first nPPS output interface at a time A [Fig. 4, ¶ 62; to receive first pulse trains 426 at time t.sub.Areceived (Fig. 1, ¶ 24) from first pulsed laser 408 of first platform 402 at time t.sub.Asend (Fig. 1, ¶ 24)]; and
to log the time B in a second memory [Fig. 4, ¶ 69; first and second counters 446, 448 record the respective times at which the pulses where sent and received];
a second nPPS output interface [Fig. 4, ¶ 64; third pulsed laser 412]:
to be connected to a first nPPS input interface of the first device via a second clock connection [Fig. 4, ¶ 62; to be connected to a first signal receivers 416 of the first platform 402 via a second pulse train 428]; and
to send a second pulse at a time C to the first nPPS input interface for receipt by the first nPPS input interface at a time D [Fig. 4, ¶ 62; to send a second pulse train 428 at a time t.sub.Bsend (Fig. 1, ¶ 24) to the second signal receivers 416 of the first platform 402 at a time t.sub.Breceived (Fig. 1, ¶ 24)]; and
a controller [Fig. 2, 3, 4, ¶ 29; PRF regulator 224/second PRF regulator 432 of platform N/(platform 404); (FIGS. 2-4 may be combined, divided, re-arranged, omitted, eliminated and/or implemented in any other way)] to detect receipt of the first pulse and cause the second nPPS output interface to send the second pulse to the first device via the second clock connection in response to detecting the receipt of the first pulse [Fig. 4, ¶¶ 29, 66, 68; detect or determine the pulse frequency repetition of the received first pulse train 216 cause the third pulsed laser 412 to send the second pulse 428 to the first platforms 402 via the second pulse train 218/428 in response to detecting the receipt of the first pulse train 216/426].
Regarding claim 25, the claim recites a method to perform the functions of the system recited as in claim 1; therefore, claim 25 is rejected along the same rationale that rejected in claim 1.
Regarding claim 26, the claim recites a method to perform the functions of the system recited as in claim 18; therefore, claim 26 is rejected along the same rationale that rejected in claim 18.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 12-13, 18-19, and 25-26 are rejected under 35 U.S.C. 103 unpatentable over HICHEMRAJ (CN 110581744) in view of CATT (AU 2023/200522).
Regarding claim 1, HICHEMRAJ discloses a system [See Figs. 1, 7, page 5 line 26; a system 700], comprising:
a first device including [See Fig. 7, page 5 lines 26; slave card 703]:
a first clock to maintain a first clock time [See Fig. 7, page 5 lines 32; ToD counter (ToDA)];
a first n-pulse-per-second (nPPS) output interface [See Fig. 7, page 6 lines 7-15; physical layer (PHY) of slave card 703 in connection with control plane 701]:
to be connected to a second nPPS input interface of a second device via a first clock connection [See Fig. 7, page 5 lines 46-47; connected to physical layer (PHY) of line card 705 in connection with control plane 701 via timestamp exchange 709/(first clock connection) from the card 703 via the control plane with the line card 705 in synchronous ToDA counter and the ToDB counter]; and
to send a first pulse at a time A to the second nPPS input interface for receipt by the second nPPS input interface at a time B [See Fig. 7; to send a 1PPS signal (t1 to t2) at a time t1 to the PHY of line card 705 in connection with control plane 701 at a time t2, also shown in FIG. 1, the 1 PPS signal 117a, 117b and 117c, and exchange shown at 105]; and
a first nPPS input interface [See Fig. 7, page 6 lines 7-15; physical layer (PHY) of slave card 703 in connection with control plane 701]:
to be connected to a second nPPS output interface of the second device via a second clock connection [See Fig. 7, page 5 lines 46-47; connected to physical layer (PHY) of line card 705 in connection with control plane 701 via timestamp exchange 709/(second clock connection)];
to receive a second pulse at a time D from the second nPPS output interface sent by the second nPPS output interface at a time C [See Fig. 7; to receive a 1PPS signal (t3 to t4) at a time t4 from the PHY of slave card 703 in connection with control plane 701, sent by the PHY of line card 705 in connection with control plane 701, at a time t3; also shown in FIG. 1, the 1 PPS signal 117a, 117b and 117c, and exchange shown at 105]; and
delay computation circuitry to compute a clock connection delay in at least one of the first clock connection or the second clock connection based on the time A, the time D, and a time difference between receiving the first pulse in the second device [See Fig. 11, page 8 lines 14-17; to compute tracking delay is divided by 2 symmetry on the bus can be used for delay accurately compensate in the master timing source and the back plate between each of the card (see Fig. 7, page 5 lines 45-50, the main card 705 in one of a ToD of counter ToDB starting timestamp exchange 709 from the card 703 via the control plane with the main card 705 in synchronous ToDA counter and the ToDB counter, based on the timestamp exchange (t1-t4), one-way delay (OWD) and error offset (see Fig. 1 in 107) for synchronizing the ToD counters TODA and DHBS] and sending the second pulse from the second device [See Fig. 2, page 5 lines 39-41; determining the tracking delay of the line card 203 is half of round trip time of the pulse emitted by the timing card 209].
HICHEMRAJ disclose all aspects of claim invention set forth above, but does not explicitly disclose to log the time D in a first memory.
However, CATT discloses to receive a second pulse at a time D from the second nPPS output interface sent by the second nPPS output interface at a time C [See Fig. 6, ¶ 76, step 634, the processing system 530 receives the reference data from the first second device 420];
to log the time D in a first memory [¶¶ 56, ; the processing device receiving the reference data, and recording an approximate local reference time for each timing pulse based on a time of local receipt determined using the local clock signal; also See Fig. 6, ¶ 76, step 634, the processing system 530 receives the reference data from the first second device 420, and records (in memory 532 of Fig. 5) an approximate local reference time for each timing pulse, at step 635]; and
delay computation circuitry to compute a clock connection delay in at least one of the first clock connection or the second clock connection based on the time A, the time D, and a time difference between receiving the first pulse in the second device and sending the second pulse from the second device [Fig. 6, ¶ 77; processing system 530 calculates an approximate first time for each timing pulse, using the first and second functions (synchronisation function can then be used to perform clock synchronisation of the first and second clock signals)].
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention was made to provide “to log the time D in a first memory” as taught by CATT in the system of HICHEMRAJ, so that it would to provide sensor fusion across multiple devices problematic, which is particularly pronounced in autonomous vehicles and other similar applications, where fusion of data from multiple sensors can be critical in ensuring accurate positional sensing and navigation [see CATT; ¶ 7].
Regarding claim 2, the combined system of HICHEMRAJ and CATT discloses the system according to claim 1.
HICHEMRAJ does not explicitly disclose further comprising
clock synchronization circuitry to discipline the first clock of the first device, or a second clock of the second device, responsively to a pulse received by the first device or the second device, respectively, and the computed clock connection delay.
However, CATT discloses further comprising clock synchronization circuitry to discipline the first clock of the first device, or a second clock of the second device, responsively to a pulse received by the first device or the second device, respectively, and the computed clock connection delay [See Fig. 6, ¶ 77; step 637, the processing system 530 calculates an approximate first time for each timing pulse, using the synchronisation function to perform clock synchronisation of the first and second clock signals].
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention was made to provide “clock synchronization circuitry to discipline the first clock of the first device, or a second clock of the second device, responsively to a pulse received by the first device or the second device, respectively, and the computed clock connection delay” as taught by CATT in the system of HICHEMRAJ, so that it would to provide sensor fusion across multiple devices problematic, which is particularly pronounced in autonomous vehicles and other similar applications, where fusion of data from multiple sensors can be critical in ensuring accurate positional sensing and navigation [see CATT; ¶ 7].
Regarding claim 12, the combined system of HICHEMRAJ and CATT discloses the system according to claim 1.
HICHEMRAJ discloses further comprising the first clock connection, the second clock connection, and the second device [see Fig. 7, page 5 line 26; timestamp exchange 709/(first clock connection), timestamp exchange 709/(second clock connection), line card 705/second device],
wherein: the second nPPS input interface [see Fig. 7, page 5; physical layer (PHY) of line card 705] is to: receive the first pulse at the time B [see Fig. 7, page 5; receive the 1PPS signal PHY of line card 705 in connection with control plane 701 at a time t2]; and log the time B in a second memory; and the second nPPS output interface is to send the second pulse to the first device via the second clock connection [See Fig. 7, page 5 lines 46-47; the line card 705/second device includes a controller to detect receipt of the 1PPS signal/first pulse and cause the PHY of slave card 705 in connection to send the 1PPS signal/second pulse (t3 to t4) to the line card 703/first device via the control plane 701 via the timestamp exchange 709/(second clock connection)].
Regarding claim 13, the combined system of HICHEMRAJ and CATT discloses the system according to claim 1.
HICHEMRAJ discloses further comprising the second device [see Fig. 7, page 5 line 26; line card 705/second device], wherein: the second nPPS input interface [see Fig. 7, page 5; physical layer (PHY) of line card 705] is to: receive the first pulse at the time B [see Fig. 7, page 5; receive the 1PPS signal PHY of line card 705 in connection with control plane 701 at a time t2]; and
the second device includes a controller to detect receipt of the first pulse and cause the second nPPS output interface to send the second pulse to the first device via the second clock connection in response to detecting the receipt of the first pulse [See Fig. 7, page 5 lines 46-47; the line card 705/second device includes a controller to detect receipt of the 1PPS signal/first pulse and cause the PHY of slave card 705 in connection to send the 1PPS signal/second pulse (t3 to t4) to the line card 703/first device via the control plane 701 via the timestamp exchange 709/(second clock connection) in response to detecting the receipt of the 1PPS signal/first pulse (t1 to t2)].
HICHEMRAJ disclose all aspects of claim invention set forth above, but does not explicitly disclose log the time B in a second memory; and the second nPPS output interface is to log the time C in the second memory.
However, CATT discloses log the time B in a second memory [¶ 56; the processing device receiving the reference data, and recording an approximate local reference time for each timing pulse based on a time of local receipt determined using the local clock signal; also See Fig. 6, ¶ 76, step 634, the processing system 530 receives the reference data from the first second device 420, and records (in memory 532 of Fig. 5) an approximate local reference time for each timing pulse, at step 635]; and
the second nPPS output interface is to log the time C in the second memory [¶ 56; the processing device receiving the reference data, and recording an approximate local reference time for each timing pulse based on a time of local receipt determined using the local clock signal; also See Fig. 6, ¶ 76, step 634, the processing system 530 receives the reference data from the first second device 420, and records (in memory 532 of Fig. 5) an approximate local reference time for each timing pulse, at step 635].
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention was made to provide “log the time B in a second memory; and the second nPPS output interface is to log the time C in the second memory” as taught by CATT in the system of HICHEMRAJ, so that it would to provide sensor fusion across multiple devices problematic, which is particularly pronounced in autonomous vehicles and other similar applications, where fusion of data from multiple sensors can be critical in ensuring accurate positional sensing and navigation [see CATT; ¶ 7].
Regarding claim 18, HICHEMRAJ discloses a system [See Figs. 1, 7, page 5 line 26; a system 700], comprising:
a second device including [See Fig. 7, page 5 lines 26; slave card 705]:
a second n-pulse-per-second (nPPS) output interface [See Fig. 7, page 6 lines 7-15; physical layer (PHY) of slave card 705 in connection with control plane 701]:
to be connected to a first nPPS input interface of a first device via a first clock connection [See Fig. 7, page 5 lines 46-47; connected to physical layer (PHY) of line card 703 in connection with control plane 701 via timestamp exchange 709/(first clock connection) from the card 703 via the control plane with the line card 705 in synchronous ToDA counter and the ToDB counter]; and
to receive a first pulse at a time B from the first nPPS input interface sent by the first nPPS input interface at a time A [See Fig. 7; to receive a 1PPS signal (t1 to t2) at a time t2 from the PHY of line card 703 in connection with control plane 701 at a time t1, also shown in FIG. 1, the 1 PPS signal 117a, 117b and 117c, and exchange shown at 105]; and
a second nPPS input interface [See Fig. 7, page 6 lines 7-15; physical layer (PHY) of slave card 705 in connection with control plane 701]:
to be connected to a first nPPS output interface of the first device via a second clock connection [See Fig. 7, page 5 lines 46-47; connected to physical layer (PHY) of line card 703 in connection with control plane 701 via timestamp exchange 709/(second clock connection)];
to send a second pulse at a time C to the first nPPS output interface for receipt by the first nPPS output interface at a time D [See Fig. 7; to receive a 1PPS signal (t3 to t4) at a time t3 from the PHY of slave card 705 in connection with control plane 701, for receipt by the PHY of line card 703 in connection with control plane 701, at a time t3; also shown in FIG. 1, the 1 PPS signal 117a, 117b and 117c, and exchange shown at 105]; and
a controller to detect receipt of the first pulse and cause the second nPPS output interface to send the second pulse to the first device via the second clock connection in response to detecting the receipt of the first pulse [See Fig. 7, page 5 lines 46-47; the line card 705/second device includes a controller to detect receipt of the 1PPS signal/first pulse and cause the PHY of slave card 705 in connection to send the 1PPS signal/second pulse (t3 to t4) to the line card 703/first device via the control plane 701 via the timestamp exchange 709/(second clock connection) in response to detecting the receipt of the 1PPS signal/first pulse (t1 to t2)].
HICHEMRAJ disclose all aspects of claim invention set forth above, but does not explicitly disclose to log the time B in a second memory.
However, CATT discloses to send a second pulse at a time D from the second nPPS output interface sent by the second nPPS output interface at a time C [See Fig. 6, ¶ 76, step 634, the processing system 530 send the reference data from the first second device 420];
to log the time B in a second memory [¶¶ 56, ; the processing device receiving the reference data, and recording an approximate local reference time for each timing pulse based on a time of local receipt determined using the local clock signal; also See Fig. 6, ¶ 76, step 634, the processing system 530 receives the reference data from the first second device 420, and records (in memory 532 of Fig. 5) an approximate local reference time for each timing pulse, at step 635].
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention was made to provide “to log the time D in a first memory” as taught by CATT in the system of HICHEMRAJ, so that it would to provide sensor fusion across multiple devices problematic, which is particularly pronounced in autonomous vehicles and other similar applications, where fusion of data from multiple sensors can be critical in ensuring accurate positional sensing and navigation [see CATT; ¶ 7].
Regarding claim 19, the claim recites the system according to claim 18 to perform the system recited as in claim 2; therefore, claim 19 is rejected along the same rationale that rejected in claim 2.
Regarding claim 25, the claim recites a method to perform the functions of the system recited as in claim 1; therefore, claim 25 is rejected along the same rationale that rejected in claim 1.
Regarding claim 26, the claim recites a method to perform the functions of the system recited as in claim 18; therefore, claim 26 is rejected along the same rationale that rejected in claim 18.
Claims 3-4 and 20-21 are rejected under 35 U.S.C. 103 unpatentable over HICHEMRAJ (CN 110581744) in view of CATT (AU 2023/200522), further in view of Bushnell et al. (US 2016/0299221).
Regarding claim 3, the combined system of HICHEMRAJ and CATT discloses the system according to claim 1, but does not explicitly disclose wherein the delay computation circuitry is to compute the time difference between receiving the first pulse in the second device and sending the second pulse from the second device based on the time B and the time C.
However, Bushnell discloses wherein the delay computation circuitry is to compute the time difference between receiving the first pulse in the second device and sending the second pulse from the second device based on the time B and the time C [see ¶¶ 70, 81; where in the balanced detector 226 is configured to determine/compute the clock offset Δt based on an average of a first time difference between a time when Aircraft A sends a pulse (according to the clock on Aircraft A) and when Aircraft B receives the pulse (according to the clock on Aircraft B) and a second time difference between a time when Aircraft B sends a pulse (according to the clock on Aircraft B) and when Aircraft A receives the pulse (according to the clock on Aircraft A) (see ¶ 44)].
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention was made to provide “clock synchronization circuitry to discipline the first clock of the first device, or a second clock of the second device, responsively to a pulse received by the first device or the second device, respectively, and the computed clock connection delay” as taught by Bushnell in the combined system of HICHEMRAJ and CATT, so that it would to determine distances between the respective platforms and to prevent platform positioning errors due to time differences between the clocks of the respective platforms [see CATT; ¶ 3].
Regarding claim 4, the combined system of HICHEMRAJ and CATT discloses the system according to claim 1, does not explicitly disclose wherein the time difference between receiving the first pulse in the second device and sending the second pulse from the second device is computed based on the time B and the time C, the delay computation circuitry being to receive the computed time difference from the second device.
However, Bushnell discloses wherein the time difference between receiving the first pulse in the second device and sending the second pulse from the second device is computed based on the time B and the time C [see Fig. 1, ¶¶ 22-24; wherein the time difference Δt between receiving the first pulse train 106 in the Aircraft B/second device and sending the second pulse train 108 from the Aircraft B/second device is computed based on the time t.sub.Areceived and the time t.sub.Bsend], the delay computation circuitry being to receive the computed time difference from the second device [see ¶ 25; one of Aircraft A or Aircraft B adjusts an overlap between the respective pulses transmitted by and received at the aircraft to locally adjust the locking of the pulses (see FIG. 3 and ¶¶ 55-56)].
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention was made to provide “wherein the time difference between receiving the first pulse in the second device and sending the second pulse from the second device is computed based on the time B and the time C, the delay computation circuitry being to receive the computed time difference from the second device” as taught by Bushnell in the combined system of HICHEMRAJ and CATT, so that it would to determine distances between the respective platforms and to prevent platform positioning errors due to time differences between the clocks of the respective platforms [see CATT; ¶ 3].
Regarding claims 20-21, the claims recite the system according to claim 19 to perform the system recited as in claims 3-4 respectively; therefore, claims 20-21 are rejected along the same rationale that rejected in claims 3-4 respectively.
Claims 5-9, 10-11, 15-16, and 22-23 are rejected under 35 U.S.C. 103 unpatentable over HICHEMRAJ (CN 110581744) in view of CATT (AU 2023/200522), further in view of WANG et al. (CN 114647179).
Regarding claim 5, the combined system of HICHEMRAJ and CATT discloses the system according to claim 1, but does not explicitly disclose wherein the time difference between receiving the first pulse in the second device and sending the second pulse from the second device is a predetermined time delay based on a hardware configuration of the second device, the delay computation circuitry being to compute the clock connection delay based on the time A, the time D, and the predetermined time delay.
However, WANG discloses
wherein the time difference between receiving the first pulse in the second device and sending the second pulse from the second device is a predetermined time delay based on a hardware configuration of the second device, the delay computation circuitry being to compute the clock connection delay based on the time A, the time D, and the predetermined time delay [page 22 lines 35-40; step S102, main clock device 200 and the clock device 300 periodically perform the first clock time MT1, ST1 and the second clock time MT2, the specific mode of the synchronization of ST2, wherein the period can be preset, also can be adjusted according to the condition in the repeating synchronous process].
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention was made to provide “wherein the time difference between receiving the first pulse in the second device and sending the second pulse from the second device is a predetermined time delay based on a hardware configuration of the second device, the delay computation circuitry being to compute the clock connection delay based on the time A, the time D, and the predetermined time delay” as taught by WANG in the combined system of HICHEMRAJ and CATT, so that it would to eliminate the negative influence of time transition to the time sensitive part of the application system, and ensure that the application system has the time following the real world [see WANG; page 2 lines 26-28].
Regarding claim 6, the combined system of HICHEMRAJ and CATT discloses the system according to claim 5.
HICHEMRAJ further discloses wherein the predetermined time delay is equal to a single clock cycle of a controller of the second device [Fig. 3, page 4 lines 42-45; FIG. 3 shows a timing card using the SyncE signal line 221 to transmit a test signal, and using the SyncE receiving signal line 223 from an embodiment of the return signals from the line card 203. assuming the tracking delay to line card is the pulse emitted by the timing card 209 of half of the round trip time over path 233].
Regarding claim 7, the combined system of HICHEMRAJ and CATT discloses the system according to claim 1, wherein the delay computation circuitry is to repeat the computation of the clock connection delay intermittently yielding multiple clock connection delay results based on other pulses sent by the first device and the second device.
However, WANG discloses
wherein the time difference between receiving the first pulse in the second device and sending the second pulse from the second device is a predetermined time delay based on a hardware configuration of the second device, the delay computation circuitry being to compute the clock connection delay based on the time A, the time D, and the predetermined time delay [page 22 lines 35-40; step S102, main clock device 200 and the clock device 300 periodically perform the first clock time MT1, ST1 and the second clock time MT2, the specific mode of the synchronization of ST2, wherein the period can be preset, also can be adjusted according to the condition in the repeating synchronous process].
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention was made to provide “wherein the time difference between receiving the first pulse in the second device and sending the second pulse from the second device is a predetermined time delay based on a hardware configuration of the second device, the delay computation circuitry being to compute the clock connection delay based on the time A, the time D, and the predetermined time delay” as taught by WANG in the combined system of HICHEMRAJ and CATT, so that it would to eliminate the negative influence of time transition to the time sensitive part of the application system, and ensure that the application system has the time following the real world [see WANG; page 2 lines 26-28].
Regarding claim 8, the combined system of HICHEMRAJ, CATT, and WANG discloses the system according to claim 7.
The combined system of HICHEMRAJ and CATT does not explicitly disclose wherein the delay computation circuitry is to compute an average of the multiple clock connection delay results.
However, WANG discloses wherein the delay computation circuitry is to compute an average of the multiple clock connection delay results [page 24 lines 45-53; the main clock device 200 again sends the second time synchronization request message Xresp2, wherein the message average time delay Pdelay can be calculated by the message average time delay].
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention was made to provide “wherein the delay computation circuitry is to compute an average of the multiple clock connection delay results” as taught by WANG in the combined system of HICHEMRAJ and CATT, so that it would to eliminate the negative influence of time transition to the time sensitive part of the application system, and ensure that the application system has the time following the real world [see WANG; page 2 lines 26-28].
Regarding claim 9, the combined system of HICHEMRAJ and CATT discloses the system according to claim 1, but does not explicitly disclose wherein: the first nPPS output interface is to periodically send clock synchronization pulses at a rate of n pulses per second to the second nPPS input interface via the first clock connection; and the first nPPS output interface is to send, among at least two of the clock synchronization pulses, third pulses of the other pulses, at a rate of m pulses per second, used to yield the multiple clock connection delay results.
However, WANG discloses wherein: the first nPPS output interface is to periodically send clock synchronization pulses at a rate of n pulses per second to the second nPPS input interface via the first clock connection [see Fig. 8, page 19 lines 25-36; : the interface unit 240/(first nPPS output interface) is to periodically send first time synchronization request message Xsyn1/(clock synchronization pulses) at a rate of n pulses per second to the recording interface unit 340/(second nPPS input interface) of the slave clock device 300 via the first clock unit 210 (also see page 20 lines 48-52)]; and the first nPPS output interface is to send, among at least two of the clock synchronization pulses, third pulses of the other pulses, at a rate of m pulses per second, used to yield the multiple clock connection delay results [page 19 lines 37-40 ; the interface unit 240 sent the first time synchronization request message Xsyn1 at TM1/( time A) between second time synchronization request message Xsyn2].
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention was made to provide “wherein: the first nPPS output interface is to periodically send clock synchronization pulses at a rate of n pulses per second to the second nPPS input interface via the first clock connection; and the first nPPS output interface is to send, among at least two of the clock synchronization pulses, third pulses of the other pulses, at a rate of m pulses per second, used to yield the multiple clock connection delay results” as taught by WANG in the combined system of HICHEMRAJ and CATT, so that it would to eliminate the negative influence of time transition to the time sensitive part of the application system, and ensure that the application system has the time following the real world [see WANG; page 2 lines 26-28].
Regarding claim 10, the combined system of HICHEMRAJ and CATT discloses the system according to claim 1, but does not explicitly disclose wherein: the first nPPS output interface is to periodically send clock synchronization pulses at a rate of n pulses per second to the second nPPS input interface via the first clock connection; and the first nPPS output interface is to send the first pulse at the time A between two of the clock synchronization pulses.
However, WANG discloses wherein: the first nPPS output interface is to periodically send clock synchronization pulses at a rate of n pulses per second to the second nPPS input interface via the first clock connection [see Fig. 8, page 19 lines 25-36; : the interface unit 240/(first nPPS output interface) is to periodically send first time synchronization request message Xsyn1/(clock synchronization pulses) at a rate of n pulses per second to the recording interface unit 340/(second nPPS input interface) of the slave clock device 300 via the first clock unit 210 (also see page 20 lines 48-52)]; and the first nPPS output interface is to send the first pulse at the time A between two of the clock synchronization pulses [page 19 lines 37-40 ; the interface unit 240 sent the first time synchronization request message Xsyn1 at TM1/( time A) between second time synchronization request message Xsyn2].
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention was made to provide “wherein: the first nPPS output interface is to periodically send clock synchronization pulses at a rate of n pulses per second to the second nPPS input interface via the first clock connection; and the first nPPS output interface is to send the first pulse at the time A between two of the clock synchronization pulses” as taught by WANG in the combined system of HICHEMRAJ and CATT, so that it would to eliminate the negative influence of time transition to the time sensitive part of the application system, and ensure that the application system has the time following the real world [see WANG; page 2 lines 26-28].
Regarding claim 11, the combined system of HICHEMRAJ and CATT discloses the system according to claim 1, but does not explicitly disclose wherein the delay computation circuitry is to derive the time A from the time D.
However, WANG discloses wherein the delay computation circuitry is to derive the time A from the time D [page 18 lines 28-37, lines 47-50; wherein the time processing unit 330/(delay computation circuitry) is to calculate/derive the time MT1/A from the time MT14/D; also see page 23 lines 39-46; (time difference [delta] T4 between the first main clock time (MT15) and the second main clock time (MT25) included in the first time synchronization request message Xsyn1 is calculated)].
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention was made to provide “wherein the delay computation circuitry is to derive the time A from the time D” as taught by WANG in the combined system of HICHEMRAJ and CATT, so that it would to eliminate the negative influence of time transition to the time sensitive part of the application system, and ensure that the application system has the time following the real world [see WANG; page 2 lines 26-28].
Regarding claim 15, the combined system of HICHEMRAJ and CATT discloses the system according to claim 1, further comprising
“the second device, wherein: the second nPPS input interface is to: receive the first pulse at the time B; and log the time B in a second memory” as set forth in claim 13.
The combined system of HICHEMRAJ and CATT does not explicitly disclose the second device includes a controller to detect receipt of the first pulse and cause the second nPPS output interface to send the second pulse to the first device via the second clock connection “within a predetermined time delay of detecting the receipt of the first pulse”.
However, WANG discloses
the second device includes a controller to detect receipt of the first pulse and cause the second nPPS output interface to send the second pulse to the first device via the second clock connection within a predetermined time delay of detecting the receipt of the first pulse [page 22 lines 35-40; step S102, main clock device 200 and the clock device 300 periodically perform the first clock time MT1, ST1 and the second clock time MT2, the specific mode of the synchronization of ST2, wherein the period can be preset, also can be adjusted according to the condition in the repeating synchronous process]
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention was made to provide “the second device includes a controller to detect receipt of the first pulse and cause the second nPPS output interface to send the second pulse to the first device via the second clock connection within a predetermined time delay of detecting the receipt of the first pulse” as taught by WANG in the combined system of HICHEMRAJ and CATT, so that it would to eliminate the negative influence of time transition to the time sensitive part of the application system, and ensure that the application system has the time following the real world [see WANG; page 2 lines 26-28].
Regarding claim 16, the combined system of HICHEMRAJ and CATT discloses the system according to claim 15.
HICHEMRAJ further discloses wherein the predetermined time delay is equal to a single clock cycle of the controller [Fig. 3, page 4 lines 42-45; FIG. 3 shows a timing card using the SyncE signal line 221 to transmit a test signal, and using the SyncE receiving signal line 223 from an embodiment of the return signals from the line card 203. assuming the tracking delay to line card is the pulse emitted by the timing card 209 of half of the round trip time over path 233].
Regarding claims 22-23, the claims recite the system according to claim 18 to perform the system recited as in claims 15-16 respectively; therefore, claims 22-23 are rejected along the same rationale that rejected in claims 15-16 respectively
Claims 14, 17, and 24 are rejected under 35 U.S.C. 103 unpatentable over HICHEMRAJ (CN 110581744) in view of CATT (AU 2023/200522), further in view of ARONKYTÖ et al. (US 2023/0189242).
Regarding claim 14, the combined system of HICHEMRAJ and CATT discloses the system according to claim 13, does not explicitly disclose wherein the controller is to minimize a difference between time B and time C.
However, ARONKYTÖ discloses wherein the controller is to minimize a difference between time B and time C [¶ 137; the marker measurement time period T.sub.meas may be reduced and the calculating of the time difference Δt (wherein the Δt=±[(t.sub.2−t.sub.3)−(t.sub.4−t.sub.1)]/2)].
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention was made to provide “wherein the controller is to minimize a difference between time B and time C” as taught by ARONKYTÖ in the combined system of HICHEMRAJ and CATT, so that it would to enable improving the accuracy of the existing solutions, such as NTP or PTP based synchronization, or alternatively enable synchronization of stand-alone clocks [see ARONKYTÖ; ¶ 43].
Regarding claim 17, the combined system of HICHEMRAJ and CATT discloses the system according to claim 1, does not explicitly disclose further comprising the second device, wherein the second nPPS output interface is to send the second pulse at time C, which is before time B.
However, ARONKYTÖ discloses further comprising the second device, wherein the second nPPS output interface is to send the second pulse at time C, which is before time B [Fig. 6B¶ 131; the receive-side measurement unit of a radio node measures a different marker from what the transmit-side measurement unit measures, whrein the receive-side measurement unit measures a false one, because the false marker arrives before the correct marker].
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention was made to provide “further comprising the second device, wherein the second nPPS output interface is to send the second pulse at time C, which is before time B” as taught by ARONKYTÖ in the combined system of HICHEMRAJ and CATT, so that it would to enable improving the accuracy of the existing solutions, such as NTP or PTP based synchronization, or alternatively enable synchronization of stand-alone clocks [see ARONKYTÖ; ¶ 43].
Regarding claim 24, the claim recites the system according to claim 18 to perform the system recited as in claim 14; therefore, claim 24 is rejected along the same rationale that rejected in claim 14.
Conclusion
In additional to references cited that are used for rejection as set forth above, LEI et al. (CN 115189796) is also considered as relevant prior arts for rejection of in claims 1, 18, and 25-26 (see Figs 2-4).
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/PHONG LA/Primary Examiner, Art Unit 2469