DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Response to Amendments
Applicant's response of 08/07/2026 has been acknowledged. Claims 1-4, 9-10, 12-25, and 27-29 have been amended. No new matter has been added.
This office action considers claims 1-29 pending for prosecution and are examined on their merits.
Response to Arguments
Applicant’s arguments filed 08/07/2026 with respect to the rejection of claims 1-3, 5, 8-9, 12-13, 15-16, and 24-29 have been fully considered but are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
Claims 1-3, 5, 8-9, 12-13, 15-16, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Tamura et al. (US 20200098747 A1 – hereinafter Tamura-747) in view of Tamura et al. (US 20200035817 A1 – hereinafter Tamura-817) and Yoshida et al. (US 20210234027 A1 – hereinafter Yoshida).
Regarding independent claim 1, Tamura-747 teaches:
(Currently Amended) A semiconductor device (200 – Fig. 1 – [0034] –
“semiconductor device 200”) comprising a semiconductor substrate (10 – Fig. 2 – [0034] – “semiconductor substrate 10”) including a transistor portion (60 – Fig. 2 – [0036] – “IGBT regions 60 are exemplary transistor regions”) and a diode portion (80 – Fig. 2 – [0036] – “FWD regions 80 are exemplary diode regions”), wherein the semiconductor substrate (10) includes:
a plurality of trench portions (40 and 50 – Fig. 2 – [0042] – “semiconductor substrate 10 has: gate trench portions 40; the dummy trench portions 50”) provided on a front surface (12 – Fig. 2 – [0041] – “front surface 12”) of the semiconductor substrate (10) and including a gate trench portion (40 – Fig. 2 - [0042] – “gate trench portions 40”);
a drift region (28 – Fig. 2 – [0042] – “N− type drift region 28”) of a first conductivity type (N – [0042] – “N type is an exemplary first conductivity-type”) provided in the semiconductor substrate (10);
a base region (24 – Fig. 2 – [0042] – “P− type base region 24”) of a second conductivity type (P – [0042] – “P type is an exemplary second conductivity-type”) provided above the drift region (28) in the transistor portion (70 – Fig. 2 shows this);
a[[n]] plurality of emitter regions (22 – Fig. 3 – [0038] – “N+ type emitter region 22”) of the first conductivity type (N) provided on the front surface (12) of the semiconductor substrate (10) and each having a doping concentration higher ([0042] – “N and P with symbols + and − mean that the carrier concentrations are higher and lower than N and P without those symbols) than that of the drift region (28 – N-);
a plurality of contact regions (25 – Fig. 3 – [0038] – “P+ type contact region 25”) of the second conductivity type (P) provided on the front surface (12) of the semiconductor substrate (10) and each having a doping concentration higher (25 – P+) than that of the base region (24 – P-); and
a[[n]] plurality of anode regions of the second conductivity type provided above the drift region in the diode portion and each having a doping concentration lower than that of the plurality of contact regions,
wherein the transistor portion includes a main region provided to be spaced apart from the diode portion and a boundary region provided to be adjacent to the diode portion,
wherein the boundary region includes a first boundary portion including the plurality of emitter regions and a second boundary portion including the plurality of anode regions and at least one of the plurality of contact regions, and
wherein the first boundary portion includes at least one injection suppression region of the second conductivity type between at least two of the plurality of emitter regions in a trench extending direction to suppress an injection of a carrier of the second conductivity type.
Tamura-747 does not expressly disclose the other limitations of claim 1.
However, in an analogous art, Tamura-817 teaches
a[[n]] plurality of anode regions (14 – Fig. 5 – [0061] – “base region 14 is the second conductivity type (P.sub.−-type) having a doping concentration lower than that of well region 11. The well region 11 is the second conductivity type (P.sub.+-type)” – this corresponds to the anode region) of the second conductivity type (P – [0046] – “second conductivity type is the P-type”) provided above the drift region (18 – Fig. 2A – [0050] – “drift region 18”) in the diode portion (80 – Fig. 5 – [0095] – “diode portion 80”) and each having a doping concentration lower (14 – P-) than that of the plurality of contact regions (15 – Fig. 6 – [0061] – “P+-type contact region 15”),
wherein the transistor portion (70 – Fig. 1B – [0050] – “transistor portion 70”) includes a main region (Fig. 1B annotated, see below – hereinafter ‘MR’) provided to be spaced apart from the diode portion (80 – Fig. 1B – [0050] – “diode portion 80”) and a boundary region (Fig. 1B annotated, see below – [0057] – “the transistor portion 70, the diode portion 80, and the boundary portion 92. The semiconductor device 100 may further include at least one of a extraction portion 90 and a suppression portion 94” – hereinafter ‘BR’) provided to be adjacent to the diode portion (80),
wherein the boundary region (BR) includes a first boundary portion (92A – Fig. 20 – [0180] – “boundary portion 92A”) including the plurality of emitter regions (12 – Fig. 20 – [0061] – “N.sub.+-type emitter region 12”) and a second boundary portion (94 – Fig. 20 – [0057] – “suppression portion 94”) including the plurality of anode regions (14) and at least one of the plurality of contact regions (15), and
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wherein the first boundary portion (92).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the region structure as taught by Tamura-817 into Tamura-747.
An ordinary artisan would have been motivated to use the known technique of Tamura-817 in the manner set forth above to produce the predictable result [0007] – “The semiconductor device preferably has good characteristics of withstand voltage and the like.”
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Tamura-747 and Tamura-817 do not expressly disclose the other limitations of claim 1.
However, in an analogous art, Yoshida teaches
at least one injection suppression region (15 – Fig. 4 – [0070] – “the hole injection from the contact regions 15 can be suppressed” – this corresponds to the injection suppression region) of the second conductivity type (P+ - Fig. 4 – [0065] – “contact regions 15 of this example are of a P+ type with a higher doping concentration than the base region 14”) between at least two of the plurality of emitter regions (12 – Fig. 4 – [0065] – “Contact regions 15 and emitter regions 12 are provided on the upper surface of the base region 14”) in a trench extending direction (Y – Fig. 4 – [0068] – “The base regions 14 may be provided to sandwich the contact region 15 in the Y axis direction on the upper surface of the mesa portion 61”) to suppress an injection of a carrier ([0131] – “the injection of carriers from the contact regions 15 being suppressed”) of the second conductivity type (it is interpreted that the carrier is of the second conductivity type due to the similarity of structure shown in Fig. 4 and the operability of the device).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the injection suppression region structure as taught by Yoshida into Tamura-747 and Tamura-817.
An ordinary artisan would have been motivated to use the known technique of Yoshida in the manner set forth above to produce the predictable result [0070] – “The trench contact 54 penetrates the contact regions 15 in the depth direction (the Z axis direction). That is, by providing the trench contact 54, the volume of the contact regions 15 is reduced. In this way, when the gate of the transistor portion 70 is turned to be in the off-state and diode operations start, the hole injection from the contact regions 15 can be suppressed. Therefore, the reverse recovery loss in the diode portion 80 can be reduced.”
Regarding claim 2, Tamura-747 as modified by Tamura-817, Yoshida, teaches claim 1 from which claim 2 depends. Tamura-747 and Tamura-817 do not expressly disclose the limitations of claim 2.
However, in an analogous art, Yoshida teaches
(Currently Amended) The semiconductor device according to claim 1,
wherein an averaged doping concentration of the at least one injection suppression region (15 – [0065] – “contact regions 15 of this example are of a P+ type with a higher doping concentration than the base region 14”) is higher than the doping concentration of the base region (14 – Fig. 4 – [0065] – “contact regions 15 of this example are of a P+ type with a higher doping concentration than the base region 14”) and lower than the doping concentration of the at least one contact regions ([0041] – “where the doping concentration is approximately uniform in a region where the donor or acceptor exists or the like, the average value of the doping concentration may be the doping concentration in the region”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the injection suppression region structure as taught by Yoshida into Tamura-747 and Tamura-817.
An ordinary artisan would have been motivated to use the known technique of Yoshida in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 3, Tamura-747 as modified by Tamura-817, Yoshida, teaches claim 1 from which claim 3 depends. Tamura-747 and Tamura-817 do not expressly disclose the limitations of claim 3.
However, in an analogous art, Yoshida teaches
(Currently Amended) The semiconductor device according to claim 1,
wherein the injection suppression region (15) includes the base region (14) and at least one of the contact regions (15 – this is a design choice not to designate the region as two regions).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the injection suppression region structure as taught by Yoshida into Tamura-747 and Tamura-817.
An ordinary artisan would have been motivated to use the known technique of Yoshida in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 5, Tamura-747 as modified by Tamura-817, Yoshida, teaches claim 1 from which claim 5 depends. Tamura-747 further teaches
(Original) The semiconductor device according to claim 1, wherein a
width of the boundary region (70) in a trench array direction (Y – Fig. 2 – [0044] – “The gate trench portions 40, and dummy trench portions 50 are provided separately from each other at predetermined intervals in the Y-axis direction”) is equal to or greater than 50 μm and equal to or smaller than 200 μm ([0052] – “The width W of the boundary region 70 in the Y-axis direction (i.e., the length from an end portion 72 adjacent to the FWD region 80 to an end portion 74 adjacent to the IGBT region 60) may be 10 μm to 100 μm, inclusive, and may be 50 μm to 100 μm, inclusive”).
Regarding claim 8, Tamura-747 as modified by Tamura-817, Yoshida, teaches claim 1 from which claim 8 depends. Tamura-747 and Yoshida do not expressly disclose the limitations of claim 8.
However, in an analogous art, Tamura-817 teaches
(Original) The semiconductor device according to claim 1, wherein the first
boundary portion (92) includes the gate trench portion (40 – Fig. 1B – [0061] – “”gate trench portion 40”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the boundary and trench structure as taught by Tamura-817 into Tamura-747 and Yoshida.
An ordinary artisan would have been motivated to use the known technique of Tamura-817 in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 9, Tamura-747 as modified by Tamura-817, Yoshida, teaches claim 1 from which claim 9 depends. Tamura-747 further teaches
(Currently Amended) The semiconductor device according to claim
1, wherein at least some of the plurality of contact region (25 – Fig. 8 – [0030] – “contact region 25”) in the second boundary portion (70 – Fig. 8 – [0030] – “boundary region 70”) are (25) discretely provided in the trench extending direction (Y – Fig. 8 shows this).
Regarding claim 12, Tamura-747 as modified by Tamura-817, Yoshida, teaches claim 1 from which claim 12 depends. Tamura-747 and Yoshida do not expressly disclose the limitations of claim 12.
However, in an analogous art, Tamura-817 teaches
(Currently Amended) The semiconductor device according to claim 1,
wherein;
the plurality of trench portions (30, 40 – Fig. 1B – [0061] – “gate
trench portion 40, a dummy trench portion 30”) includes a dummy trench portion (30 – Fig. 1B – [0061] – “a dummy trench portion 30”)[[,]]; and
the second boundary portion (94 – Fig. 1B – [0057] – “suppression portion 94”
– this corresponds to the secondary boundary portion) includes the dummy trench portion (30) and does not include the gate trench portion (40 – Fig. 1B shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the trench and boundary region structure as taught by Tamura-817 into Tamura-747 and Yoshida.
An ordinary artisan would have been motivated to use the known technique of Tamura-817 in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 13, Tamura-747 as modified by Tamura-817, Yoshida, teaches claim 1 from which claim 13 depends. Tamura-747 and Tamura-817 do not expressly disclose the limitations of claim 13.
However, in an analogous art, Yoshida teaches
(Currently Amended) The semiconductor device according to claim 1,
wherein;
at least some of the emitter regions (12 – Fig – [0056] – “emitter region 12”)
are (Y)[[,]]; and
the at least one injection suppression region (15) includes a plurality of injection suppression regions (15) provided between the plurality of emitter regions (12) in the trench extending direction (Fig. 4 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the emitter region structure as taught by Yoshida into Tamura-747 and Tamura-817.
An ordinary artisan would have been motivated to use the known technique of Yoshida in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 15, Tamura-747 as modified by Tamura-817, Yoshida, teaches claim 2 from which claim 15 depends. Tamura-747 and Tamura-817 do not expressly disclose the limitations of claim 15.
However, in an analogous art, Yoshida teaches
(Currently Amended) The semiconductor device according to claim 2,
wherein each end of the base region (14) in the injection suppression region (95) (15) is at least one of the plurality of contact regions (15) in the trench extending direction (Y).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the emitter region structure as taught by Yoshida into Tamura-747 and Tamura-817.
An ordinary artisan would have been motivated to use the known technique of Yoshida in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 16, Tamura-747 as modified by Tamura-817, Yoshida, teaches claim 5 from which claim 16 depends. Tamura-747 does not expressly disclose the limitations of claim 15.
However, in an analogous art, Tamura-817 teaches
the first boundary portion (92 – Fig. 1B – [0057] – “boundary portion 92”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the region structure as taught by Tamura-817 into Tamura-747.
An ordinary artisan would have been motivated to use the known technique of Tamura-817 in the manner set forth above to produce the predictable result as stated above in claim 1.
However, in an analogous art, Yoshida teaches
(Currently Amended) The semiconductor device according to claim 5,
wherein on the front surface (21 – Fig. 3 – [0078] – “emitter electrode 52 may be in contact with the upper surface 21 of the semiconductor substrate 10 in each mesa portion”) of the semiconductor substrate (10), each at least one of the plurality of emitter regions (12) in the first boundary portion in the trench extending direction (Y) are in contact with at least one of the plurality of contact regions (15) in the injection suppression region (15).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the emitter region structure as taught by Yoshida into Tamura-747 and Tamura-817.
An ordinary artisan would have been motivated to use the known technique of Yoshida in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 24, Tamura-747 as modified by Tamura-817, Yoshida, teaches claim 1 from which claim 24 depends. Tamura-747 and Yoshida do not expressly disclose the limitations of claim 24.
However, in an analogous art, Tamura-817 teaches
(Currently Amended) The semiconductor device according to claim 1,
wherein the diode portion (80 – [0165] – “diode portion 80 includes the emitter region 12 and the contact region 15 in the mesa portion 60-5”) includes at least one of the plurality of contact regions (15 – [0165] – “diode portion 80 includes the emitter region 12 and the contact region 15 in the mesa portion 60-5”) ing in the trench extending direction (Y – Fig. 16 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the diode and contact region structure as taught by Tamura-817 into Tamura-747 and Yoshida.
An ordinary artisan would have been motivated to use the known technique of Tamura-817 in the manner set forth above to produce the predictable result as stated above in claim 1.
Claims 7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Tamura-747 in view of Tamura-817, Yoshida, and Yokoyama et al. (WO 2021251011 A1 – hereinafter Yokoyama).
Regarding claim 7, Tamura-747 as modified by Tamura-817, Yoshida, teaches claim 1 from which claim 7 depends. Tamura-747, Tamura-817, and Yoshida do not expressly disclose the limitations of claim 7.
However, in an analogous art, Yokoyama teaches
(Original) The semiconductor device according to claim 1, wherein a width
of the first boundary portion (74 – Fig. 1A – [0114] – “boundary region 74”) in a trench array direction ([0114] – “X-axis direction”) is equal to or greater than 50 μm and equal to or smaller than 150 μm ([0114] – “The width of the boundary region 74 in the X-axis direction may be 50 μm or more and 150 μm
or less”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the boundary width as taught by Yokoyama into Tamura-747, Tamura-817, and Yoshida.
An ordinary artisan would have been motivated to use the known technique of Yokoyama in the manner set forth above to produce the predictable result of [0113] – “the threshold voltage of the boundary region 74 can be made higher than that of the transistor section 70, and the decrease in threshold voltage due to an increase in tunnel current can be suppressed.”
Regarding claim 17, Tamura-747 as modified by Tamura-817, Yoshida, teaches claim 15 from which claim 17 depends. Tamura-747, Tamura-817, and Yoshida do not expressly disclose the limitations of claim 17.
However, in an analogous art, Yokoyama teaches
(Currently Amended) The semiconductor device according to claim 15,
wherein at least one of the plurality of contact regions (17 – Fig. 1B – [0068] – “plug region 17 is a second conductivity type region with a higher doping concentration than the withdrawal region 15. In this example, the plug region 17 is of type P++”) in the second boundary portion (74 – Fig. 1B – [0084] – “boundary region 74”) s from one trench portion (54 – Fig. 1B – [0067] – “contact hole 54”) to another opposing trench portion in a trench array direction (X – Fig. 1B shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the contact region structure as taught by Yokoyama into Tamura-747, Tamura-817, and Yoshida.
An ordinary artisan would have been motivated to use the known technique of Yokoyama in the manner set forth above to produce the predictable result of [0068] – “this improves the contact resistance between the barrier metal and the extraction region 15.”
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Tamura-747 in view of Tamura-817, Yoshida, and Murakawa et al. (US 20190252534 A1 – hereinafter Murakawa).
Regarding claim 10, Tamura-747 as modified by Tamura-817, Yoshida, teaches claim 9 from which claim 10 depends. Tamura-747, Tamura-817, and Yoshida do not expressly disclose the limitations of claim 10.
However, in an analogous art, Murakawa teaches
(Currently Amended) The semiconductor device according to claim 9,
wherein on the front surface (10a – Fig. 2 – [0039] – “first surface 10a of the semiconductor substrate 10”) of the semiconductor substrate (10 – Fig. 2 – [0039] – “substrate 10”), an area ratio of the plurality of contact regions (15c – Fig. 2 – [0040] – “contact region 15c”) in the second boundary portion (1c – Fig. 2 – [0040] – “the boundary region 1c”) is smaller than an area ratio of the plurality of contact regions (15c) in the diode portion (1b – Fig. 2 – [0040] – “the ohmic contact area ratio of the boundary region 1c are made smaller than those in the diode region 1b”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the contact region structure as taught by Murakawa into Tamura-747, Tamura-817, and Yoshida.
An ordinary artisan would have been motivated to use the known technique of Murakawa in the manner set forth above to produce the predictable result of [0040] – “By changing formation area of the second contact region 15b and the third contact region 15c, the formation ratio of high concentration P-type layer per unit area and the ohmic contact area ratio are changed.”
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Tamura-747 in view of Tamura-817, Yoshida, and Tamura et al. (US 20210050345 A1 – hereinafter Tamura-345).
Regarding claim 25, Tamura-747 as modified by Tamura-817, Yoshida, teaches claim 1 from which claim 25 depends. Tamura-747, Tamura-817, and Yoshida do not expressly disclose the limitations of claim 25.
However, in an analogous art, Tamura-345 teaches
(Currently Amended) The semiconductor device according to claim 1,
wherein the doping concentration of at least one of the plurality of contact regions is equal to or greater than 1E18 cm-3 and equal to or smaller than 1E21 cm-3 ([0089] – “The doping concentration of the contact region 84 may be 1E18 cm.sup.−3 or higher, or 1E20 cm.sup.−3 or lower”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the contact region structure as taught by Tamura-345 into Tamura-747, Tamura-817, and Yoshida.
An ordinary artisan would have been motivated to use the known technique of Tamura-345 in the manner set forth above to produce the predictable result [0091] – “to suppress the injection amount of holes even when the contact region 84 is included.”
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Tamura-747 in view of Tamura-817, Yoshida, and Berglund et al. (US 20180145158 A1 – hereinafter Berglund).
Regarding claim 26, Tamura-747 as modified by Tamura-817, Yoshida, teaches claim 1 from which claim 26 depends. Tamura-747, Tamura-817, and Yoshida do not expressly disclose the limitations of claim 26.
However, in an analogous art, Berglund teaches
(Original) The semiconductor device according to claim 1, wherein the
doping concentration of the base region is equal to or greater than 1E16 cm-3 and equal to or smaller than 1E18 cm-3 ([0076] – “The doping concentration of the emitter region for a typical transistor may be in the range of 1e18 cm.sup.−3 to 1e20 cm.sup.−3, the base region concentration may be in the range 1e16 cm .sup.−3 to 1e18 cis.sup.−3”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the base region structure as taught by Berglund into Tamura-747, Tamura-817, and Yoshida.
An ordinary artisan would have been motivated to use the known technique of Berglund in the manner set forth above to produce the predictable result [0029] – “to lower the resistance in the connection between an active part of the collector region beneath the base region and the first electrically conductive part of the collector terminal on the major surface of the substrate.”
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Tamura-747 in view of Tamura-817, Yoshida, and Harada et a. (US 20200161460 A1 – hereinafter Harada).
Regarding claim 27, Tamura-747 as modified by Tamura-817, Yoshida, teaches claim 1 from which claim 27 depends. Tamura-747, Tamura-817, and Yoshida do not expressly disclose the limitations of claim 27.
However, in an analogous art, Harada teaches
(Currently Amended) The semiconductor device according to claim 1,
wherein the doping concentration of at least one of the plurality of anode regions is the same as the doping concentration of the base region ([0055] – “the anode region 13 and the base region 14 have the same P-type dopant concentration”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the doping structure as taught by Harada into Tamura-747, Tamura-817, and Yoshida.
An ordinary artisan would have been motivated to use the known technique of Harada in the manner set forth above to produce the predictable result [0011] – “to prevent a decrease in the breakdown withstand capability in an FWD region.”
Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over Tamura-747 in view of Tamura-817, Yoshida, and Mitsuzuka et al. (US 20200091329 A1 – hereinafter Mitsuzuka).
Regarding claim 28, Tamura-747 as modified by Tamura-817, Yoshida, teaches claim 1 from which claim 28 depends. Tamura-747, Tamura-817, and Yoshida do not expressly disclose the limitations of claim 28.
However, in an analogous art, Mitsuzuka teaches
(Currently Amended) The semiconductor device according to claim 1,
wherein the doping concentration of at least one of the plurality of anode regions wherein the doping concentration of the anode region is lower than the doping concentration of the base region ([0014] – “The doping concentration of the anode region may be lower than the doping concentration of the base region”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the doping structure as taught by Mitsuzuka into Tamura-747, Tamura-817, and Yoshida.
An ordinary artisan would have been motivated to use the known technique of Mitsuzuka in the manner set forth above to produce the predictable result [0007] – “to improve the conduction characteristics of the transistor portion and the diode portion.”
Claim 29 is rejected under 35 U.S.C. 103 as being unpatentable over Tamura-747 in view of Tamura-817, Yoshida, and Mitsuzuka et al. (US 20200335497 A1 – hereinafter Mitsuzuka-497).
Regarding claim 29, Tamura-747 as modified by Tamura-817, Yoshida, teaches claim 1 from which claim 29 depends. Tamura-747, Tamura-817, and Yoshida do not expressly disclose the limitations of claim 29.
However, in an analogous art, Mitsuzuka-497 teaches
(Original) The semiconductor device according to claim 1, wherein the
semiconductor substrate is not provided with a lifetime control region including a lifetime killer in a front surface side compared to a center in a depth direction of the semiconductor substrate ([0128] – “in an example where the upper surface side lifetime control region 92 is not provided, the threshold of the gate structure portion 46 is 6 V or more and 6.5 V or less”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the lack of a lifetime control as taught by Mitsuzuka-497 into Tamura-747, Tamura-817, and Yoshida.
An ordinary artisan would have been motivated to use the known technique of Mitsuzuka-497 in the manner set forth above to produce the predictable result [0011] – “that a dynamic characteristic such as a snapback phenomenon is improved” by changing the threshold voltage drop.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Allowable Subject Matter
Claims 4, 6, 11, 14, and 18-23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 4, prior art of record fails to teach or suggest wherein
on the front surface of the semiconductor substrate, an area ratio of the
contact region in the injection suppression region is equal to or greater than 5% and equal to or smaller than 80% of an area ratio of the contact region in the main region.
Claim 14 depends on claim 4 and therefore would be allowable if claim 4 is rewritten.
Regarding claim 6, prior art of record fails to teach or suggest wherein
a width of the boundary region in a trench array direction is equal to or greater than 0.5 times and equal to or smaller than twice a thickness of the semiconductor substrate.
Regarding claim 11, prior art of record fails to teach or suggest wherein
a width of the second boundary portion in a trench array direction s equal to or greater than 20 μm and equal to or smaller than 100 μm.
Regarding claim 18, prior art of record fails to teach or suggest
wherein on the front surface of the semiconductor substrate, the injection
suppression region includes a first region including the contact region provided to extend from one trench portion to the other opposing trench portion, and
the first region is provided to be in contact with the emitter region.
Claim 19 depends on claim 18 and therefore would be allowable if claim 18 is rewritten.
Regarding claim 20, prior art of record fails to teach or suggest wherein
on the front surface of the semiconductor substrate, the injection suppression region includes a third region including the base region provided to extend from one trench portion to the other opposing trench portion.
Regarding claim 21, prior art of record fails to teach or suggest wherein
a width of the emitter region in the first boundary portion in the trench
extending direction is smaller than a width of the emitter region in the main region in the trench extending direction.
Claims 22-23 depends on claim 21 and therefore would be allowable if claim 21 is rewritten.
Pertinent Art
For the benefits of the Applicant, US 20190051739 A1 is cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. These references fail to disclose the combination of limitations including emitter region width.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the
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/GRA/
Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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